TWI263279B - Semiconductor device processing - Google Patents

Abstract

A process for manufacturing a semiconductor device of the trench variety with reduced feature sizes and improved characteristics which process includes forming a termination structure having a field oxide disposed in a recess below the surface of the semiconductor die in which the active elements of the device are formed, and forming source regions after the major thermal steps have been performed.

Description

1263279 玫,发明说明: Related Applications This application is based on U.S. Provisional Application Serial No. 60/415,302, filed on Sep. 30, 2002, entitled <RTI ID=0.0> A recent source of self-alignment of crystals (Trench MOSFETs), and U.S. Provisional Application No. 60/444.064, dated January 29, 2003, entitled "Traffated Metal Oxides for DC-DC Converter Applications Semiconductor field effect transistor (Trench MOSFET) technology, and advocates its interests, which is claimed herein. [Technical Field] The present invention relates to a semiconductor device processing method. 3 BACKGROUND OF THE INVENTION More and more demand for more efficient power supplies and electronic devices that last longer than 15 battery power has become more efficient in power management systems, one of the engineers' greatest challenge areas. Discrete power devices, such as electrically driven metal-oxide-semiconductor field-effect transistors used in power management systems, continue to drive manufacturers 20 device with lower ON-resistance, lower thyristor charge and lower current supply capability. A method according to the invention significantly reduces the size of the features in the electrical device, thus resulting in a reduction Conducting path impedance, reducing gate charge, and increasing current carrying capability. As a result, devices fabricated in accordance with the present invention, such as electrically driven metal oxide semiconductor field effect transistors, can be used in 1263279 in back frequency applications, such as 丨 million hertz There is no undue heat generation. The device manufactured according to the present invention can exhibit improved characteristics in power conversion. The electrically driven metal oxide half-conductor field effect transistor fabricated in accordance with an embodiment of the present invention is a trench. The trench-changing metal oxide semiconductor field effect device has a plurality of trenches, each of which supports a gate structure, and each of which is grown on a monolithic semiconductor substrate. Formed in the epitaxiai iayer. The terminal structure is disposed around the active area of the I-position. The termination structure 10 is a recess formed around the active area and includes a field oxide layer deposited on the surface of the recess, a conductive layer deposited on the field oxide, and a low temperature oxide formation Above the conductive layer, a contact layer may be formed over the low temperature oxide and connected to the conductive layer of the termination structure by the low temperature oxide. 15 The termination structure can significantly reduce the electric field clustered at the terminal Therefore, the implantation does not include the breakdown voltage of the device and the strong guide ring. In the case of a die in a DPAK, the general snow energy (aValanChe energy) for the terminal structure is 1 joule (J). The field oxide in the termination structure, for example, is grown using a local oxidation isolation (LOCOS) program after the terminal 20 recess has been etched. Since the field oxide is represented below the top of the die, wafer flatness during the activation trench lithography stage is greatly improved. Many improved wafer surface slow flatness in the trench lithography stage can further reduce the trench width by as much as 2 G%. For example, the reduction in size may increase the density of the 1263279 trenches, thereby increasing the channel density while maintaining a low gate charge, especially Qgd and Qswitch. To increase the performance of the device, the depth of the channels may also be reduced. A procedure in accordance with the present invention includes forming a source region after the high temperature step has been performed. As a result, the size of the source region can be minimized, which makes it possible to reduce the depth of the channel region, thereby shortening the channel in the device. These shorter channels in turn improve the on-resistance of the device. In addition, compared to prior art devices, shorter channels require a relatively thin epitaxial layer, thereby reducing the cost of the device, and further reducing the on-resistance by shortening the common conduction region of the device by 10. . A program in accordance with the present invention includes the feature of defining a terminal recess and an active region trench with a nitride hard mask; implanting the channel dopant into the epitaxial layer through a spacer oxide; The bottom of the active region trenches b form a thick oxide; and a source is formed after the lion is formed.

Other features and advantages of the present invention will become apparent from the following description of the invention and the accompanying drawings. The present invention relates to a method for fabricating a semiconductor device comprising: • Q. • a semiconductor die providing a semiconducting material having a first conductive channel receiving layer; a receiving layer in the channel Forming a layer of an oxidant resist material; forming a trench in the channel receiving layer in a region of the channel receiving layer; 1263279 forming a terminal recess around the trenches, the terminal recess having a half An exposed surface of the electrically conductive material; a further layer of oxidizing resist material is formed on the sidewalls and the bottom of the trenches; and 5 an oxide layer is grown on the exposed surface of the terminal recess. The present invention relates to a method for fabricating a metal oxide semiconductor gated semiconductor conversion device, comprising: providing a semiconductor die having a first conductivity channel receiving region; forming a second conduction in the channel receiving region a channel region; 10 forming at least one trench in the semiconductor die extending through the channel region; forming a gate structure in the at least one trench; and forming the gate structure in the channel region A first conductive conductive region is formed adjacent each side of the trench. BRIEF DESCRIPTION OF THE DRAWINGS Figure la is a cross-sectional view showing a portion of a semiconductor device in accordance with the present invention. Figure lb shows a cross-sectional illustration of a portion of another embodiment of a semiconductor device in accordance with the present invention. 20 Figures 2a-2u illustrate a procedure in accordance with the present invention. Figures 3a-3h illustrate a procedure in accordance with another embodiment of the present invention. L. Embodiment 3 DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT Referring to FIG. 1a, a semiconductor device according to the present invention is formed at 1263279, which includes a first conductivity type of a non-polar region and a lightly doped conductive pattern. Shi Xijing's teachings of the channel region 12 of the dopant. The semiconductor skirt according to the present invention includes a plurality of trenches 14 extending from the upper surface of the die 5 to the drain region 10 10 15 . The trench 14 has a conductive material such as a doped polycrystalline layer deposited therein to form the idle electrode 16. The idle electrode 16 is insulated by the oxide-channel region. Oxidation (4) is formed on the side walls of each of the grooves. It should be noted that thick oxide 15 is formed at the bottom of each trench. The semiconductor device in accordance with the present invention also includes a self-aligned source region 20' disposed on the opposite side of each trench 14 and extending to a predetermined depth less than the depth of the channel region 12. The self-aligned source region 20 is doped with the dopant of the drain region 1__. Each of the electrode electrodes 16 has a gate insulating layer 22 disposed on its upper surface. Disposed on the upper surface of each of the closed insulating layers 22 is a layer of low temperature insulating material 24. Extending from the ± surface of the pass region 12 to a bead that is preferably smaller than the adjacent source region: each adjacent source region 2〇 is a vibration having the same conductivity as the material in the channel region L The high-doped impurity contact region of the impurity doping = the highly doped contact region 26 is the bottom of the concave land formed on the upper surface of the crystal grain 5. A source contact layer 28, typically composed of an aluminum alloy, is disposed over the upper surface of the wafer, in ohmic contact with the source region 2A and the contact region 26, thereby shorting the source region 2G and the contact region 26. A drain contact layer 30, possibly composed of a trimetal or two other contact metal suitable for soldering, is disposed over the die to the free surface of the source contact layer 28 and is in ohmic contact with the drain region 10. In the semiconductor according to the second embodiment, as shown in Fig. 1b, a high 20 Ϊ 263279 impurity contact region 26 is formed on the upper surface of the crystal grain 5. The first and fifth figures show only a portion of a semiconductor device fabricated in accordance with the present invention. Those skilled in the art will appreciate that in an actual semiconductor device, the/tongue region will contain a number of grooves 14. 5 The semiconductor device shown in Figure 1a*lb is a trench variation. The I-position of the trench pattern is operated by applying a voltage to its gate electrode 16 to invert the regions of the adjacent oxide 18 such that it is electrically connected to its source region 2 and its drain region 10. The semiconductor device shown in the figure and the figure is a channel device. By inverting the polarity of the dopants in each region, a P-channel device can be obtained in each of the cases. The die 5 in the preferred embodiment is comprised of a single stone substrate 2 having a stray layer over the upper surface of the crucible. The trench Μ as described above is formed in the epitaxial layer. Here, the description of the drain region 10 means a drift region 14 disposed between the substrate 2 and the channel region 12. It will be appreciated by those skilled in the art that semiconductor dies that do not deviate from other materials or structures of the present invention can be used. The semiconductor device shown in Fig. 13 is manufactured in accordance with the following procedure. Referring first to Figure 2a, initially the pad oxide 32 is formed over the epitaxial layer 3 of the first conductivity type dopant doped germanium die 5. In the embodiment shown in Fig. 20, the first conductivity type dopant n-type dopant. A dopant having a conductivity pattern opposite that of the first conductivity type (P-type) is then implanted throughout the pad oxide 32 to form a channel implant region 34 that will become the channel region 12 (top), as will be described later. . Referring then to the sinker map, the vapor layer % is deposited on the pad oxide 32 top 263279. A protective mask is deposited which is deposited over most of the nitride layer 36 leaving only the termination regions exposed. Then, as shown in Fig. 2c, the photoresist 38 is used as a mask. For example, the terminal recess is formed by a conventionally known dry etching technique or some other suitable etching method. The photoresist 5 38 is then removed' and the dopants in the shallow channel implant region 34 are driven in a diffusion motion to form the channel region 12 as shown in Figure 2d. It should be 5 Hai's idea that although not shown, the terminal recess 42 is disposed around the active area of the device.

Referring then to Figure 2e, field oxide 44 is formed in terminal recess 42 to thereby provide a recessed field oxide termination structure. Referring next to Figure 2f, trench mask 46 is placed over nitride 36 and field oxide 44. The trench mask 46 includes openings 48 to define the locations of the trenches 14 (Fig. 1) that will be formed in the die 5. Then, the groove 14 is formed in the body of the granule 5 in a position coincident with the opening 48 as shown in Fig. 2g. The trench 15 14 is formed by dry etching and extends through the channel from the upper surface of the die 5

The region 12 is to a predetermined depth of the drift region 4. It should be noted that it is also possible to extend the groove 14 below the drift region 4. It should also be noted that the grooves 14 may be in the form of parallel strips, hexagonal or some other shape, although strips are preferred, wherein the strips may further reduce the on-resistance. After the trench 14 is formed, a sacrificial oxide layer is grown on the sidewalls and bottom of the trench 14 and then etched. Thereafter the trench mask 46 is removed. Next, the pad oxide is formed in the trench 14, as shown in Figure 2h. Referring again to Figure 2h, the nitride layer is extended over the pad oxide 32 in the trench 14 by nitride layer deposition. 11 1263279 Eight, with the nitride part at the bottom of each groove 14 after m. The brother's were removed by dry cooking, and the thick oxide 15 grew at the bottom of the mother-groove 14. The 5 emulsion 36 disposed on the sidewalls of each trench 14 is an oxidizing resistor that prevents the oxide from growing on the sidewalls of the trench 14 at the bottom of each trench. . As a result, the sidewalls of each trench can be covered by a very thin oxide layer while the bottom of the trench will be completely insulated. ',,; and then as shown in Fig. 2j, the nitride % of the sidewall covering the trench PP' is 'removed' by wet etching, and the gate oxide layer 10 18 is grown in each The interior of the trencher 4. The polycrystalline layer is then deposited such that the trench 14 is filled with polysilicon. Referring then to Figure 2k, a polycrystalline stone mask 52 is formed to cover at least the termination region 40. Then, a gate electrode 16 is formed, and the polysilicon layer 5 is etched such that each trench 14 has a polycrystalline whisker body extending between its bottom portion and the 15 position above the channel portion 12. As a result, the polysilicon layer 50 under the polycrystalline litter mask 52 will be left and then it will become part of the termination structure of the device, as shown in FIG. Next, referring to Fig. 2m, the surface of the gate electrode 16 in each trench μ is oxidized, for example, thermally oxidized, to form the insulating layer 22. Then, substantially all of the nitride 36 is removed by wet etching, for example, leaving only a small portion of the nitride 36 adjacent to the termination structure of the semiconductor device, as shown in Figure 2n. As the nitride 36 is substantially removed, dopants for the formation of the source regions 2 are implanted to form the source implant regions 54, as shown in FIG. 12 1263279 The formation of the source implant region 54 is followed by deposition of a low temperature oxide layer 24 over the entire upper surface of the die, as shown in Figure 2p. It should be noted that the source implant region 54 is formed after the polycrystalline stone is thermally oxidized to form the insulating layer 2 2 . After the thermal oxidation process, the source region 5 (10) final depth can be maintained at a minimum by implanting the source dopant. As a result, the channel region η 2 iceness 'and the thickness of the worm layer 3 can also be minimized, whereby the use of smuggling in the garment shortens the channels and reduces the thickness of the drift region 4 to reduce conduction. impedance. 10 15 20 :, , , : The rear 'source contact light 56 is formed on the low temperature oxide 24 as shown in Fig. 2q. The source contact light % is produced by patterning the photoresist to include the job 58 in a known manner. The opening 58 is used to shape the portion of the low temperature oxide layer 24 such that the secreted region is stretched on the underside of the pole contact material 56 and extends to a depth less than the thickness of the low temperature oxygen, material 24. '(d), making the opening in the source contact surface 56: continuing vertical _ to create a recess 25 extending to a depth below the source implanted area μ, as shown by the butterfly. Once the source contact is formed, the initial tapered etch will improve the step coverage. ... then the source contact material 56 is removed and the source material in the source implant/area 54 is pulled to form a source region, such as f2. After the source diffusion, the highly doped region 26 is etched into a mask using a low temperature oxide as a mask, followed by a diffusion motion, and is formed between the source regions 20, as shown in FIG. . Then, the low temperature telluride 24 can be (4) dropped to expose the source region 2〇 portion of the upper surface of the crystal grain 5.

After 13 1263279 U, the source contact 28 is disposed on the upper surface of the die 5, and the gate contact 30 is formed on the lower surface of the die 5 as shown in Fig. 2u. In addition to these previous steps, conventionally known steps may be performed to form a gate contact 5 structure (not shown) on the upper surface of the die 5 before or after the source contact 28 is formed. A semiconductor device having a self-aligned source region as shown in Fig. 1b can be processed in accordance with the following. Referring to Figure 3a, nitride 36 is formed over the upper surface of the die 5 after the channel implantation step illustrated with reference to Figure 2a. Then, a low temperature 1 〇 oxide layer 24 is formed over the nitride layer 36. It may be about 5 inches thick, and the low temperature oxide 24 may be about 3 〇〇〇 A thick. Referring next to Figure 3b, the trench mask 46 is disposed over the low temperature oxide 24, and the trenches 14 are formed in the die 5 as previously described with reference to Figures 2f and 2g. In accordance with one aspect of the present invention, the low temperature oxide 24 is etched 15 away from the edge of the trench 14 while exposing the surface portion of the nitride 36 disposed between the edge of the trench 14 and the layer of low temperature oxide 24. Referring next to Figure 3c, trench mask 46 is removed and pad oxide 34 is formed over die 5, including the sidewalls and bottom of trench 14. The pad oxide 34 may be about 24 〇A. Nitride 36 is then deposited over the pad oxide 34 2〇. Nitride 36 may be about 2 inches thick. Next, referring to Fig. 3d', the nitride 36 is removed from the upper surface of the low temperature oxide 24 and the bottom of the trenches 14 by etching. Then, the bottom of each trench 14 is oxidized, and the gate electrode 16 and the gate insulating layer are formed as previously described in the Maiko 2i-2m diagram to obtain the junction 14 1263279 shown in Fig. 3e. It should be noted that due to the etching described above with reference to Figure 3b, a shoulder is formed adjacent the upper edge of each of the grooves 14. Using the openings in the low temperature oxide 24 as a mask, dopants are implanted throughout the shoulder adjacent the upper edge of the trench 14 to form the source implant region 54. Then, the dopants in the source implant region 54 are then driven in a diffusion motion to form the source region 20, as shown in Figure 3f. Thereafter, another layer of low temperature oxide 24 may be formed on the upper surface of the crystal grains 5. Referring next to FIG. 3g, the source contact mask 58 is placed over the upper surface of the die 5 and the source contact mask 58 is formed by, for example, photolithography and worming to provide The source contact 28 (see the second) and the die 5 have the same position for electrical contact. The layer of low temperature oxide 24 at the bottom of each opening in the contact mask 58 is engraved to expose the contact area on the upper surface of the die 5, and then highly doped with the channel region 12 Dopings of the same polarity. The dopants are then driven during the diffusion motion 15 to form a highly doped contact region 26. The highly doped contact region 2 is then followed by a low temperature oxide, so that the top portion of the low temperature oxide that exposes the source region 2 〇 below the contact mask is also etched as in FIG. 3g. Do not. Thereafter, the source contact % is deposited on the upper surface of the die $, and the germanium source region 2〇 and the highly alternating contact region % are electrically contacted as shown in Fig. 3h. II <1 As is well known, the immersion contact is formed on the back side of the die $: in addition to the foregoing steps, before or after the source contact 28 is formed, a conventionally known step can be performed to The upper surface of the pellet 5 forms a gate contact structure (not shown). Although the present invention has been described in connection with the specific embodiments thereof, many other variations and modifications and other uses will become apparent to those skilled in the art. Therefore, the invention is preferably not limited to the specific description herein, but is limited only by the scope of the application of the appendices. 5 [Simple description of the cymbal] Fig. 1a is a cross-sectional view showing a part of the semiconductor device according to the present invention.

Figure lb shows a cross-sectional illustration of a portion of another embodiment of a semiconductor device in accordance with the present invention. 10 Figures 2a-2u illustrate a procedure in accordance with the present invention. Figure 3a-3h illustrates a [representative symbol table of the main components of the figure]

2···Early Stone Second Substrate 28...Source Contact Area 3···Stupid Layer 30···Button Contact Area 4...Floating Area 32...Material Oxide 5···$夕晶34·· Channel implant region 10 and pole region 36... nitride layer 12···channel region 38··· photoresist 14... trench 40···terminal region 15... thick oxide 42···terminal recess 16 ...gate electrode 44··· field oxide 18...oxide 46···trench mask 20···self-aligned source region 48···opening 22···gate insulating layer 50·· · Polycrystalline layer 24... Low temperature insulating material / low temperature oxide 52... Polycrystalline germanium mask 26... Contact area 54... Source implanted area 16 1263279 56 · · Source contact mask 58 · · · Opening / contact Mask

17

Claims (1)

1263279 94.1.10 Patent Application Serial No. 92,126,976, the entire disclosure of which is incorporated herein by reference in its entire entire entire entire entire entire entire entire entire entire entire entire entire entire entire entire entire entire entire entire entire entire entire entire a semiconductor crystal grain of the material; 5 forming a layer of an oxidant resist material over the channel receiving layer; forming a trench in the channel receiving layer in a region of the channel receiving layer; Forming a terminal recess around the trenches, the terminal recess having an exposed surface of a semiconducting material, 10 forming a further layer of an oxide resist material on the sidewalls and the bottom of the trenches; An oxide layer is grown on the exposed surface of the terminal recess. 2. The method of claim 1, further comprising: implanting a second passivity 15 channel dopant in the channel receiving layer prior to forming the layer of the oxidant resist material; Forming the layer of the oxidant resist material Thereafter, the channel dopant is diffused to form a channel region. 3. The method of claim 2, further comprising: removing the oxidant resist material from the bottom of the trenches and leaving the oxidant resist material on the sidewalls of the trenches; a bottom portion of the trench, forming a bottom 20 oxide layer; removing the oxide resist material from the sidewalls of the trench; and forming a gate oxide layer on the sidewalls of the trench Wherein the bottom oxide layer is thicker than the gate oxide layer. 4. The method of claim 3, further comprising: forming a gate electrode in each of the trenches; forming an 18 1263279 insulating layer over the gate electrode; and in the channel region The implant having the first conductivity is implanted. 5. The method of claim 4, wherein the gate electrodes are formed by depositing a layer of gate electrode material to at least fill the recesses 5 and extend the oxide in the terminal recess Above the layer; the gate electrode material is removed leaving only the gate electrode material in the interior of the trenches without removing the gate electrode material deposited on the terminal recess. 6. The method of claim 4, further comprising: forming a low temperature oxide layer over the trenches and the terminal recess; patterning the 10 low temperature oxide layer, the low temperature oxide layer a low temperature oxide extending to the opening of the semiconductor die and remaining over the gate electrodes; and driving the dopant having the first conductivity to form adjacent trenches The first conductive conductive region. 7. The method of claim 6, wherein the patterning comprises forming a mask having a masking opening over the 15 low temperature oxide to confirm a region in the low temperature oxide that will be removed to form an opening in the low temperature oxide; and a portion comprising the low temperature oxide laterally removed below the opening of the mask, and then vertically removing the low temperature oxide And forming the openings, whereby the openings in the low temperature oxide will be narrower 20 adjacent to the semiconductor die. 8. The method of claim 6, further comprising forming a contact layer extending to the conductive region having the first conductivity, and the contact layer is adjacent to the trench The first conductive conductive region is in electrical contact. 19 U63279 • The access area as in item 6 of the patent application. And a method of sputum, wherein the openings are exposed to the channel region as disclosed in the ninth item of the patent application scope 5 10 15 15 20, and the phytosan is further included in the opening dopant The concentration of the dopant of the second conductivity type of the human such as the W conductivity type. • Ι: ΓΓ the method of item 9 which in turn includes semiconductor dies in two portions of each of the opening regions to create an exposed channel 12. The method of claim 1, wherein the method further comprises implanting a second conductivity pattern in the region of the channel exposed by the aperture, wherein the third conductivity type is 13 Å plus (four) two conductivity The concentration of the type of dopant. The method of claim 1, wherein the oxidant resist material is a nitride. The method of claim 1, wherein the channel receiving layer is a silicon-conducting stupid layer, and the first conductive layer is formed in the first nature- Above the monolithic substrate. 15. The method of claim 2, wherein the semiconductor device is a gold oxide semiconductor field effect transistor (m〇sfet). A method for fabricating a metal oxide semiconductor (MOS)-controlled semiconductor conversion device, comprising: providing a body grain having a channel-receiving region having a first conductivity; 'in the channel receiving region, forming a a second conductive channel region; 20 a^63279 in the semiconductor die extending through the channel region, one less trench; in the at least one trench, forming a gate structure; and After the gate structure, a conductive region having the first conductivity is formed in the channel region adjacent to each side of the trench. </ RTI> <RTIgt; </ RTI> <RTIgt; </ RTI> <RTIgt; </ RTI> <RTIgt; </ RTI> <RTIgt; </ RTI> <RTIgt; </ RTI> <RTIgt; </ RTI> <RTIgt; </ RTI> <RTIgt; </ RTI> <RTIgt; </ RTI> <RTIgt; On the semiconductor, as an external connection of the conductive package; using the opaque 1 to penetrate the conductive region to reach the concave region of the channel region; at the bottom of the __ implant the second conductive dopant And diffusing the first conductive region in the diffusion drive. The method of forming the handle of claim 18, which is further included in the sidewall of the at least one groove, forming a layer of an oxidant resist material, and forming a layer at the bottom of the groove Thick oxides. 19. The scope of the patent application, in the granules, in the granules, further comprises forming a terminal structure in the semiconductor crystal grains, the notches in the ruthenium grains. "Construction comprises - formed in the semiconductor 20 - as in the scope of claim 16 - gate electrode, the gate electrode ', (four) pole structure comprises sidewall insulation, wherein 4: two insulating layers are formed and the trenches The groove is formed by thermal oxidation. Before the domain, the insulation layer is borrowed 21