JPH11274173A - Manufacture of silicon carbide semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To form a source region and a base region with accurate positional relation. SOLUTION: Mask material 20 is formed on an n-type silicon carbide epitaxial layer 2, and also an opening 20a whose side in inclined is made in the prescribed region of this mask material 20, and ion implantation is performed through this opening 20a, so as to form p<-> -type silicon carbide base regions 3a and 3b and n<+> -type source regions 4a, 4b which are shallower in junction depth than those of p<-> -type silicon carbide base regions 3a and 3b. In this way, the p<-> -type silicon carbide base regions 3a and 3b and n<+> -type regions 4a and 4b can be formed by the same mask, so that the p<-> -type silicon carbide base regions 3a and 3b and n<+> -type source regions 4a and 4b can be made in a self-aligned manner, and these can be formed, with accurate positional relations.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a silicon carbide semiconductor device, and more particularly to an insulated gate field effect transistor, and more particularly to a vertical power MOSFET for high power.

[0002]

2. Description of the Related Art As a conventional technique for manufacturing a MOSFET using silicon carbide, a manufacturing method for avoiding a drawback that a double diffusion technique for forming a channel by self-alignment cannot be used is disclosed in Japanese Patent Laid-Open No. 6-151860. It is proposed in the gazette. 24A to 24F show the manufacturing steps. In this manufacturing process, after the surface of n-type silicon carbide substrate 101 is thermally oxidized to form gate oxide film 102, gate electrode 103 having inclined surface 104 made of polycrystalline silicon or metal is formed. After that, the gate electrode 103
Is used as part of a mask to implant p-type and n-type impurity ions to form a p-base region 106 and an n ⁺ -type source region 107.

[0003] In this method, since a self-alignment technique using the gate electrode 103 as a mask at the time of implantation is applied, high performance can be achieved. Further, the present applicant has filed an application in Japanese Patent Application No. 9-259076 as a structure for improving the channel mobility of a vertical MOSFET and reducing the on-resistance. FIG. 20 shows a cross-sectional view of a planar MOSFET as an example of the vertical MOSFET.
The structure of the planar type vertical MOSFET will be described with reference to FIG.

[0004] The n ⁺ type silicon carbide semiconductor substrate 1 has an upper surface as a main surface 1a and a lower surface opposite to the main surface as a back surface 1b. Main surface 1a of n ⁺ type silicon carbide semiconductor substrate 1
Above, n ⁻ having a lower dopant concentration than substrate 1
-Type silicon carbide epitaxial layer (hereinafter referred to as n ^- type silicon carbide epi layer) 2 is stacked. In this case, n ⁺ -type silicon carbide semiconductor substrate 1 and the n ^- but the upper surface of type silicon carbide epitaxial layer 2 is set to (0001) Si plane, n ⁺ -type silicon carbide semiconductor substrate 1 and the n ^- -type silicon carbide epitaxial layer 2 The upper surface may be the (112-0) a surface. That is, (000
1) A low surface state density can be obtained by using the Si surface, and (1)
The use of the 12-0) a-plane makes it possible to obtain a crystal having a low surface state density and completely free from screw dislocations. Note that an off-substrate having an inclination of about 3 ° to 10 ° can be used.

[0005] n^-In the surface layer of silicon carbide epilayer 2
In a predetermined area, p having a predetermined depth ^-Type silicon carbide base
Regions 3a and p^-Type silicon carbide base region 3b is separated
It is formed. Also, p^--Type silicon carbide base region 3
a in a predetermined region in the surface layer portion of the base region 3a
Also shallow n⁺The type source region 4a also has p^-Type silicon carbide
A predetermined area in the surface portion of the base area 3b includes a base
N shallower than region 3b ⁺Each of the mold source regions 4b
Has been established.

Deep base layers 30a and 30b formed at positions that do not substantially overlap n ⁺ -type source regions 4a and 4b are provided at the center of p ^-- type silicon carbide base regions 3a and 3b. These deep base layers 30a, 30b
As a result, p ⁻ -type silicon carbide base regions 3a and 3b are partially deepened, and n ⁻ -type silicon carbide epi layer 2 under deep base layers 30a and 30b is thinned to form p ⁻ -type silicon carbide base region 3a. , 3b and n ⁺ -type silicon carbide semiconductor substrate 1 are made shorter.

The deep base layers 30a and 30b increase the electric field strength at the junction between the deep base layers 30a and 30b and the n ⁻ -type silicon carbide epilayer 2 to facilitate avalanche breakdown at these portions. By forming the deep base layers 30a and 30b at the positions described above, the surge energy can be extracted through a path in which the parasitic transistor is difficult to operate, so that a sufficient L load tolerance can be provided. Since the deep base layers 30a and 30b are formed at such positions, the surge energy can be drawn through a path that makes it difficult to operate the parasitic bipolar transistor.

Further, the surface portions of n ^-- type silicon carbide epilayer 2 and p ^-- type silicon carbide base regions 3a, 3b between n ⁺ -type source region 4a and n ⁺ -type source region 4b are provided with n ^-- type SiC. Layer 5 extends. That is, n ⁻ -type SiC layer 5 is arranged so as to connect source regions 4a, 4b and n ⁻ -type silicon carbide epilayer 2 at the surface portions of p ⁻ -type silicon carbide base regions 3a, 3b.

[0009] The n ^- type SiC layer 5 has been formed by epitaxial growth, the crystal of the epitaxial film is used 4H, 6H, those 3C. The epitaxial layer can form various crystals regardless of the underlying substrate. This n ⁻ -type SiC layer 5 functions as a channel forming layer on the device surface during device operation. Hereinafter, this n ⁻ -type SiC layer 5 is referred to as a surface channel layer.

The dopant concentration of the surface channel layer 5 is 1
The concentration is as low as about × 10 ¹⁵ cm ⁻³ to about 1 × 10 ¹⁷ cm ⁻³ , and is lower than the dopant concentration of n ⁻ -type silicon carbide epilayer 2 and p ⁻ -type silicon carbide base regions 3a and 3b. ing. Thereby, low on-resistance is achieved. In addition, concave portions 6a and 6b are formed in the surface portions of p ⁻ -type silicon carbide base regions 3a and 3b and n ⁺ -type source regions 4a and 4b.

A gate insulating film (silicon oxide film) 7 is formed on the upper surface of the surface channel layer 5 and the upper surfaces of the n ⁺ type source regions 4a and 4b. Further, a polysilicon gate electrode 8 is formed on the gate insulating film 7, and the polysilicon gate electrode 8 is formed by LTO (Low Tem).
It is covered with an insulating film 9 made of P.O. A source electrode 10 is formed thereon,
The source electrode 10 includes n ⁺ type source regions 4a, 4b and p
^- type silicon carbide base regions 3a, is in contact with 3b. Drain electrode 11 is formed on rear surface 1b of n ⁺ -type silicon carbide semiconductor substrate 1.

Next, a planar type power MO shown in FIG.
The manufacturing process of the SFET will be described with reference to FIGS. [Step shown in FIG. 21A] First, n-type 4H or 6H
Alternatively, a 3C-SiC substrate, that is, an n ⁺ type silicon carbide semiconductor substrate 1 is prepared. Here, n ⁺ -type silicon carbide semiconductor substrate 1 has a thickness of 400 μm and main surface 1a has a thickness of (0
(001) Si plane or (112-0) a plane. An n ^-- type silicon carbide epilayer 2 having a thickness of 5 μm is epitaxially grown on main surface 1a of substrate 1. In this example, n ⁻ -type silicon carbide epilayer 2 has the same crystal as base substrate 1,
It becomes an n-type 4H or 6H or 3C-SiC layer.

[Step shown in FIG. 21B] n^-Type silicon carbide
An LTO film 20 is arranged in a predetermined region on the surface of the element epi layer 2,
Using this as a mask, a p-type impurity (for example, boron or
Ion) and p ^-Type silicon carbide base
Regions 3a and 3b are formed. Ion implantation conditions at this time
Is boron (B⁺) Is injected at a temperature of 700
At ~ 1000 ° C, dose amount is about 1 × 10^Fifteencm^-2As
I have.

[Step shown in FIG. 21C] LTO film 20
Is removed, surface channel layer 5 is grown by epitaxial growth on the surface of n ⁻ -type silicon carbide epilayer 2 and over p ⁻ -type silicon carbide base regions 3a and 3b.
The temperature of the heat treatment performed at the time of this epitaxial growth is performed at 1200 to 1500 ° C.

At this time, the planar type power MOS
To make the FET normally-off type, the surface channel layer
The thickness (film thickness) of 5 is a desired thickness. [Step shown in FIG. 22A] Location above the surface channel layer 5
An LTO film 21 is arranged in the constant region, and n
Type impurities (eg, nitrogen (N⁺)) And n⁺
Form source regions 4a and 4b are formed. Ion at this time
The implantation condition is 700 ° C., and the dose amount is 1 × 10 ^Fifteencm^-2When
doing.

[Step shown in FIG. 22 (b)]
After removing the O film 21, an LTO film 22 is arranged in a predetermined region on the surface channel layer 5 using photolithography, and the surface of the p ^- type silicon carbide base regions 3 a and 3 b is subjected to RIE using this as a mask. The channel layer 5 is partially etched away.

[Step shown in FIG. 22C] Further, LT
B ⁺ ions are implanted using the O film 22 as a mask to form the deep base layers 30a and 30b. Thereby, a part of base regions 3a and 3b becomes thicker, and the thickness of n ⁻ -type silicon carbide epilayer 2 under deep base layers 30a and 30b becomes thinner.

The deep base layers 30a and 30b are
The p ^- type silicon carbide base regions 3a, 3b are formed in portions that do not overlap the n ⁺ -type source regions 4a, 4b, and the portions of the p ⁻ -type silicon carbide base regions 3a, 3b where the deep base layers 30a, 30b are formed are thickened. The impurity concentration is higher than that of the thin portion where the layer 30a is not formed.

[Step shown in FIG. 23A] LTO film 22
Is removed, a gate insulating film (gate oxide film) 7 is formed on the substrate by wet oxidation. At this time, the ambient temperature is 1080 ° C. Thereafter, a polysilicon gate electrode 8 is deposited on the gate insulating film 7 by LPCVD. The film formation temperature at this time is 600 ° C.

[Step shown in FIG. 23B] Subsequently, after removing unnecessary portions of the polysilicon gate electrode 8, LT
An insulating film 9 made of O is formed to cover the gate insulating film 7. More specifically, the film formation temperature is 425 ° C.
Anneal at 00 ° C. At this time, the annealing atmosphere gas is H ₂ , N ₂ or Ar. Thereafter, unnecessary portions of the gate insulating film 7 and the insulating film 9 are removed, and a contact hole is formed.

[Step shown in FIG. 23 (c)] Then, the source electrode 10 and the drain electrode 11 are arranged by metal sputtering at room temperature. After film formation, annealing at 1000 ° C. is performed. Thus, the vertical power MOSFET shown in FIG. 20 is completed.

[0022]

As described above, according to the method disclosed in JP-A-6-151860, self-alignment becomes possible and the performance of the element can be improved. However, since the impurity profile is controlled by controlling the acceleration energy of ions using the gate electrode 103 having the inclined surface 104 as an ion implantation mask, the gate insulating film 102 located under the gate electrode 103 is in principle also required. There is a problem that the ion species are directly implanted, and the damage is reduced in the use of the gate insulating film 102 for the tree.

In the vertical power MOSFET filed by the present applicant, p ^- type silicon carbide base regions 3a, 3a
Since b and n ⁺ -type source regions 4a and 4b were formed using different masks, it was found that misalignment occurred. Since the misalignment causes a variation in channel length, a problem of increasing variations in electrical characteristics (threshold voltage, breakdown voltage, on-resistance, etc.) between elements occurs. This problem occurs remarkably when forming a device having a fine pattern, and makes it difficult to miniaturize the device.

The present invention has been made in view of the above points, and has as its object to provide a method of manufacturing a silicon carbide semiconductor device capable of forming a source region and a base region in a precise positional relationship.

[0025]

In order to achieve the above object, the following technical means are employed. According to the first aspect of the present invention, a mask material (20) is formed on the semiconductor layer (2), and an opening having a side surface inclined in a predetermined region of the mask material is formed. To form a base region (3a, 3b) and a source region (4a, 4b) having a junction depth smaller than that of the base region.

As described above, when the ion implantation is performed using the mask material having the opening having the inclined side surface as a mask, the base region and the source region are changed in size (width) and junction by changing the ion implantation energy. It can be formed by changing the depth. In this case, since the base region and the source region can be formed using the same mask, the base region and the source region can be formed in a self-aligned manner, and they can be formed with an accurate positional relationship.

The size of the source region can be controlled by changing the inclination angle of the side surface of the opening of the mask material. According to the third aspect of the present invention, the base region (3a, 3b) is formed by ion-implanting the first opening (22a) formed in the predetermined region of the first mask material (22). The second mask material (2) is placed on the first mask material including the first opening.
3) is formed, and the second mask material is removed by reactive ion etching until the first mask material is exposed to form a second opening (23a). Ion implantation is performed from the part to form source regions (4a, 4b).
Is formed.

As described above, if the second mask material is formed on the first mask material including the first opening, and the second mask material is etched back by reactive ion etching, the second mask material is obtained. It is possible to form a second opening smaller than the first opening by an equal distance in the mask material. Therefore, if the source region is formed by ion implantation from the second opening, the base region and the source region can be formed in a self-aligned manner. Thereby, the same effect as the first aspect can be obtained.

As described above, the size of the source region can be controlled by controlling the thickness of the second mask material. That is, since the distance between the second opening and the first opening is set by the thickness of the second mask material, the size of the source region is reduced according to the thickness of the second mask material. Can be changed. In the invention according to claim 5, the opening formed in the predetermined region of the mask material is
Base regions (3a, 3b) are formed by oblique ion implantation, and ion implantation is further performed through the openings to form source regions (4a, 4b) having a shallower junction depth than the base regions in the base regions. It is characterized by forming.

As described above, when the oblique ion implantation is performed from the opening, the impurity is implanted to a position deeper than the opening end of the opening by a predetermined distance. If the base region is formed by oblique ion implantation and the source region is formed by normal ion implantation (or even by ion implantation with lower energy than when forming the base region), the source region can be formed. Can be formed on the surface of the base region. Thus, the source region and the base region can be formed using the same mask, so that the base region and the source region can be formed in a self-aligned manner, and the same effect as that of the first aspect can be obtained.

The size of the base region can be controlled by controlling the acceleration voltage and the angle of the oblique ion implantation. In the invention according to claim 7, the first and second mask materials (41, 51, 42, 52) are sequentially laminated on the semiconductor layer (2), and the second mask material (42, 52) is formed. The first opening (52a)
Are provided, and the first mask material (41, 5
1) is etched to provide a second opening (51a) larger than the first opening, and ion implantation is performed from the first opening to form source regions (4a, 4b); After the mask material is removed, ion implantation is performed from the second opening to form the base regions (3a, 3b).

As described above, if the first mask material is etched from the first opening formed in the second mask material to form a second opening larger than the first opening,
The distance between the opening end of the second opening and the opening end of the first opening is formed to be constant. For this reason, if the source region is formed by performing ion implantation from the first opening, the second mask material is removed, and ion implantation is performed from the second opening to form the base region. The base region can be formed in a self-aligned manner. Thereby, claim 1
The same effect can be obtained.

[0033] As described in claim 8, a silicon nitride film can be used as the first mask material.
A silicon oxide film can be used as the second mask material. According to the ninth aspect of the present invention, the first and second mask materials (45, 6) laminated on the semiconductor layer (2) are provided.
1, 46, 62) through the first openings (48, 7).
0) is provided, ion implantation is performed from the first opening to form source regions (4a, 4b), and then the second region is formed.
LOCOS using the first mask material as a mask
The second mask material is oxidized and an oxidized portion (45a) of the second mask material and the first mask material is removed, and a second opening (49, 71) larger than the first opening is formed in the first mask material. And a base region (3a, 3b) is formed by performing ion implantation from the second opening.

As described above, when the first mask material is LOCOS-oxidized using the second mask material as a mask,
The mask material is oxidized to a portion at a predetermined distance from the first opening, and by removing the oxidized portion, a second opening larger than the first opening can be formed. Therefore, if a source region is formed by ion implantation from the first opening and a base region is formed by ion implantation from the second opening, these are formed in a self-aligned manner. The same effect can be obtained.

According to a tenth aspect of the present invention, the first mask material can be made of polysilicon, and the second mask material can be made of a silicon nitride film. According to a tenth aspect of the present invention, after the step of forming the base region, a surface channel layer (5) serving as a channel region is formed on the base region so as to connect the source region and the semiconductor layer. And

As described above, the present invention can be applied to a storage-type silicon carbide semiconductor device having a surface channel layer as a channel region.

[0037]

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a block diagram showing a first embodiment of the present invention. (First Embodiment) Vertical power MO shown in this embodiment
The SFET is shown in FIG. The vertical power MOSFET shown in FIG. 1 is a vertical power MOSFET shown in FIG.
Since it is almost the same configuration as, only the different parts will be described,
Similar parts are denoted by the same reference numerals, and description thereof is omitted.

As shown in FIG. 1, the side surfaces of p ^-- type silicon carbide base regions 3a and 3b and n ⁺ -type source regions 4a and 4b
Are tapered with respect to the substrate surface (the surface of the n ⁻ -type silicon carbide epilayer 2), and have a substantially parallel relationship. The bottom surfaces of p ⁻ -type silicon carbide base regions 3a and 3b and the bottom surfaces of n ⁺ -type source regions 4a and 4b are substantially parallel to the substrate surface (the surface of n ⁻ -type silicon carbide epilayer 2).

The surface channel layer 5 is disposed above the surfaces of the n ⁺ type source regions 4a and 4b. This is because the surface channel layer 5 is formed after the formation of the n ⁺ -type source regions 4a and 4b. p ^- type silicon carbide base regions 3a, 3b and n ⁺ type source region 4
A contact hole penetrating n ⁺ -type source regions 4a and 4b and reaching p ⁻ -type silicon carbide base regions 3a and 3b is formed at the center of a and b, and source electrode 10 is formed through these contact holes. Is the n ⁺ type source region 4a,
4b and are electrically in contact with p ^- type silicon carbide base regions 3a and 3b.

The vertical power MOSFET according to the present embodiment
T is the vertical power MOSF shown in FIG.
Different from ET. Next, a manufacturing process of the vertical power MOSFET shown in FIG. 1 will be described with reference to FIGS. However, in these figures, only the parts different from the conventional manufacturing steps shown in FIGS. 21 to 23 described above are shown, and the description of the same parts is omitted.

First, as shown in FIG. 21 (a), n on the n ⁺ -type silicon carbide semiconductor substrate 1 ^- is prepared which was deposited type silicon carbide epitaxial layer 2. Then, the following steps are sequentially performed. [Step shown in FIG. 2A] A mask material 20 is formed on the n ⁻ -type silicon carbide epilayer 2 by a silicon oxide film or the like.
Then, a predetermined region of the mask material 20, specifically, n ⁺
An opening 20a having a substantially tapered side surface is formed at a position corresponding to a region where the type source regions 4a and 4b and the p ^- type silicon carbide base regions 3a and 3b are to be formed. The formation of the substantially tapered opening 20a can be realized by performing isotropic etching or the like. In addition,
The size (width) of n ⁺ -type source regions 4a and 4b formed in a later step can be controlled by the angle of the side surface.

[Step shown in FIG. 2B] Next, ions of a p-type impurity (for example, boron or aluminum) are implanted from the normal direction of the substrate using the mask material 20 as a mask. Thus, p ⁻ -type silicon carbide base regions 3a and 3b are formed. At this time, since the depth at which the p-type impurity is implanted is substantially determined, the impurity is implanted from the surface of the mask material 20 by a predetermined depth. Therefore, p ⁻ -type silicon carbide base regions 3a and 3b are formed in the same shape as opening 20a.

[Step shown in FIG. 2 (c)] Further, using the mask material 20 used earlier as a mask, n
Ion implantation of a type impurity (for example, nitrogen) is performed. The ion implantation at this time is performed with smaller energy than the ion implantation of the p-type impurity performed in FIG. This allows
An n-type impurity is implanted at a position shallower than p ^-- type silicon carbide base regions 3a, 3b, and the p-type impurity in that portion is compensated to form n ⁺ -type source regions 4a, 4b.
At this time, since the implantation depth of the n-type impurity is substantially determined as described above, the n ⁺ -type source regions 4a and 4b are implanted in the same shape as the opening 20a.

At this time, a mask for forming n ⁺ type source regions 4a and 4b is used as p ⁻ type silicon carbide base region 3.
a, 3b are formed using the same mask as that for forming p ⁻ -type base regions 3a, 3b and n.
⁺ Type source regions 4a and 4b are formed in a self-aligned manner (self-aligned). Therefore, the formation positions of p ⁻ -type silicon carbide base regions 3a and 3b and n ⁺ -type source regions 4a and 4b
The position where b is formed has an accurate positional relationship.

[Step shown in FIG. 3 (a)]
Remove and n^-Type silicon carbide epilayer 2 is exposed. [Step shown in FIG. 3B]
And p^--Type silicon carbide base regions 3a, 3b and n⁺Type
N at the center of the source regions 4a and 4b.⁺Mold source region 4
a, penetrating through 4b ^--Type silicon carbide base regions 3a, 3
A contact hole reaching up to b is formed.

Thereafter, the vertical power MOSFET shown in FIG. 1 is completed through the steps shown in FIGS. 21 to 23, such as by epitaxially growing the surface channel layer 5. The vertical power MOSFET thus completed has n ⁺ -type source regions 4a and 4b and p ^-- type silicon carbide base regions 3a and 3a.
Are formed in an accurate positional relationship, from the end of p ⁻ -type silicon carbide base regions 3a and 3b on the surface of n ⁻ -type silicon carbide epilayer 2 to the end of n ⁺ -type source regions 4a and 4b. Can be accurately formed, and the length (channel length) of the channel region formed on this portion can be set accurately. Therefore, it is possible to manufacture a vertical power MOSFET having good characteristics with little characteristic fluctuation of the element.

In the present embodiment, the deep base layer 3 shown in FIG.
Although 0a and 30b are not formed, they can be formed separately by, for example, ion-implanting p-type impurities through contact holes. (Second Embodiment) Vertical power MO shown in this embodiment
The SFET is shown in FIG. Since the vertical power MOSFET shown in FIG. 4 has almost the same configuration as the vertical power MOSFET shown in FIG. 1, only different portions will be described, and the same portions will be assigned the same reference numerals and description thereof will be omitted.

As shown in FIG. 4, side surfaces of p ^-- type silicon carbide base regions 3a and 3b and n ⁺ -type source regions 4a and 4b
Have a shape that is substantially perpendicular to the substrate surface (the surface of the n ⁻ -type silicon carbide epilayer 2), and are substantially parallel to each other. The bottom surfaces of p ⁻ -type silicon carbide base regions 3a and 3b and n ⁺ -type source regions 4a and 4b
Is the substrate surface (the surface of the n ⁻ -type silicon carbide epilayer 2)
And it is almost parallel. The vertical power MOSFET according to the present embodiment is different from the vertical power MOSFET shown in FIG. 1 in this point.

Next, the vertical power MOSF shown in FIG.
The manufacturing process of the ET will be described with reference to FIGS. However, in these figures, only the portions different from the conventional manufacturing process shown in FIGS. 21 to 23 described above are shown,
The description of the same parts is omitted. First, FIG.
As shown in FIG. 1A, an n ⁻ -type silicon carbide semiconductor layer 1 having an n ⁻ -type silicon carbide epitaxial layer 2 formed thereon is prepared.
Then, the following steps are sequentially performed.

[Step shown in FIG. 5A] A mask material 22 is formed on the n ⁻ -type silicon carbide epilayer 2 by a silicon oxide film or the like.
Is formed. An opening whose side surface is substantially perpendicular to a predetermined region of mask material 22, specifically, a region corresponding to a region where n ⁺ -type source regions 4a and 4b and p ⁻ -type silicon carbide base regions 3a and 3b are to be formed. The part 22a is formed.

[Step shown in FIG. 5B] Next, ions of a p-type impurity (for example, boron or aluminum) are implanted from the normal direction of the substrate using the mask material 22 as a mask. As a result, p-type impurities are implanted to a predetermined depth to form p ⁻ -type silicon carbide base regions 3a and 3b. At this time, since the side surface of the opening of mask material 22 is substantially perpendicular to the substrate surface, p ⁻ -type silicon carbide base region 3a,
3b is formed with its side surface substantially perpendicular to the substrate surface.

[Step shown in FIG. 5C] Next, the opening 2
2a, the entire surface of the mask material 22 (the entire surface of the wafer)
An EOS oxide film 23 is formed. Thereby, the opening 22
a is also filled with the TEOS oxide film 23. At this time, T
The portion of the EOS oxide film 23 that has entered the opening 22a is formed at the central portion of the opening 22a to have the same thickness as that on the mask material 22, and the other center near the opening end of the opening 22a. It is formed thicker than the part. At this time, the thickness of the TEOS oxide film 23 that has entered the opening 22a from the opening end of the opening 22a is substantially the same at any position.

[Step shown in FIG. 6A] The TEOS oxide film 23 is etched back until the TEOS oxide film 23 on the mask material 22 disappears. As a result, the TEOS oxide film 23 is one of those that have entered the opening 22a.
Since the thick portion (other than the central portion) remains and the central portion is opened, the opening area of the opening 22a is reduced. Further, at this time, the thickness of the remaining TEOS oxide film 23 from the opening end of the opening 23a is substantially the same at any position.

[Step shown in FIG. 6B] Using the mask material 22 and the TEOS oxide film 23 as a mask, ions of an n-type impurity (for example, nitrogen) are implanted from the normal direction of the substrate. The ion implantation at this time is performed with smaller energy than the ion implantation of the p-type impurity performed in FIG.
As a result, n-type impurities are implanted at a position shallower than p ^-- type silicon carbide base regions 3a and 3b, and the p-type impurities in those portions are compensated to form n ⁺ -type source regions 4a and 4b.

At this time, the opening 2 of the TEOS oxide film 23
Since the distance from the opening end of 3a to the opening end of opening 22a of mask material 22 is constant at any position, n ⁺ -type source regions 4a and 4b have p ^-- type silicon carbide base region 3a, 3b is formed in an accurate positional relationship. [Step shown in FIG. 6C] The mask material 22 and the TEOS oxide film 23 are removed to expose the n ⁻ -type silicon carbide epilayer 2. Then, by further photo-etching, p ^-
Type silicon carbide base regions 3a, 3b and the n ⁺ -type source region 4a, the middle portion of the 4b, n ⁺ -type source region 4a, through the 4b p ^- -type silicon carbide base region 3a, a contact hole reaching 3b formed I do.

Thereafter, through the steps shown in FIGS. 21 to 23, such as by epitaxially growing the surface channel layer 5, the vertical power MOSFET shown in FIG. 4 is completed. In the completed vertical power MOSFET, the n ⁺ type source region and the p ⁻ type silicon carbide base regions 3a, 3a are formed in a precise positional relationship, so that the same effects as in the first embodiment can be obtained. Can be.

(Third Embodiment) FIG. 7 shows a vertical power MOSFET shown in this embodiment. The vertical power MOSFET shown in FIG.
Since the configuration is almost the same as that of the SFET, only different portions will be described, and similar portions will be denoted by the same reference numerals and description thereof will be omitted.

As shown in FIG. 7, the side surfaces of p ^- type silicon carbide base regions 3a and 3b are both substantially tapered with respect to the substrate surface (the surface of n ^- type silicon carbide epilayer 2). . On the other hand, the side surfaces of the n ⁺ type source regions 4a and 4b are substantially perpendicular to the substrate surface. Therefore, p
^- type silicon carbide base region 3a, the side surface and the n ⁺ -type source region 4a of 3b, the side of the 4b not parallel. In addition,
The bottom surfaces of the p ⁻ -type silicon carbide base regions 3a and 3b and the bottom surfaces of the n ⁺ -type source regions 4a and 4b are substantially parallel to the substrate surface and are substantially parallel to each other. The vertical power MOSFET according to the present embodiment is different from the vertical power MOSFET shown in FIG. 1 in this point.

Next, the vertical power MOSF shown in FIG.
The manufacturing process of the ET will be described with reference to FIG. However, in this figure, only parts different from the conventional manufacturing steps shown in FIGS. 21 to 23 described above are shown, and description of similar parts is omitted. First, as shown in FIG. 21A, an n ⁻ -type silicon carbide semiconductor substrate 1 having an n ⁻ -type silicon carbide epilayer 2 formed thereon is prepared. Then, the following steps are sequentially performed.

[Step shown in FIG. 8A] A mask material 25 is formed on the n ⁻ -type silicon carbide epilayer 2 by a silicon oxide film or the like.
Is formed. An opening whose side surface is substantially perpendicular to a predetermined region of mask material 25, specifically, a region corresponding to a region where n ⁺ -type source regions 4a and 4b and p ⁻ -type silicon carbide base regions 3a and 3b are to be formed. The part 25a is formed.

Thereafter, p-type impurities (for example, boron or aluminum) are obliquely ion-implanted while rotating the substrate to form p ^- type silicon carbide base regions 3a and 3b.
As described above, since p ⁻ -type silicon carbide base regions 3a and 3b are formed by oblique ion implantation, the side surfaces of p ⁻ -type silicon carbide base regions 3a and 3b are substantially tapered with respect to the substrate surface.

At this time, by oblique ion implantation,
The depth of the implanted p-type impurity depends on the energy at the time of ion implantation.
Because it is generally determined by the energy of the mask material 25
P-type impurities from the opening end of the opening 25a to a depth at an equal interval.
Is injected. Therefore, p ^--Type silicon carbide base region 3
The distance between the terminal ends of the openings a and 3b and the opening end of the opening 25a is one.
It will be fixed.

[Step shown in FIG. 8 (b)]
N-type from the substrate normal direction using the mask material 25
Impurity (eg, nitrogen) ion implantation is performed. At this time
The ion implantation is performed using the p-type impurity ions performed in FIG.
Perform with less energy than during injection. This gives p
^-Shallower than n-type silicon carbide base regions 3a, 3b and n-type impurity
Is implanted, and p-type impurities in that part are compensated.
T⁺Form source regions 4a and 4b are formed.

At this time, n ⁺ type source regions 4a, 4b
Is formed so that the terminal end is substantially coincident with the opening end of opening 25a, so that the distance from the terminal of p ⁻ -type silicon carbide base regions 3a, 3b to the terminal of n ⁺ -type source regions 4a, 4b is increased. It becomes constant, and the n ⁺ type source region and the p ⁻ type silicon carbide base region 3a, 3a are formed in an accurate positional relationship.
Since the n ⁺ -type source regions 4a and 4b are formed by ion implantation from the normal direction of the substrate surface, the side surfaces of the n ⁺ -type source regions 4a and 4b are substantially perpendicular to the substrate surface. Shape.

[Step shown in FIG. 8C]
Remove and n^-Type silicon carbide epilayer 2 is exposed. Soshi
And by photo etching, p^-Type silicon carbide
Elementary base regions 3a, 3b and n⁺Mold source regions 4a, 4
In the center of b, n⁺Through the mold source regions 4a, 4b
p ^-Contour reaching silicon carbide base regions 3a and 3b
Form a hole.

Thereafter, the vertical power MOSFET shown in FIG. 7 is completed through the steps shown in FIGS. 21 to 23, such as by epitaxially growing the surface channel layer 5. The vertical power MOSFET thus completed has n ⁺ -type source regions 4a and 4b and p ^-- type silicon carbide base regions 3a and 3a.
Are formed in an accurate positional relationship, and the same effects as in the first embodiment can be obtained.

(Fourth Embodiment) The vertical power MOSFET shown in the present embodiment has the same configuration as the vertical power MOSFET (see FIG. 4) in the second embodiment, and the manufacturing method is different. Description will be omitted, and only the manufacturing process will be described. The manufacturing process of the vertical power MOSFET according to the present embodiment will be described with reference to FIGS. However, in these figures, FIGS.
Only parts different from the conventional manufacturing process shown in FIG. 23 are shown, and description of similar parts is omitted.

[0068] First, as shown in FIG. 21 (a), n on the n ⁺ -type silicon carbide semiconductor substrate 1 ^- is prepared which was deposited type silicon carbide epitaxial layer 2. Then, the following steps are sequentially performed. [Step shown in FIG. 9 (a)] A silicon nitride film (Si ₃ N ₄ film) 41 is formed to a desired thickness on the n ⁻ -type silicon carbide epilayer 2 and further a silicon oxide film (SiO ₂ film) ) 42 is formed in a desired thickness. After the photoresist 43 is deposited, the n ⁺ -type source region 4 of the photoresist is deposited.
Open regions where a and 4b are to be formed.

[Step shown in FIG. 9B] The n ⁺ -type source regions 4a and 4b of the silicon oxide film 42 are to be formed by RIE (reactive ion etching) using CF ₄ + H ₂ gas. The opening 42a is provided in the region of. At this time, since the etching is performed using the CF ₄ + H ₂ gas, only the silicon oxide film is selectively etched, and the silicon nitride film 41 remains without being etched.

[Step shown in FIG. 9C] Next, a part of the silicon nitride film 41 is removed by dry etching.
An opening 41a is provided in a region where p ^- type silicon carbide base regions 3a and 3b are to be formed. Specifically, the region is opened by etching the silicon nitride film 41 in the lateral direction. The amount of the dry etching is controlled by selecting an etching gas, controlling the etching time, and the like. At this time, the amount of dry etching in the horizontal direction is equal in any direction, and therefore, the distance from the opening end of the opening 42a to the opening end of the opening 41a is equal in any direction.

[Step shown in FIG. 10A] After removing the photoresist 43, ion implantation is performed using the silicon oxide film 42 as a mask to form n ⁺ -type source regions 4a and 4b. [Step shown in FIG. 10B] And the silicon oxide film 4
2 are removed, and a p-type impurity (for example, boron or aluminum) is ion-implanted using the silicon nitride film 41 as a mask. Thereby, p ⁻ -type silicon carbide base region 3
a, 3b are formed.

At this time, the opening end of the opening 41a is
No matter where the distance to the open end of 42a is,
Since they are almost equal, the silicon oxide film 42 is masked.
N formed⁺Type source regions 4a, 4b and silicon
Formed using the nitride film 41 as a mask.^-Type silicon carbide
Source regions 3a and 3b are formed in a self-aligned manner. this
After that, the silicon nitride film 41 is removed and photo-etching is performed.
By p^--Type silicon carbide base regions 3a, 3b and n
⁺In the center of the mold source regions 4a and 4b, n ⁺Type source area
P through areas 4a, 4b^--Type silicon carbide base region 3
Contact holes reaching a and 3b are formed. Further
Such as epitaxially growing the surface channel layer 5 in FIG.
Through the steps shown in FIG. 21 to FIG.
The type power MOSFET is completed.

The vertical power MOSFET thus completed
In T, the same effects as in the first embodiment can be obtained because the n ⁺ type source regions 4a and 4b and the p ⁻ type silicon carbide base regions 3a and 3a are formed in a precise positional relationship. (Fifth Embodiment) Vertical power MO shown in this embodiment
The SFET is a vertical power MOSF according to the second embodiment.
Since the configuration is the same as that of ET (see FIG. 4) and the manufacturing method is different, the description of the configuration is omitted and only the manufacturing process will be described.

The vertical power MOSFET according to the present embodiment
The manufacturing process of T will be described with reference to FIGS. However, in these figures, only the portions different from the conventional manufacturing process shown in FIGS. 21 to 23 described above are shown,
The description of the same parts is omitted. First, FIG.
As shown in FIG. 1A, an n ⁻ -type silicon carbide semiconductor layer 1 having an n ⁻ -type silicon carbide epitaxial layer 2 formed thereon is prepared.
Then, the following steps are sequentially performed.

[Step shown in FIG. 11A] A polysilicon film 45 is formed to a desired thickness on the n ⁻ -type silicon carbide epilayer 2, and a silicon nitride film (Si ₃ N ₄ film) 46 is further formed. Is formed in a desired thickness. Then, after the photoresist 47 is deposited, the regions of the photoresist 47 where the n ⁺ -type source regions 4a and 4b are to be formed are opened.

[Step shown in FIG. 11B] In the silicon nitride film 46 and the polysilicon film 45 by RIE (reactive ion etching), the regions where the n ⁺ -type source regions 4a and 4b are to be formed are formed. An opening 48 is provided. [Step shown in FIG. 11C] After the photoresist 47 is removed, ion implantation is performed using the silicon nitride film 46 as a mask to form n ⁺ -type source regions 4a and 4b.

[Step shown in FIG. 12A] LOCOS (Local Oxi) using silicon nitride film 46 as a mask.
(dation of Silicon) oxidation to partially oxidize the polysilicon film 45. As a result, a portion 45 of the polysilicon film 45 near the opening 48 is formed.
a is silicon oxide. At this time, the polysilicon film 4
5 is oxidized from the opening end of the opening 48 by an equal distance in any direction.

Then, the oxidized portion 45a of the silicon nitride film 46 and the polysilicon film 45 is removed by etching using hydrofluoric acid or the like. Thereby, the polysilicon film 45 has
Opening 4 when n ⁺ -type source regions 4a and 4b are formed
8, an opening 49 which is larger in each direction by a predetermined amount is formed. [Step shown in FIG. 12B] Then, the silicon nitride film 4
6 and the oxidized portion 45a of the polysilicon 45 are removed, and then a p-type impurity (for example, boron or aluminum) is ion-implanted using the polysilicon film 45 as a mask. Thus, p ⁻ -type silicon carbide base regions 3a and 3b are formed.

At this time, the opening end of the opening 49 is
The distance to the opening end of 2a is almost
Since they are equal, the silicon nitride film 46 is used as a mask.
N formed⁺Type source regions 4a, 4b and polysilicon.
P formed by using the capacitor film 45 as a mask^-Type silicon carbide base
Are formed in a self-aligned manner. this
After that, the polysilicon film 45 is removed and photo-etching is performed.
By p^--Type silicon carbide base regions 3a, 3b and n
⁺In the center of the mold source regions 4a and 4b, n ⁺Type source area
P through areas 4a, 4b^--Type silicon carbide base region 3
Contact holes reaching a and 3b are formed. Further
Such as epitaxially growing the surface channel layer 5 in FIG.
Through the steps shown in FIG. 21 to FIG.
The type power MOSFET is completed.

The vertical power MOSFET thus completed
In T, the same effects as in the first embodiment can be obtained because the n ⁺ type source regions 4a and 4b and the p ⁻ type silicon carbide base regions 3a and 3a are formed in a precise positional relationship. (Sixth Embodiment) A vertical power MO shown in this embodiment
The SFET is shown in FIG. In the present embodiment, n ⁺ type source regions 4a and 4b and p ⁻ type silicon carbide base regions 3a and 3b
In addition to b, the deep base layers 30a and 30b can be formed in a self-aligned manner. It should be noted that the vertical power MOSFET shown in FIG.
Since the configuration is almost the same as that of the SFET, only different portions will be described, and similar portions will be denoted by the same reference numerals and description thereof will be omitted.

As shown in FIG. 13, the surface of n ⁻ -type silicon carbide epilayer 2 in which p ⁻ -type silicon carbide base regions 3a and 3b and n ⁺ -type source regions 4a and 4b are formed is formed of p ⁻ -type silicon carbide. A concave portion 50 is formed at the center of the base regions 3a and 3b. The concave portion 50 is composed of a bottom surface 50a forming a horizontal direction on the substrate surface and a side surface 50b forming a substantially tapered shape with respect to the substrate surface, and has a so-called bathtub shape.

This concave portion 50⁺Mold source region 4a,
4b through p^-Type silicon carbide base regions 3a, 3b
Has been reached. At the bottom of this recess 50
And p ^-Type silicon carbide base regions 3a and 3b are partially deep
This portion is formed in the deep base layer 30.
a and 30b. This p^-Type silicon carbide base
Deep base layer 3 in which regions 3a and 3b are partially deepened
0a and 30b are horizontal bottom surfaces 50a on the substrate surface.
And a side surface 50b having a substantially tapered shape with respect to the substrate surface.
And has a shape substantially parallel to the concave portion 50.
Further, the deep base layers 30a and 30b have n⁺Mold saw
Formed at a position that does not substantially overlap with the storage regions 4a and 4b
Have been.

Here, if side surface 50b of concave portion 50 is perpendicular to the substrate surface, the shortest distance from the corner of concave portion 50 to n ⁻ -type silicon carbide epilayer 2, ie, the vicinity of the corner of concave portion 50 In this case, the width of p ⁻ -type silicon carbide base regions 3a and 3b becomes very small, so that the resistance value in this portion becomes high. However, n
^- type silicon carbide epitaxial layer 2, p ^- type silicon carbide base region 3
In order to make it difficult to operate a parasitic transistor composed of a, 3b and n ⁺ -type source regions 4a, 4b, it is preferable to further reduce the internal resistance of p ⁻ -type carbonized base regions 3a, 3b. Therefore, the concave portion 50 and the deep base layer 30 are formed so that the shortest distance from the corner of the concave portion 50 to the n ⁻ -type silicon carbide epitaxial layer 2 can be made as long as possible.
The side surface 50b of each of a and 30b has a tapered shape.

Further, surface channel layer 5a is arranged above the surface of n ⁺ type source regions 4a, 4b. This is because the surface channel layer 5a is formed after forming the n ⁺ -type base regions 4a and 4b. The vertical power MOSFET according to the present embodiment is different from the conventional power MOSFET shown in FIG.

Next, the vertical power MOS shown in FIG.
The manufacturing process of the FET will be described with reference to FIGS. However, in these figures, only the parts different from the conventional manufacturing steps shown in FIGS. 21 to 23 described above are shown, and the description of the same parts is omitted. First, as shown in FIG. 21A, n ⁺ type silicon carbide semiconductor substrate 1
On which an n ⁻ -type silicon carbide epilayer 2 is formed. Then, the following steps are sequentially performed.

[Step shown in FIG. 14 (a)] A polysilicon film 51 is formed to a desired thickness on the n ⁻ -type silicon carbide epilayer 2 and a silicon oxide film (SiO ₂ film) 52 is further formed. Is formed with a thickness of After the photoresist 53 is deposited, the n ⁺ -type source region 4 in the photoresist is deposited.
Open regions where a and 4b are to be formed.

[Step shown in FIG. 14B] CF ₄ + H ₂
An opening 52a is provided in a region of the silicon oxide film 52 where the n ⁺ -type source regions 4a and 4b are to be formed by RIE (reactive ion etching) using a gas. At this time, since the etching is performed using the CF ₄ + H ₂ gas, only the silicon oxide film is selectively etched, and the polysilicon film 51 remains without being etched.

[Step shown in FIG. 14C] Next, a part of the polysilicon film 51 is removed by dry etching, and an opening is formed in a region where the p ⁻ -type silicon carbide base regions 3 a and 3 b are to be formed. 51a is provided. Specifically, the region is opened by laterally etching the polysilicon film 51. The amount of the dry etching is controlled by selecting an etching gas, controlling the etching time, and the like. At this time, since the amount of dry etching in the horizontal direction is equal in any direction, the distance from the opening end of the opening 52a to the opening end of the opening 51a is equal in any direction.

[Step shown in FIG. 15A] After removing the photoresist 53, ion implantation is performed using the silicon oxide film 52 as a mask to form n ⁺ -type source regions 4a and 4b. [Step shown in FIG. 15B] A TEOS oxide film 54 is deposited on the entire surface of the silicon oxide film 52 including the opening 52a (the entire surface of the wafer). Thereby, the opening 52a
The inside is also filled with the TEOS oxide film 54. At this time, TE
The portion of the OS oxide film 54 that has entered the opening 52 is formed at the central portion of the opening 52 with the same thickness as that on the silicon oxide film 52, and in the vicinity of the opening end of the opening 52, another portion is formed. It is formed thicker than the central part. Also,
At this time, the TEOS oxide film 54 that has entered the opening 52
The thickness from the opening end of the opening 52 is substantially the same at any position.

[Step shown in FIG. 15 (c)] T is maintained until the TEOS oxide film 54 on the silicon oxide film 52 disappears.
The EOS oxide film 54 is etched back. This gives T
The EOS oxide film 54 has a thicker portion (except for the central portion) of the EOS oxide film 54 that has entered the opening portion 52a, and the central portion is opened, so that the opening area of the opening portion 52a is reduced. Also, at this time, the thickness of the remaining TEOS oxide film 54 from the opening end of the opening 52 is substantially the same at any position.

[Step shown in FIG. 16A] Isotropic dry etching is performed using the silicon oxide film 52 and the TEOS oxide film 54 as a mask. Thus, n ^- -type silicon carbide epitaxial layer 2, a substantially parallel bottom surface 50a is the substrate surface, such as side 50b forms a tapered shape with respect to the substrate surface, n ⁺ -type source region 4a, Recess 5 penetrating through 4b
0 is formed. The recess 50 is provided with the opening 52 and the opening 5.
1 is formed substantially at the center.

[Step shown in FIG. 16B] Silicon oxidation
After removing the film 52 and the TEOS oxide film 54, the polysilicon
The film 54 is exposed. [Step shown in FIG. 16C] Then, the polysilicon film 5 is formed.
4 as a mask with p-type impurities (for example, boron or aluminum).
Ion). At this time, the ion implantation depth
Is constant, but n ^-Recesses 50 in the silicon carbide epilayer 2
Is formed, so that the concave portion 50 is formed.
The p-type impurity is ion-implanted deeply. Specifically
Means that a p-type impurity is implanted by a predetermined depth from the surface of the concave portion 50.
Therefore, in the portion where the concave portion 50 is formed,
The p-type impurity is implanted only partially deeply,
P-type impurities are implanted so as to be substantially parallel to the above. to this
Than p^-Type silicon carbide base regions 3a and 3b are formed
The deepened part is the deep base layer 30.
a and 30b.

The opening 5a extends from the opening end of the opening 51a.
Since the distance to the opening end of 2a is almost equal at any position, n ⁺ -type source regions 4a and 4b formed using silicon oxide film 52 as a mask and polysilicon film 51 as a mask are formed. P ⁻ -type silicon carbide base regions 3a and 3b are formed in a self-aligned manner. Thereafter, the polysilicon film 51 is removed, and the surface channel layer 5a is further epitaxially grown.
Through the process shown in FIG. 13, the vertical power MOSF shown in FIG.
ET is completed.

The vertical power MOSFET thus completed
T is an n ⁺ type source region and ap ⁻ type silicon carbide base region 3
Since the elements a and 3a are formed in a self-aligned manner, the characteristic fluctuation of the element is small. (Seventh Embodiment) In this embodiment, a case where a vertical power MOSFET is manufactured by using a method different from that of the first embodiment will be described. Since the structure of the vertical power MOSFET is the same as that shown in FIG. 13, the description of the structure is omitted.

Hereinafter, the vertical power MO in this embodiment will be described.
The manufacturing process of the SFET will be described with reference to FIGS. In these figures, only the parts different from the conventional manufacturing steps shown in FIGS. 21 to 23 described above are shown,
The description of the same parts is omitted. [Step shown in FIG. 17 (a)] A silicon oxide film 61, a polysilicon film 62, a silicon (Si ₃ N ₄ ) nitride film 63 and a silicon oxide film 64 are respectively formed on the n ⁻ -type silicon carbide epilayer 2 as desired. Films are formed in order of thickness. Then, after depositing the photoresist 65, the regions of the photoresist where the n ⁺ -type source regions 4a and 4b are to be formed are opened.

[Step shown in FIG. 17B] The n ⁺ -type source regions 4a and 4b of the silicon oxide film 64, the silicon nitride film 63 and the polysilicon film 62 are formed by RIE (reactive ion etching). An opening 70 is provided in a region to be formed. [Step shown in FIG. 17C] After removing the photoresist 65, the silicon oxide film 64, the silicon nitride film 63,
Ion implantation is performed using the polysilicon film 62 and the silicon oxide film 61 as a mask, and the n ⁺ -type source regions 4a, 4b
To form

[Step shown in FIG. 18A] A TEOS oxide film 66 is deposited on the entire surface of the silicon oxide film 64 including the opening 70. Thus, the opening 70 is also filled with the TEOS oxide film 66. At this time, TEOS
The portion of the oxide film 66 that has entered the opening 70 is
The central portion of the opening 70 is formed with the same thickness as that on the silicon oxide film 64, and near the opening end of the opening 70 is formed thicker than the other central portions. Further, the thickness of the TEOS oxide film 66 that has entered the opening 70 from the opening end of the opening 70 is substantially the same at any position.

By increasing the height of silicon oxide film 64, the thickness of TEOS oxide film 66 from the opening end of opening 70 can be increased. [Step shown in FIG. 18B] T
The TEOS oxide film 66 is etched back until the EOS oxide film 66 disappears. As a result, of the TEOS oxide film 66 that has entered the opening 70, a thicker portion (other than the central portion) remains, and the central portion is opened. Thus, the opening area of the opening 70 is reduced. At this time, the thickness of the remaining TEOS oxide film 66 from the opening end of the opening 70 is substantially the same at any position.

[Step shown in FIG. 18C] Isotropic dry etching is performed using the silicon oxide film 64 and the TEOS oxide film 66 as a mask. Thus, n ^- -type silicon carbide epitaxial layer 2, a substantially parallel bottom surface 60a is the substrate surface, such as side 60b forms a tapered shape with respect to the substrate surface, n ⁺ -type source region 4a, Recess 6 penetrating through 4b
0 is formed. The recess 60 is formed substantially at the center of the opening 70.

[Step shown in FIG. 19A] The silicon oxide film 63 and the TEOS oxide film 66 are removed to expose the silicon nitride film 63. [Step shown in FIG. 19B] LOCOS oxidation is performed using the silicon nitride film 62 as a mask to partially oxidize the polysilicon film 62. Thus, the portion 62a of the polysilicon film 62 near the opening 70 becomes silicon oxide. At this time, the polysilicon film 62 is oxidized by an equal distance in any direction from the opening end of the opening 70.

Then, the oxidized portions 62a of the silicon nitride film 63 and the polysilicon film 62 are removed by etching using hydrofluoric acid or the like. Thereby, the polysilicon film 62 has
Opening 7 when n ⁺ -type source regions 4a and 4b are formed
An opening 71 which is larger than 0 by a predetermined amount in any direction is formed. [Step shown in FIG. 19C] Then, the polysilicon film 6
2 is used as a mask to ion-implant p ^- type impurities (for example, boron or aluminum). At this time, the ion implantation depth is constant, but the recess 6 is formed in the n ⁻ -type silicon carbide epilayer 2.
Since 0 is formed, p-type impurities are ion-implanted to the depth corresponding to the formation of the concave portion 60. Specifically, since the p-type impurity is implanted by a predetermined depth from the surface of the concave portion 60, the p-type impurity is implanted to a part deeper in the portion where the concave portion 60 is formed.
A p-type impurity is implanted so as to be substantially parallel to the recess 60. Thereby, p ^- type silicon carbide base regions 3a, 3b
Are formed, and the partially deepened portions become the deep base layers 30a and 30b.

Further, from the opening end of the opening 71 to the opening 70
Since the distances to the opening ends are almost equal at any position, the n ⁺ -type source regions 4a and 4b formed using the silicon oxide film 64 as a mask and the p ⁺ formed using the polysilicon film 62 as a mask are used. ^- type silicon carbide base region 3a, and the 3b are formed in a self-aligned manner. Thereafter, the polysilicon film 62 and the silicon oxide film 61 are removed, and the surface channel layer 5a is further epitaxially grown.
Through the steps shown in FIGS. 21 to 23, the vertical power MOSFET of this embodiment is completed.

The vertical power MOSFET thus completed
In T, since the n ⁺ -type source regions 4a and 4b and the p ⁻ -type silicon carbide base regions 3a and 3a are formed in a self-alignment manner, the characteristic variation of the element is small. (Other Embodiments) In the first to fourth embodiments, the case where the deep base layers 30a and 30b are not formed is shown. However, p-type impurities are ion-implanted through contact holes to separate them. It can also be formed. At this time, deep base layers 30a and 30b can have a higher concentration than other portions of p ⁻ -type silicon carbide base regions 3a and 3b.

In the above embodiment, n⁺Mold source region 4
a, 4b and p^-Type silicon carbide base regions 3a, 3b
In order to form in self-alignment, a stack of multiple films
Although used as a mask, p^-Type silicon carbide base region
When forming 3a and 3b, n ^-Type silicon carbide epilayer 2
The concave portions 50 and 60 are provided, and the concave portions 50 and 60 are shaped.
If ion implantation is performed on the formed part, less
Form deep base layers 30a, 30b with energy
Can be

Further, deep base layers 30a and 30b can be formed in a step different from other portions of p ⁻ -type silicon carbide base regions 3a and 3b. At this time, the deep base layers 30a, 30b are changed to the p ⁻ -type silicon carbide base regions 3a, 3a.
b can be formed at a higher concentration than other portions. In the above embodiment, p ^- type silicon carbide base region 3
a, 3b, after forming the n ⁺ type source regions 4a, 4b,
To form the gate insulating film 7, see Japanese Patent Application Laid-Open No. 6-15186.
There is no problem that the life of the gate insulating film, which is generated by the method disclosed in Japanese Patent Publication No. 0-086, is reduced.

In the above embodiment, when indicating the crystal form of silicon carbide, the expression should be affixed with a bar above the required number. However, since the expression means is restricted, it is not described herein. Instead of adding a bar above the required number, the required number is indicated with a "-" after the number.

[Brief description of the drawings]

FIG. 1 is a planer type power MOS according to a first embodiment.
FIG. 3 is a cross-sectional view showing an FET.

FIG. 2 is a view showing a manufacturing process of the planar power MOSFET shown in FIG. 1;

FIG. 3 is a view showing a manufacturing step of the planar power MOSFET following FIG. 2;

FIG. 4 is a planer type power MOS according to a second embodiment.
FIG. 3 is a cross-sectional view showing an FET.

FIG. 5 is a view showing a manufacturing process of the planar power MOSFET shown in FIG. 4;

FIG. 6 is a view illustrating a manufacturing step of the planar power MOSFET following FIG. 5;

FIG. 7 is a planer type power MOS according to a third embodiment.
FIG. 3 is a cross-sectional view showing an FET.

FIG. 8 is a view showing a manufacturing process of the planar power MOSFET shown in FIG. 7;

FIG. 9 is a planer type power MOS according to a fourth embodiment.
It is a figure showing the manufacturing process of FET.

FIG. 10 is a view showing a manufacturing process of the planar power MOSFET shown in FIG. 9;

FIG. 11 is a planer type power MO according to a fifth embodiment.
It is sectional drawing which shows the manufacturing process of SFET.

FIG. 12 is a planer type power MOSFET following FIG. 11;
It is a figure which shows the manufacturing process of.

FIG. 13 is a planer type power MO according to a sixth embodiment.
FIG. 3 is a cross-sectional view illustrating an SFET.

FIG. 14 is a planer type power MOSFET shown in FIG.
It is a figure which shows the manufacturing process of.

FIG. 15 is a planer type power MOSFET following FIG. 14;
It is a figure which shows the manufacturing process of.

FIG. 16 is a planer type power MOSFET following FIG.
It is a figure which shows the manufacturing process of.

FIG. 17 is a planer type power MO according to a seventh embodiment.
It is a figure showing the manufacturing process of SFET.

FIG. 18 is a planer type power MOSFET following FIG. 17;
It is a figure which shows the manufacturing process of.

FIG. 19 is a planer type power MOSFET following FIG. 18;
FIG. 6 is a cross-sectional view showing a manufacturing process of the second embodiment.

FIG. 20 is a vertical power MOSF filed by the present applicant.
It is sectional drawing which shows the structure of ET.

FIG. 21 is a diagram illustrating a manufacturing process of the vertical power MOSFET illustrated in FIG. 20;

FIG. 22 is a view illustrating a manufacturing step of the vertical power MOSFET following FIG. 21;

FIG. 23 is a view illustrating a manufacturing step of the vertical power MOSFET following FIG. 22;

FIG. 24 shows a conventional M using self-alignment technology.
It is a figure showing the manufacturing process of OSFET.

[Explanation of symbols]

1 ... n ⁺ -type silicon carbide semiconductor substrate, 2 ... n ^- -type silicon carbide epitaxial layer, 3a, 3b ... p ^- type silicon carbide base region, 4a, 4b ... n ⁺ -type source region, 5 ... surface channel layer (n ^- 7: gate insulating film, 8: gate electrode, 9: insulating film, 10: source electrode, 11: drain electrode, 20, 22, 23, 25 ... mask material, 30a, 3
0b: deep base layer, 41: silicon nitride film, 42
... Silicon oxide film, 45 ... Polysilicon film, 46 ... Silicon nitride film, 50, 60 ... Concave part, 50a, 60a ... Bottom surface, 50b, 60b ... Side, 51, 62 ... Polysilicon film, 52, 61, 64 ... Silicon Oxide film, 63: silicon nitride film, 54, 66: TEOS oxide film.

Claims (11)

[Claims] 1. A first conductivity type semiconductor layer (2) made of silicon carbide having a higher resistance than this semiconductor substrate is formed on a main surface of a first conductivity type semiconductor substrate (1) made of silicon carbide. A step of forming a mask material (20) on the semiconductor layer; and forming an opening (2) having a side surface inclined in a predetermined region of the mask material.
0a); performing ion implantation from the opening using the mask material as a mask to form a second conductivity type base region (3a, 3b); and forming the opening using the mask material as a mask. Forming a source region (4a, 4b) having a junction depth smaller than that of the base region in the base region by performing more ion implantation; removing the mask material; Forming a gate electrode on a surface portion of the base region sandwiched between the semiconductor layer and forming a source electrode electrically connected to the base region and the source region; And forming a drain electrode (11) on a side of the semiconductor substrate opposite to the main surface, a method for manufacturing a silicon carbide semiconductor device. 2. The method of manufacturing a silicon carbide semiconductor device according to claim 1, wherein the size of said source region is controlled by changing an inclination angle of a side surface of an opening of said mask material. 3. A first conductivity type semiconductor layer (2) made of silicon carbide having a higher resistance than the semiconductor substrate is formed on a main surface of a first conductivity type semiconductor substrate (1) made of silicon carbide. Forming a first mask material (22) on the semiconductor layer; and forming a first opening (22) in a predetermined region of the first mask material.
forming a), performing ion implantation from the first opening using the first mask material as a mask, and forming a first conductivity type base region (3a, 3b) in a surface layer of the semiconductor layer. Performing a second step on the first mask material including the first opening.
Depositing the mask material, and removing the second mask material until the first mask material is exposed, and forming a second opening smaller than the first opening in the second mask material. Forming a portion; performing ion implantation from the second opening using the first and second mask materials as a mask; and forming a source region (shallower in junction depth than the base region) in the base region. 4a, 4
b); removing the first mask material and the second mask; and at least over a surface layer of the base region sandwiched between the source region and the semiconductor layer. Forming a gate electrode and forming a source electrode electrically connected to the base region and the source region; and forming a drain on a side of the semiconductor substrate opposite to the main surface. Forming a electrode (11). A method for manufacturing a silicon carbide semiconductor device, comprising: 4. The method of manufacturing a silicon carbide semiconductor device according to claim 3, wherein the size of said source region is controlled by controlling a film thickness of said second mask material. 5. A first conductivity type semiconductor layer (2) made of silicon carbide having a higher resistance than the semiconductor substrate is formed on a main surface of a first conductivity type semiconductor substrate (1) made of silicon carbide. A step of forming a mask material (25) on the semiconductor layer; a step of forming an opening (25a) in a predetermined area of the mask material; Forming a second conductivity type base region (3a, 3b) by oblique ion implantation at a predetermined angle to the substrate, and performing ion implantation from the opening using the mask material as a mask. Forming a source region (4a, 4b) having a junction depth smaller than the base region therein; removing the mask material; at least the base sandwiched between the source region and the semiconductor layer Surface of area Forming a gate electrode (8) on the substrate and forming a source electrode (10) electrically connected to the base region and the source region; and opposing the main surface of the semiconductor substrate. Forming a drain electrode (11) on the side of the silicon carbide semiconductor device. 6. The method according to claim 5, wherein in the step of forming the base region, the size of the base region is controlled by controlling an acceleration voltage and an angle of the oblique ion implantation. Of manufacturing a silicon carbide semiconductor device. 7. A first conductivity type semiconductor layer (2) made of silicon carbide having a higher resistance than the semiconductor substrate is formed on a main surface of a first conductivity type semiconductor substrate (1) made of silicon carbide. A first and second mask material (41, 5) on the semiconductor layer.
1, 42, 52), a step of providing a first opening (42a, 52a) in the second mask material (42, 52), and a step of forming the second opening from the first opening. 1 mask material (41, 5
1) etching to form second openings (41a, 51a) larger than the first openings; and ion implantation from the first openings using the second mask material. Forming a first conductivity type source region (4a, 4b); removing the second mask material; and using the first mask material as a mask to remove the second conductive material from the second opening. Ion implantation is performed, and a second conductivity type base region (3a, 3a,
b) forming a gate electrode (8) on at least a surface portion of the base region sandwiched between the source region and the semiconductor layer, and electrically connecting the base region and the source region to each other. Forming a source electrode (10) to be electrically connected; and forming a drain electrode (11) on a side of the semiconductor substrate opposite to the main surface. A method for manufacturing a semiconductor device. 8. The method of manufacturing a silicon carbide semiconductor device according to claim 7, wherein said first mask material is made of a silicon nitride film, and said second mask material is made of a silicon oxide film. . 9. A first conductivity type semiconductor layer (2) made of silicon carbide having a higher resistance than the semiconductor substrate is formed on a main surface of a first conductivity type semiconductor substrate (1) made of silicon carbide. A first and second mask material (45, 6) on the semiconductor layer.
2, 46, 63), a step of providing first openings (48, 70) penetrating the first and second mask materials, and a step of providing the first and second mask materials. The first conductive type source region (4a,
4b), and after LOCOS-oxidizing the first mask material using the second mask material as a mask, the oxidized portions (45a, 62a) of the second mask material and the first mask material ) To provide a second opening (49, 71) larger than the first opening in the first mask material; and using the first mask material as a mask, Ion implantation is performed from the opening of the second conductive type base region (3a, 3a, 3b) in a predetermined region of the semiconductor layer including the source region.
b) forming a gate electrode (8) on at least a surface portion of the base region sandwiched between the source region and the semiconductor layer, and electrically connecting the base region and the source region to each other. Forming a source electrode (10) to be electrically connected; and forming a drain electrode (11) on a side of the semiconductor substrate opposite to the main surface. A method for manufacturing a semiconductor device. 10. The method of manufacturing a silicon carbide semiconductor device according to claim 9, wherein said first mask material is made of polysilicon, and said second mask material is made of a silicon nitride film. Method. 11. After the step of forming the base region,
A surface channel layer serving as a channel region on the base region so as to connect the source region and the semiconductor layer;
11. The silicon carbide according to claim 1, further comprising: forming the gate electrode on the surface channel layer in the step of forming the gate electrode. A method for manufacturing a semiconductor device.