JP2009147381A - Method of manufacturing sic vertical mosfet - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To obtain a semiconductor device wherein the trade-off relation between channel resistance and JFET resistance, which is an obstacle to device miniaturization, is improved and the same mask is used to form a source region and a base region by ion implantation, and to provide a method of manufacturing the same. <P>SOLUTION: In a vertical MOSFET that uses SiC, a source region 4 and a base region 5 are formed by ion implantation using the same tapered mask 9 to give the base region 5 a tapered shape. The taper angle of the tapered mask 9 is set to 30 to 60° when the material of the tapered mask 9 has the same range as SiC does in ion implantation, and is set to 20 to 45° when the material of the tapered mask is SiO<SB>2</SB>. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to a method for manufacturing a vertical MOSFET using SiC, in which a vertical MOSFET using SiC is manufactured by ion implantation.

  Conventionally, when a vertical MOSFET using SiC is manufactured by ion implantation, it is necessary to change the width of a mask used for ion implantation of a source region and a base region (see, for example, Patent Document 1).

Japanese Patent Laid-Open No. 10-233503 (Claim 1)

  However, the above-described conventional method for manufacturing a semiconductor device has a problem that the number of steps for manufacturing a MOSFET increases because different masks are used for ion implantation of the source region and the base region. In addition, the channel length, which is one of the factors that determine the characteristics of the MOSFET, depends on the processing accuracy of each mask and the alignment accuracy of the two masks, and becomes a serious problem when miniaturizing elements. Further, when the element is further miniaturized, there is a problem that the JFET resistance increases in a trade-off relationship with the reduction of channel resistance due to the miniaturization.

  The present invention has been made in view of the above points, and provides a method for manufacturing a vertical MOSFET using SiC capable of improving the trade-off relationship between channel resistance and JFET resistance, which is a problem in miniaturization of elements. For the purpose.

  In addition, when a source region and a base region of a vertical MOSFET using SiC are manufactured by ion implantation, SiC can be manufactured using the same mask, and element miniaturization can be promoted. An object is to obtain a method for manufacturing a vertical MOSFET.

  The vertical MOSFET manufacturing method using SiC according to the present invention has a taper angle of 30 ° or more and 60 ° or less on the surface of the epitaxially grown SiC drift region, and the same ion implantation range as SiC. A p base region having a first conductivity type is formed in the drift region of SiC by implanting first ions into the epitaxial layer of SiC through the surface using an ion implantation mask using And implanting second ions into the SiC drift region through the surface using the ion implantation mask so that at least the base region is within a range of 30 ° to 60 °. Forming a source region having a second conductivity type in the p base region so as to have a side surface forming an angle with respect to a normal to the surface; Equipped with a.

The first epitaxial layer is formed on the epitaxial layer of SiC through the surface by using a SiO ₂ mask having a taper angle of 20 ° to 45 ° on the surface of the epitaxially grown SiC drift region as an ion implantation mask. To form a p base region having the first conductivity type in the SiC drift region, and to the SiC drift region through the surface using the ion implantation mask. A second ion is implanted into the p base region such that at least the base region has a side surface that forms an angle with respect to a normal to the surface within a range of 30 ° to 60 ° by implanting second ions. Forming a source region having a conductivity type.

  Further, a mask using a material having a side surface substantially parallel to the normal to the surface of the SiC drift region on the surface of the epitaxially grown SiC drift region and having the same ion implantation range as SiC is used as an ion implantation mask. Using a first conductivity type in the SiC drift region by implanting a first ion into the SiC drift region through the surface in a direction that forms an angle of 70 ° or less on the surface. Forming a p base region having, and implanting second ions into the SiC layer through the surface in a direction substantially parallel to the normal using the ion implantation mask, On the opposite side of the first conductivity type in the base region such that the channel length of the p base region measured along is at least 0.3 microns. It comprises forming a source region having a second conductivity type.

Furthermore, on the surface of the epitaxially grown SiC drift region, a SiO ₂ mask having a side surface substantially parallel to the normal to the surface of the SiC drift region is used as an ion implantation mask, and the surface is 75 ° or less. Forming a p-base region having a first conductivity type in the SiC drift region by implanting first ions into the SiC drift region through the surface in a direction to form an angle; Using the ion implantation mask, the p base region is compared with the source region by implanting second ions into the SiC drift region through the surface in a direction substantially parallel to the normal. A source having a second conductivity type opposite the first conductivity type in the p base region so as to have a thickness of at least 0.3 microns And a forming a band.

  According to the present invention, by tapering the base region of the vertical MOSFET using SiC, the trade-off relationship between the channel resistance and the JFET resistance can be improved, and the device can be miniaturized.

  According to the present invention, when manufacturing a vertical MOSFET using SiC, the source region and the base region are formed by ion implantation using the same mask, and selective impurity doping is performed in a self-alignment manner. Thus, a MOSFET can be manufactured, and miniaturization of the element can be promoted.

It is sectional drawing which shows the semiconductor device (SiC vertical MOSFET) produced by Embodiment 1 of this invention. It is a figure for demonstrating the element structure of the semiconductor device produced by Embodiment 1 of this invention. It is a figure for demonstrating the on-resistance of the semiconductor device produced by Embodiment 1 of this invention. It is a figure which shows the result of having investigated by experiment the relationship between the space | interval Ld of the p base region 5 and JFET resistance Rj in the semiconductor device produced by Embodiment 1 of this invention. FIG. 6 is a diagram for explaining the relationship between the taper angle θ of the p base region 5 and the channel length Lch and the distances Ld1 and Ld2 between the p base regions in the semiconductor device manufactured according to the first embodiment of the present invention; The case where is formed is shown. FIG. 6 is a diagram for explaining the relationship between the taper angle θ of the p base region 5 and the channel length Lch and the distances Ld1 and Ld2 between the p base regions in the semiconductor device manufactured according to the first embodiment of the present invention; The case where no is formed is shown. FIG. 7 is a diagram showing the relationship between the taper angle of p base region 5 and the on-resistance in the semiconductor device manufactured according to the first embodiment of the present invention, and shows a case where a taper is formed in n source region 4. FIG. 7 is a diagram showing the relationship between the taper angle of p base region 5 and on-resistance in the semiconductor device manufactured according to the first embodiment of the present invention, and shows a case where no taper is formed in n source region 4. It is a figure explaining the limit which the taper angle of the p base area | region 5 and punch through generate | occur | produce in the semiconductor device produced by Embodiment 1 of this invention. FIG. 10 is a diagram for explaining a method for manufacturing a semiconductor device according to a second embodiment of the present invention, and is a diagram for explaining a method of forming a source region 4 and a base region 5 by ion implantation. FIG. 9 is a diagram showing the relationship between the taper angle of the mask, the channel length Lch, and the taper angle of the p base region 5 in the semiconductor device manufactured according to the second embodiment of the present invention, and showing the same range of the implantation mask and SiC. is there. In view showing the taper angle and the channel length of the mask in the semiconductor device manufactured in accordance with the second embodiment of the invention Lch, p taper angle of the base region 5 relationship, implantation mask is a diagram showing the case of SiO _2. It is sectional drawing which shows the semiconductor device (SiC vertical MOSFET) produced by Embodiment 3 and 5 of this invention. FIG. 10 is a diagram for explaining a method of manufacturing a semiconductor device according to a third embodiment of the present invention and is a diagram for explaining a method of forming a source region 4 and a base region 5 by ion implantation. It is a figure which shows the relationship between the ion implantation angle in the semiconductor device produced by Embodiment 3 of this invention, channel length Lch, and the taper angle of p base region 5, and is a figure which shows the case where the implantation mask and the range of SiC are the same. . A diagram showing an ion implantation angle and the channel length Lch, the relationship of the taper angle of the p base region 5 in the semiconductor device manufactured in accordance with the third embodiment of the present invention, the implantation mask is a diagram showing a case of SiO _2. It is a figure which shows the relationship between the ion implantation angle and on-resistance in the semiconductor device produced by Embodiment 3 of this invention, and is a figure which shows the case where the implantation mask and the range of SiC are the same. A diagram showing an ion implantation angle and the on-resistance relationship in the semiconductor device manufactured in accordance with the third embodiment of the present invention, the implantation mask is a diagram showing a case of SiO _2. It is sectional drawing which shows the semiconductor device (SiC vertical MOSFET) produced by Embodiment 4 and 6 of this invention. FIG. 10 is a diagram for explaining a method of manufacturing a semiconductor device according to a fourth embodiment of the present invention and is a diagram for explaining a method of forming a source region 4 and a base region 5 by ion implantation. FIG. 10 is a diagram for explaining a method of manufacturing a semiconductor device according to a fifth embodiment of the present invention and is a diagram for explaining a method of forming a source region 4 and a base region 5 by ion implantation. FIG. 10 is a diagram for explaining a method of manufacturing a semiconductor device according to a sixth embodiment of the present invention and is a diagram for explaining a method of forming a source region 4 and a base region 5 by ion implantation.

  First, the outline of the present invention will be described. When manufacturing a vertical MOSFET using SiC, it is difficult to diffuse impurities by heat treatment, and a self-alignment process using thermal diffusion of impurities as used in manufacturing a vertical MOSFET using Si is performed. I can't. Usually, selective impurity doping is performed by ion implantation.

  Regarding the shape of the region formed by ion implantation, it was difficult to control the shape (taper angle) of the ion implantation region because the thermal diffusion was large in the case of Si, but in the case of SiC, the thermal diffusion was almost ignored. Therefore, the shape (taper angle) in the depth direction and the lateral direction of the ion implantation region can be easily controlled.

  In the past, the side surface of the implantation mask was vertical, and ion implantation was performed from the direction perpendicular to the substrate. At that time, it is impossible to dope impurities by a self-alignment process using the same mask. There is a need to use masks having different widths when ion implantation is performed on the source region and the base region. In addition, activation annealing at about 1500 ° C. is necessary after ion implantation, and there is a possibility of damage such as roughening of the SiC surface when activation annealing is performed.

  For this reason, when a gate electrode is used as the same mask used for ion implantation, the gate electrode is used as an implantation mask in order to damage the gate electrode and the gate oxide film when activation annealing is performed. It is difficult.

  Therefore, the vertical MOSFET using SiC according to the present invention is characterized in that the same mask for ion implantation is used when the source region and the base region are formed by ion implantation. The mask is tapered or ion implantation from an oblique direction is performed, whereby selective impurity doping is performed by self-alignment to produce a MOSFET. Since the base region manufactured by this method has a tapered shape, the JFET resistance is smaller than that of a conventional base region having a substantially vertical shape. Hereinafter, specific embodiments will be described.

Embodiment 1 FIG.
1 is a cross-sectional view showing a semiconductor device (SiC vertical MOSFET) manufactured according to the first embodiment of the present invention. A source region 4 and a base region 5 are formed by ion implantation in a drift region 6 epitaxially grown on a substrate 7, and a gate oxide film 2, a gate electrode 1, a source electrode 3, and a drain electrode 8 are formed to produce a MOSFET. .

  In this semiconductor device, as shown in FIG. 2, the effect of setting the taper angle θ in the p base region 5 will be described. As shown in FIG. 3, the on-resistance representing the performance of the semiconductor device (vertical MOSFET) has several components, that is, source contact resistance Rcs, n source sheet resistance Rn +, channel resistance Rch, JFET resistance Rj, drift resistance. Rd, substrate resistance Rsub, and drain contact resistance Rcd. In the case of a vertical MOSFET using SiC, the channel resistance Rch is the highest at present, which is the biggest problem for practical application of the SiC vertical MOSFET.

  As a method for reducing the channel resistance Rch, there is miniaturization of elements (shortening the channel length of the MOSFET and increasing the channel width). In this case, there is a trade-off relationship that the interval between the p base regions 5 (see FIG. 2, Ld1: the upper interval between the p base regions 5 and Ld2: the lower interval between the p base regions 5) is shortened, and the JFET resistance Rj is increased. is there. Inserting the taper angle θ of the P base region 5 has an effect of improving the trade-off relationship between the channel resistance Rch and the JFET resistance Rj.

In order to specifically estimate this effect, first, a MOSFET test sample having a taper angle θ of 0 ° is prepared, and the relationship between the interval of the p base region 5 and the JFET resistance Rj is experimentally shown in FIG. . The test sample was assumed to be an element having a withstand voltage of 1200 V used for an in-vehicle or industrial inverter, and was prepared using a substrate having a carrier concentration of 1 × 10 ¹⁶ cm ⁻³ and 10 μm in the drift region 6. As a result, it can be seen that the JFET resistance Rj increases rapidly as the interval Ld (Ld = Ld1 = Ld2) between the p base regions 5 decreases.

  From the results shown in FIG. 4, in order to reduce the JFET resistance Rj, the interval Ld between the p base regions 5 may be increased, but in this case, the breakdown voltage of the MOSFET decreases. Actually, as a result of producing and evaluating a test sample, when the distance Ld between the p base regions 5 is 4 μm or more, the electric field applied to the gate oxide film 2 is increased, and the MOSFET is compared with the theoretical breakdown voltage predicted from the pn junction. It was found that the withstand voltage decreased.

  In summary, the distance Ld between the p base regions 5 is preferably smaller from the viewpoint of miniaturization, but when the distance Ld between the p base regions 5 is 2 μm or less, the JFET resistance Rj is reduced. Increases rapidly. Further, when the interval Ld between the p base regions 5 is 4 μm or more, the breakdown voltage of the MOSFET is lowered. Therefore, the interval Ld between the p base regions 5 is optimally 2 to 4 μm.

  Based on the above results, the trade-off relationship between the JFET resistance Rj and the channel resistance Rch when the taper angle θ of the p base region 5 is inserted will be examined. That is, the relationship between the taper angle θ, the JFET resistance Rj, and the channel resistance Rch is calculated with the assumption of an element having a withstand voltage of 1200 V used for an in-vehicle or industrial inverter.

  As a structure of the MOSFET, for simplification, when the taper angle θ is inserted in the p base region 5, the case where the same taper angle θ is also included in the n source region 4 and the case where the same taper angle θ is not included (θ = 0 °) are shown in FIG. And with reference to FIG. At this time, assuming that the implantation depth of the p base region 5 is dp and the implantation depth of the n source region 4 is dn, the channel length Lch and the intervals Ld1 and Ld2 between the p base regions 5 are as shown in FIGS. Become a relationship. That is, when the same taper angle θ is formed also in the n source region 4, the channel length Lch = (dp−dn) sinθ and Ld2 = Ld1 + 2 dpsinθ are obtained from FIG. On the other hand, when the taper angle θ is not formed in the n source region 4, the channel length Lch = dpsinθ and Ld2 = Ld1 + 2 dpsinθ are obtained from FIG.

Here, as a parameter of the MOSFET, an element having a withstand voltage of 1200 V used for an in-vehicle or industrial inverter is assumed. As a drift region 6 currently being prototyped, carrier concentration = 1 × 10 ¹⁶ cm ⁻³ , 10 μm The substrate is dp = 0.9 μm and dn = 0.3 μm. Further, the distance Ld2 is calculated with respect to the taper angle θ with Ld1 = 2.5 μm, and the JFET resistance Rj is obtained from FIG. 4 on the assumption that the JFET resistance Rj is determined by the distance Ld2. As for the channel resistance Rch, according to the result of trial production performed by us, the channel resistance Rch = 20 mΩcm ² when the channel length Lch = 2 μm. In the future, it is considered that the channel resistance Rch will be reduced by device miniaturization (shortening the MOSFET channel length and increasing the channel width) and improving the process. Therefore, here, the channel resistance Rch when the channel length Lch = 2 μm. Was assumed to be Rch = 20, ¹⁰ , 5 mΩcm ² . The channel resistance Rch is calculated from the channel length Lch with respect to the taper angle θ, assuming that the channel resistance Rch is proportional to the channel length Lch.

  FIG. 7 and FIG. 8 show the results of calculating the relationship between the ON resistance (= Rj + Rch) and the taper angle θ when the taper angle θ is inserted into the n source region 4 by the above method. When the taper angle θ is smaller (60 ° or less), the channel length Lch is smaller and the channel resistance Rch is smaller. However, when the taper angle θ is 30 ° or less, the lower interval Ld2 of the p base region 5 is smaller and the JFET resistance Rj is smaller. Increased impact comes out. Therefore, the taper angle θ is preferably 30 ° to 60 ° (30 ° or more and 60 ° or less), and is preferably 30 ° to 45 ° (30 ° or more and 45 ° or less).

7 and 8, it is described that the taper angle θ is 30 ° or more and no punch-through occurs. This is because the interval (the minimum value of the interval between the source region 4 and the base region 5) Lp shown in FIG. The angle θ is 30 ° or less and 0.3 μm or less, which indicates that punch through occurs and the breakdown voltage of the MOSFET decreases. In the case of an element having a withstand voltage of 1200 V specifically assumed, the concentration of the p base region 5 is 5 × 10 ¹⁷ to 1 × 10 ¹⁸ cm ⁻³ and the concentration of the drift region is 1 × 10 ¹⁶ cm ⁻³ . When the drain voltage of the MOSFET is 1200 V, the depletion layer extends 0.11 to 0.23 μm toward the p base region 5 side. When the distance Lp is smaller than the depletion layer, punch-through occurs. Considering the margin of the device manufacturing process, punch-through is likely to occur when the distance Lp is 0.3 μm or less. Therefore, in order to prevent punch-through, the taper angle θ is set to 30 ° or more and the distance Lp is set to 0.3 μm or more. It is necessary to be.

  7 and 8, only the result in the case of Ld1 = 2.5 μm is shown, but the taper angle dependency of the on-resistance is Ld1 = 2 to 4 μm which is the optimum value of the interval Ld of the p base region 5. Both are the same. When the upper interval Ld1 of the p base region 5 is 2.5 μm or more, the influence of the JFET resistance Rj is small, and the taper angle dependency of the on-resistance is almost the same as in FIGS. Further, when the upper interval Ld1 of the p base region 5 is 2.5 μm or less, the influence of the JFET resistance Rj is large, and the absolute value of the on-resistance becomes large at any taper angle as compared with FIGS. The dependency on is the same. Therefore, when Ld1 = 2 to 4 μm, the taper angle θ of the p base region 5 is preferably 30 ° to 60 °, and is preferably 30 to 45 ° which is smaller.

  Therefore, according to the first embodiment, by tapering the base region 5 of the vertical MOSFET using SiC, the trade-off relationship between the channel resistance and the JFET resistance can be improved, and the device can be miniaturized. Can proceed.

Embodiment 2. FIG.
FIG. 10 illustrates a method of manufacturing a semiconductor device according to the second embodiment of the present invention in which the source region 4 and the base region 5 of the semiconductor device (SiC vertical MOSFET) shown in FIG. 1 are formed by ion implantation. It is a figure for doing. When ion implantation is performed using a tapered implantation mask 9 as shown in FIG. 10, ions are also implanted under the implantation mask 9 at the tapered end portion 10. The width of the region where ions are implanted under the implantation mask 9 is proportional to the depth of ion implantation. Since the base region 5 is deeply implanted as compared with the source region 4, the region under the mask 9 is not implanted with the source region 4, and a region where only the base region 5 is implanted is formed. This part becomes the channel of the MOSFET. Further, both the source region 4 and the base region 5 are tapered, and there is an effect of improving the trade-off relationship between the JFET resistance Rj and the channel resistance Rch when miniaturization is performed as described in the first embodiment.

The channel length and the taper angle of the base region 5 are determined by the material of the implantation mask 9 and the taper angle θ. Specifically, as the implantation mask 9, (a) a case where the same ion implantation range as that of SiC is used, and (b) SiO ₂ (an implantation range of 1. FIG. 11 and FIG. 12 show the relationship between the shape of the implantation mask, the channel length Lch, and the taper angle of the base region 5 in the case of (7 times). When a material having the same ion implantation range as SiC is used as the implantation mask 9, as shown in FIG. 11, the taper angle θ of the implantation mask 9 and the taper angle θ of the p base region 5 match, (b) the case of using SiO _2, as shown in FIG. 12, the taper angle of the p base region 5 than the taper angle theta implantation mask 9 theta 'is the projected range of SiO ₂ is 1.7 times the SiC Therefore, it becomes large from the relationship of 1.7 tan θ = tan θ ′.

As described in the first embodiment, when a device having a withstand voltage of 1200 V used for an in-vehicle or industrial inverter is manufactured, the taper angle θ of the p base region 5 is preferably 30 ° to 60 °, and is smaller than 30. ~ 45 ° is preferred. Therefore, when the same ion implantation range as SiC is used, the taper angle θ of the implantation mask 9 is 30 ° to 60 °, more preferably 30 to 45 °. When the implantation mask 9 is SiO ₂ , The taper angle θ ′ of the implantation mask 9 is preferably 20 ° to 45 °, more preferably 20 to 30 ° from the relationship of 1.7 tan θ = tan θ ′.

Further, as a method of processing the implantation mask 9 into a desired shape, when SiO ₂ is used as the implantation mask 9, the SiO ₂ and resist etching selectivity ratio is large when dry etching SiO ₂ using the resist mask. For example, only SiO ₂ is etched during dry etching, and the side surface of the SiO ₂ implantation mask becomes vertical. However, when the etching selection ratio is reduced, the resist is also etched during the dry etching of SiO ₂ and used as a mask. The width of the resist used is reduced. When etching is performed under such conditions, the SiO ₂ implantation mask is tapered, and the angle can be controlled by the selection ratio between SiO ₂ and the resist.

  Therefore, according to the second embodiment, selective impurity doping can be performed by the above-described method by a self-alignment process using the same mask 9. Further, the channel length of the MOSFET and the taper angle of the p base region 5 can be easily controlled by the shape of the implantation mask 9, which is advantageous when the MOSFET is miniaturized. Furthermore, the tradeoff relationship between the channel resistance Rch and the JFET resistance Rj can be improved by providing the taper angle of the p base region 5.

Embodiment 3 FIG.
FIG. 13 is a cross-sectional view showing a semiconductor device (SiC vertical MOSFET) fabricated according to the third embodiment of the present invention. A source region 4 and a base region 5 are formed by ion implantation in a drift region 6 epitaxially grown on a substrate 7, and a gate oxide film 2, a gate electrode 1, a source electrode 3, and a drain electrode 8 are formed to produce a MOSFET. .

FIG. 14 illustrates a method for manufacturing a semiconductor device according to the third embodiment of the present invention, and is a diagram for illustrating a method for forming source region 4 and base region 5 by ion implantation. As shown in FIG. 14, for example, when N ions are implanted from a direction perpendicular to the substrate and Al ions are implanted into the substrate from an oblique direction having a smaller implantation angle than N ions, the same side surface as in the prior art is vertical. When the implantation mask 11 is used, N ions are not implanted under the implantation mask 11 and only Al ions are implanted under the implantation mask 11. This part becomes the channel of the MOSFET. Further, when SiO ₂ or the like, which has a longer ion implantation range than SiC, is used as the material of the implantation mask 11, the base region 5 has a tapered shape, and when miniaturization is performed as described in the first embodiment. There is an effect of improving the trade-off relationship between the JFET resistance Rj and the channel resistance Rch.

The channel length and the taper angle of the base region 5 are determined by the material of the implantation mask 11 and the ion implantation angle. Specifically, as the implantation mask 11, (a) a case where the same ion implantation range as that of SiC is used, and (b) SiO ₂ (the implantation range is 1 of SiC which we are currently using for trial production). FIG. 15 and FIG. 16 show the relationship between the ion implantation angle, the channel length Lch, and the taper angle of the base region 5 in the case of. (A) When a material having the same ion implantation range as SiC is used, as shown in FIG. 15, the taper angle of the p base region 5 coincides with the mask shape and becomes vertical. (B) In the case of SiO ₂ , as shown in FIG. 16, the p base region 5 is tapered, and the taper angle θ ′ is larger than 0 °.

Here, in the same manner as in the first embodiment described above, the carrier concentration 1 × 10 of the drift region 6 currently being prototyped assuming an element with a withstand voltage of 1200 V used for a vehicle-mounted or industrial inverter as a parameter of the MOSFET. The optimum value of the implantation angle is examined with ¹⁶ cm ⁻³ , substrate thickness = 10 μm, dp = 0.9 μm, and dn = 0.3 μm.

  First, consider the case where (a) a material having the same ion implantation range as SiC is used as the implantation mask 11. Since the angle of the p base region 5 does not change depending on the implantation angle θ, the JFET resistance Rj does not change. Further, the channel length Lch can be calculated with respect to the ion implantation angle θ, and the channel resistance Rch is obtained. As described in the first embodiment, when the on-resistance (= Rj + Rch) with respect to the ion implantation angle θ is obtained with the interval Ld1 of the p base region 5 = 2.5 μm, the result is as shown in FIG. Here, the case of Ld1 = 2.5 μm is shown, but the tendency of the on-resistance to monotonously decrease with respect to the implantation angle θ is the same regardless of the value of the interval Ld1 of the p base region 5. is there. That is, the on-resistance decreases as the implantation angle θ increases and the channel length Lch decreases. However, when the channel length Lch becomes small, punch-through occurs as in the first embodiment, and the breakdown voltage decreases. That is, in the case of FIG. 15, the channel length Lch can be expressed as Lch = dp · cos θ, and punch-through occurs when Lp = Lch = 0.3 μm or less. Considering this, in order to make the interval Lp 0.3 μm or more, the ion implantation angle θ needs to be 70 ° or less.

  In summary, when (a) a material having the same ion implantation range as SiC is used as the implantation mask 11, the optimum value of the ion implantation angle is θ of 70 ° or less, and the implantation angle is considered in consideration of the margin. It is preferable to set it as 60 degrees-70 degrees with large.

Next, consider the case where (b) SiO ₂ (the implantation range is 1.7 times that of SiC) is used as the implantation mask 11. The channel length Lch and the taper angle θ ′ of the p base region 5 can be calculated with respect to the ion implantation angle θ. As described in the first embodiment, Ld2 is calculated with respect to the taper angle θ ′ with Ld1 = 2.5 μm, and the JFET resistance Rj is obtained from FIG. 4 on the assumption that the JFET resistance Rj is determined by Ld2. When the channel resistance Rch is similarly calculated from the channel length Lch, the on-resistance (= JFET resistance Rj + channel resistance Rch) with respect to the ion implantation angle θ is as shown in FIG.

  Here, the case of Ld1 = 2.5 μm is shown, but when Ld1 = 2 to 4 μm, the tendency of the on-resistance to decrease monotonously with respect to the implantation angle θ is the same. That is, when the implantation angle θ is large and the channel length Lch is small, the on-resistance decreases and the influence of the JFET resistance Rj changing is small. Further, when considering punch-through, in order to make Lp 0.3 μm or more, the injection angle θ needs to be 75 ° or less. That is, in the case of FIG. 16, Lch = 1.7 dp · cos θ, tan θ = 0.7 cot θ ′, Lp = Lch · cos θ′−dn · sin θ ′, and punch through occurs when Lp = 0.3 μm or less. . Considering this, in order to make the interval Lp 0.3 μm or more, the ion implantation angle θ needs to be 75 ° or less.

In summary, when (b) SiO ₂ (implantation range is 1.7 times that of SiC) is used as the implantation mask 11, the optimum value of the ion implantation angle is θ of 75 ° or less, and the margin is taken into consideration. Thus, it is preferable to set the injection angle to 65 ° to 75 ° with a large injection angle.

  In actual ion implantation, the ion implantation angle can be controlled simply by tilting the substrate in accordance with the orientation of the implantation mask using the orientation flat of the substrate. In FIG. 14, Al is implanted from two different angles on the left and right, but ion implantation may be performed at two or more different implantation angles on the left and right. In addition to tilting the substrate left and right, if the substrate is tilted and rotated during ion implantation, the same implantation as in FIG. 14 can be realized by a single implantation.

  Therefore, according to the third embodiment, selective impurity doping can be performed by the above-described method by a self-alignment process using the same mask. In particular, the channel length of the MOSFET can be easily controlled by the depth and angle of ion implantation, which is advantageous when miniaturizing the MOSFET compared to the case of using a different mask for conventional ion implantation. If a material having an ion implantation range longer than SiC is used as an implantation mask, a taper can be formed in the p base region 5, and the channel resistance Rch and JFET resistance Rj are traded off when the MOSFET is miniaturized. The relationship can be improved.

Embodiment 4 FIG.
FIG. 19 is a sectional view showing a semiconductor device (SiC vertical MOSFET) manufactured according to the fourth embodiment of the present invention. A source region 4 and a base region 5 are formed by ion implantation in a drift region 6 epitaxially grown on a substrate 7, and a gate oxide film 2, a gate electrode 1, a source electrode 3, and a drain electrode 8 are formed to produce a MOSFET. .

  FIG. 20 is a diagram for explaining a method of manufacturing a semiconductor device according to the fourth embodiment of the present invention, and is a diagram for explaining a method of forming source region 4 and base region 5 by ion implantation. As shown in FIG. 20, by using the tapered implantation mask 9 to perform ion implantation from the vertical direction and the oblique direction with respect to the substrate, as in the second and third embodiments described above, A region where only the base region 5 is implanted is formed. This part becomes the channel of the MOSFET. The channel length and the taper angle of the p base region 5 can be controlled by the depth and angle of ion implantation and the shape of the implantation mask (taper angle).

  Therefore, according to the fourth embodiment, selective impurity doping can be performed by the above-described method by a self-alignment process using the same mask. In particular, there are more parameters for controlling the channel length and the taper angle of the p base region 5 than in the second and third embodiments, the MOSFET can be easily miniaturized, and the trade-off between the channel resistance Rch and the JFET resistance Rj. The off relationship can be improved.

Embodiment 5 FIG.
FIG. 21 illustrates a method of manufacturing a semiconductor device according to the fifth embodiment of the present invention in which the source region 4 and the base region 5 of the semiconductor device (SiC vertical MOSFET) shown in FIG. 13 are formed by ion implantation. It is a figure for doing. As shown in FIG. 21, both the source region 4 and the base region 5 are formed by ion implantation from an oblique direction with respect to the substrate. When the implantation angle θ is smaller, the width of the region implanted under the mask 10 becomes larger. Therefore, if the ion implantation angle of the base region 5 is made smaller than that of the source region 4, only the base region 5 is implanted under the mask 10. However, it is formed. This part becomes the channel of the MOSFET. The channel length can be controlled by the ion implantation depth and implantation angle, as in the third embodiment.

  Therefore, according to the fifth embodiment, selective impurity doping can be performed by the above-described method by a self-alignment process using the same mask. In particular, the channel length of the MOSFET can be easily controlled by the depth and angle of ion implantation, which is advantageous when miniaturizing the MOSFET compared to the case of using a different mask for conventional ion implantation. In addition, if a material having a longer ion implantation range than SiC is used as the material for the same mask, the p base region 5 can be tapered, and the channel resistance Rch and the JFET resistance Rj can be reduced when the MOSFET is miniaturized. The trade-off relationship can be improved.

Embodiment 6 FIG.
FIG. 22 illustrates a method of manufacturing a semiconductor device according to the sixth embodiment of the present invention in which the source region 4 and the base region 5 of the semiconductor device (SiC vertical MOSFET) shown in FIG. 19 are formed by ion implantation. It is a figure for doing. As shown in FIG. 22, using the tapered implantation mask 9, both the source region 4 and the base region 5 are formed by ion implantation from an oblique direction with respect to the substrate. When the implantation angle θ is smaller, the width of the region implanted under the mask 9 becomes larger. Therefore, if the ion implantation angle of the base region 5 is made smaller than that of the source region 4, only the base region 5 is implanted under the mask 9. However, it is formed. This part becomes the channel of the MOSFET. In addition to the effect that the implantation mask is tapered, the channel length and the taper angle of the p base region 5 can be controlled by the depth and implantation angle of the ion implantation and the shape (taper angle) of the implantation mask.

  Therefore, according to the sixth embodiment, selective impurity doping can be performed by the above-described method by a self-alignment process using the same mask. In particular, there are more parameters for controlling the channel length and the taper angle of the p base region 5 than in the second and third embodiments, and the MOSFET can be easily miniaturized. Further, by providing the taper angle of the p base region 5, the trade-off relationship between the channel resistance Rch and the JFET resistance Rj can be improved.

  1 gate electrode, 2 gate oxide film, 3 source electrode, 4 source region, 5 base region, 6 drift region, 7 substrate, 8 drain electrode, 9, 10 implantation mask.

Claims (12)

On the surface of the epitaxially grown SiC drift region, an ion implantation mask having a taper angle of 30 ° to 60 ° and having the same ion implantation range as that of SiC is used. Forming a p base region having a first conductivity type in the SiC drift region by implanting first ions into the epitaxial layer of SiC;
By using the ion implantation mask and implanting second ions into the SiC drift region through the surface, at least the base region is normal to the surface within a range of 30 ° to 60 °. Forming a source region having a second conductivity type in the p base region so as to have a side surface forming an angle with respect to the vertical MOSFET using SiC. Implanting first ions along a tilt direction with respect to a normal to the surface;
A method of manufacturing a vertical MOSFET using SiC according to claim 1, comprising implanting second ions along a normal to the surface.   At each angle inclined relative to the normal to the surface such that both the p base region and the source region have sides that form an angle with respect to the normal to the surface within a range of 30 ° to 60 °. The method for manufacturing a vertical MOSFET using SiC according to claim 1, comprising implanting first and second ions.   2. The method of manufacturing a vertical MOSFET using SiC according to claim 1, comprising simultaneously implanting the first and second ions. A first ion is applied to the epitaxial layer of SiC through the surface using a SiO ₂ mask having an angle of taper of 20 ° to 45 ° on the surface of the epitaxially grown SiC drift region as an ion implantation mask. Forming a p-base region having a first conductivity type in the SiC drift region;
By using the ion implantation mask and implanting second ions into the SiC drift region through the surface, at least the base region is normal to the surface within a range of 30 ° to 60 °. Forming a source region having a second conductivity type in the p base region so as to have a side surface forming an angle with respect to the vertical MOSFET using SiC. Implanting first ions along a tilt direction with respect to a normal to the surface;
A method for manufacturing a vertical MOSFET using SiC according to claim 5, comprising implanting second ions along a normal to the surface.   At each angle inclined relative to the normal to the surface such that both the p base region and the source region have sides that form an angle with respect to the normal to the surface within a range of 30 ° to 60 °. The method of manufacturing a vertical MOSFET using SiC according to claim 5, comprising implanting first and second ions.   6. The method of manufacturing a vertical MOSFET using SiC according to claim 5, comprising simultaneously implanting the first and second ions. A mask made of the same material as that of SiC having a side surface substantially parallel to the normal to the surface of the SiC drift region on the surface of the epitaxially grown SiC drift region is used as the ion implantation mask. Then, by implanting a first ion into the SiC drift region through the surface in a direction that forms an angle of 70 ° or less on the surface, p having a first conductivity type in the SiC drift region is obtained. Forming a base region;
The p base region measured along the surface by implanting second ions into the SiC layer through the surface in a direction substantially parallel to the normal using the ion implantation mask. Forming a source region having a second conductivity type on the opposite side of the first conductivity type in the base region so that the channel length of the substrate is at least 0.3 microns. Manufacturing method of vertical MOSFET.   The method for manufacturing a vertical MOSFET using SiC according to claim 9, comprising simultaneously implanting the first ions and the second ions. Using an SiO ₂ mask as an ion implantation mask having a side surface substantially parallel to the normal to the surface of the SiC drift region on the surface of the epitaxially grown SiC drift region, an angle of 75 ° or less is formed on the surface. Forming a p base region having a first conductivity type in the SiC drift region by implanting first ions into the SiC drift region through the surface in the direction of formation;
Using the ion implantation mask, the p base region is compared with the source region by implanting second ions into the SiC drift region through the surface in a direction substantially parallel to the normal. Forming a source region having a second conductivity type on the opposite side of the first conductivity type in the p base region so as to have a thickness of at least 0.3 microns. Manufacturing method of vertical MOSFET.   The method for manufacturing a vertical MOSFET using SiC according to claim 11, comprising simultaneously implanting the first ions and the second ions.

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