TWI263247B - Method for manufacturing tantalum oxy nitride capacitor - Google Patents

Method for manufacturing tantalum oxy nitride capacitor Download PDF

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Publication number
TWI263247B
TWI263247B TW090130330A TW90130330A TWI263247B TW I263247 B TWI263247 B TW I263247B TW 090130330 A TW090130330 A TW 090130330A TW 90130330 A TW90130330 A TW 90130330A TW I263247 B TWI263247 B TW I263247B
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Taiwan
Prior art keywords
mps
gas
mixture
doping
nitrogen oxide
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TW090130330A
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Chinese (zh)
Inventor
Dong-Su Park
Kwang-Seok Jeon
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Hynix Semiconductor Inc
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B99/00—Subject matter not provided for in other groups of this subclass
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02172—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides
    • H01L21/02175—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides characterised by the metal
    • H01L21/02183—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides characterised by the metal the material containing tantalum, e.g. Ta2O5
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
    • H01L21/0226—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
    • H01L21/02263—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase
    • H01L21/02271—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02296—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer
    • H01L21/02318—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment
    • H01L21/02337—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment treatment by exposure to a gas or vapour
    • H01L21/0234—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment treatment by exposure to a gas or vapour treatment by exposure to a plasma
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02296—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer
    • H01L21/02318—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment
    • H01L21/02356—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment treatment to change the morphology of the insulating layer, e.g. transformation of an amorphous layer into a crystalline layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/314—Inorganic layers
    • H01L21/3143—Inorganic layers composed of alternated layers or of mixtures of nitrides and oxides or of oxinitrides, e.g. formation of oxinitride by oxidation of nitride layers
    • H01L21/3144—Inorganic layers composed of alternated layers or of mixtures of nitrides and oxides or of oxinitrides, e.g. formation of oxinitride by oxidation of nitride layers on silicon
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
    • H01L28/40—Capacitors
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T29/00—Metal working
    • Y10T29/43—Electric condenser making
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T29/00—Metal working
    • Y10T29/43—Electric condenser making
    • Y10T29/435—Solid dielectric type
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T29/00—Metal working
    • Y10T29/49—Method of mechanical manufacture
    • Y10T29/49002—Electrical device making
    • Y10T29/49117—Conductor or circuit manufacturing
    • Y10T29/49124—On flat or curved insulated base, e.g., printed circuit, etc.
    • Y10T29/49128—Assembling formed circuit to base

Abstract

The present invention relates to a method for manufacturing a capacitor using a tantalum oxy nitride (TaON) film in a process for a semiconductor device, and more particularly, to a method for manufacturing a capacitor which reduces a number of steps and thus increases yield by in-situ performing the step of executing P-doping after forming a MPS (metastable poly silicon) on a lower electrode and the step of forming a nitride film before forming a tantalum oxy nitride film, and prevents the concentration of phosphor contained in the lower electrode from being reduced by removing the phosphor on the surface of the lower electrode in a cleaning process of a conventional art performed between the above two steps, for thereby increasing the capacitance of the capacitor.

Description

1263247 九、發明說明： 【發明所屬之技術領域】 本發明係有關於半導體元件製造方法’係利用氮氣化 钽溥膜製帛’且特別有關於電容器之製造，以減少樂、牛 驟，從而以在MPS形成之後在下電極進繼雜以増力:： 效果，在氮氧化㈣膜形成之前1行形成氮化物薄膜了 且為防止磷（phosphor)隼中力πτ φ技：士 巾在下電極表面現象會因傳統的 >月洗步驟而降低，故在形成氮 风虱化物潯步驟及形成氮氧化 、旦濤膜步驟之間去除傳統的清^ ^ ^ ^ ^ ^ 電容值。 ^進而增加電容器的 【先前技術】 一般而言’半導體以電容器做為儲存電荷之用。半 =高度積體性，隨單元尺寸的減小，元件電容值的 每單=升^目前，_则以上之電容值需求超過30: 口此，隨著半導體元件的高度積 化#日如舌面 又積版化，電容器的微] Γ 不過’為滿足所需之電容值，對尺寸的— ’仍限制’因此也造成了電容器微型化之困難。 、 為了解決目前所遇到的㈣，電容1263247 IX. Description of the Invention: [Technical Field] The present invention relates to a method for manufacturing a semiconductor device, which is based on the manufacture of a ruthenium nitride film, and particularly relates to the manufacture of a capacitor to reduce the amount of music and cattle. After the formation of MPS, the next electrode is mixed with a force:: effect, a nitride film is formed in one row before the formation of the nitrogen oxide (tetra) film, and in order to prevent the phosphorus 隼 medium force πτ φ technique: the surface of the lower electrode will be Due to the conventional > month wash step, the conventional capacitance of the ^ ^ ^ ^ ^ ^ is removed between the steps of forming the nitrogen wind and the formation of nitrogen oxide and the film. ^ Further increasing the number of capacitors [Prior Art] Generally, a semiconductor uses a capacitor as a storage charge. Half = high integration, as the size of the unit decreases, each element of the component capacitance value = liter ^ current, _ above the capacitance value demand exceeds 30: mouth, with the height of the semiconductor component accumulation #日如舌The surface is further integrated, the capacitor's micro] Γ but 'to meet the required capacitance value, the size of the 'still limited' therefore also caused the capacitor miniaturization difficulties. In order to solve the current (four), capacitor

i亲钊担古+ A 又文夕種結構J 違到拨同電容值的目的。本方法為了拗 值’包含之方式有使用氮氧化组或BST等/人W之電； 料做為介電層以及增加電容器表面積之方：:丨電常數之4 在上述方法中，在此簡述傳統製i relatives bear the ancient + A and the eve of the structure J violate the purpose of dialing the same capacitance value. In order to depreciate the method, the method of using the oxynitride group or the BST or the like is used; the material is used as the dielectric layer and the surface area of the capacitor is increased: the 丨 electric constant 4 is in the above method, Traditional system

〜用有向介電常I 5142-4527-PF3 6 1263247 J氮氧化1旦為介電層之電容哭制 , 电A為製程： 百先，利用未摻雜之石 雜之石夕之其中之1可長t、低推雜石夕、已換雜混合未摻 形成下電極100 (此為(gr〇Wth)成為MPS之材料以 乾钱刻上述所形成 11極$成步驟），#做濕餘刻或 、卜電極層，定差、 之氣體形成MPS (此Α # 、電極區域；用含矽 々开》成MPS夕半®、. 氣體做摻雜（此為摻 乂 ”’ ，用含磷之混合 ^ 肝s之步驟）。 接下來，為了清除乂 物镜胺斗… ’、土述步驟中在表面所產吐沾-/ 物4艇或氦化物薄膜 厅產生的乳化 中之-做清洗步驟，τ=^、臟、H〜及心其 102，因此形成5〜20 A之ς•與乳反應形成氮化物薄膜 化鈕前製程之步驟）。 在下包極表面（此為氮氧 在氮氧化鈕前製程步 氣在S鬥主 '、後，釗用含有钽成分之化鐵# 4在日日0表面引起化學 之化子游 為开3 ώ用而儿積一層非晶的薄 為形成虱氧化Μ薄膜之步^ 。 ’1ϋ4(此 最後’利用電漿法硝化 表面，強化紝槿 ^ 处之已形成之薄膜 步驟）。之德，掩田人 為亂乳化鈕後製程 豎金屬層做為上電極1 06，則此f 1 π 电谷益凡成（此為形成上電極步驟）。 在傳統電容器製程中，在么 西以 見乳化組刖製程步驟，兔7 要^加Si -Ν的鍵社作用，e卢 為了 導致温度的二在電漿的激發狀態之下，因而 (LPC脚： 乳化鈕薄膜在化學辅助氣相沉積 ”在晶圓上沉積不均勻的現象而難以達到掣程 而求的條件。特別是氮氧化組的沉積溫度需…咐， 5142~4527-pf3 7 1263247 /斤以 >里度的增加勢必 ψ L ^後束的製程產生嚴重的問題。 另外’在MPS摻雜| _也尸 牛_ . Λ /驟一氮化物薄膜步驟之間的清洗 步驟’會減低嶙隼中太τ α ^ 〜在下電極表面現象而導致電容器之電 各值降低。 【發明内容】 本知明主要在於提供-氮氧化鈕電容器製造方法，以 、、二Α步驟:在MPS形成之後在下電極進行構摻雜以增 ' ’、 在氮氧化鈕薄膜形成之前在同一腔體内先行形 物薄膜’防止碟—。r)集中在下電極表面現 b □在φ成氮化物薄膜步驟及形成氮氧化叙薄膜步驟之 閟去除傳統的清洗步驟而降低’進而增加電容器的電容值。 為了達到以上所述之功效，本發明提供—具體化的氣 乳化鈕電容器製造步驟：使用摻雜之矽、低摻雜矽、已摻 雜混合未摻雜之石夕之其中之一在半導體基板形成下電極； 在濕钱刻或乾钱刻下電極定義其形狀後，用含^來㈣ 分之氣體形成MPS;用含磷之混合氣體做摻雜；在摻雜㈣ 之同—腔體沉積氮化物薄膜為氮氧化组之前製程步驟，利 用含有组之化學蒸氣在氮化薄膜上沉積氮氧化组薄膜；在 上述之沉積表面利用硝化或氮硝化表面做氮氧化鈕之後製 程；最後再上述之全部表面利用堆積一金屬層方式形成上 電極。 在傳統方法中，MPS有一長膜用腔體、Mps摻雜用腔 肢X及氮氧化组長旗用腔體，而利用前述之本發明步驟， 5142-4 527-PF3 8 1263247 從MPS形成步驟到氮氧化组薄膜沉積步驟皆可在同一腔體 π統中進仃’其中包括下列四個步驟：Mps形成步驟、 ”隹v ’氮化物》儿積步驟以及氮氧化鈕薄膜沉積步驟。 …根據本發明之氮氧化钽電容器製造方法中，氮氧化鈒 薄膜"L積v騍岫的Mps摻雜步驟及氮化物沉積步驟皆在同 一腔體中進行’則不需要去除氧化層的清洗步驟，因而防 止電谷為之電容值降低現象。 另外，依據本發明之氮氧化钽製造方法，因為氮氧化 组沉積步驟前的MPS摻雜步驟及氮化物沉積步驟皆在同— 2體中進行，所以不會發生類似因為電槳激發狀態所導致 盟度'a加而引起氮氧化叙薄膜沉積不均勻的問題。 依據本發明之氮氧化组製造方法，下電極之银刻可利 用合有HF之氣體特別是HF和Μ混合氣體、hf和㈣混 合氣體、BOE、HF和CH3COOH和混合氣體。 此 依據本發明之氮氧化鈕製造方法，在MPS形成步驟 中3有石夕之氣體，其成分為Si{h、nCh其中之 其壓力在5· 0E’以下’溫度低於7。。。。（以晶圓溫 度為準）。 β ，據本發明之氮氧化鈕製造方法，其中Mps摻雜 屋力耗圍在l.0E_03〜500t〇rr，溫度在5〇〇~i〇〇『c。含磷 之混合氣體成分為包含有混合Ρίί3之氣體。其中混合J : 體成分為包含抓與Ν2之混合物、版與Η2之混合物、= 與S1扒之混合物、或ΡΗ3與Ar之混合物。 依據本發明之氮氧化组製造方法，氮化物沉積步驟步 5142-4527_PF3 9 1263247 驟中，使用NIL·氣體且壓力範圍在〇1〜2〇〇t〇rr ,溫度在 6 00〜850°C之間。 此外，在氮氧化鈕薄膜沉積步驟中，一種鈕的混合物， 譬如鈕的乙醇化物（如乙醇鈕），被置於一蒸餾器或蒸發管 中，透過一流s控制器，譬如氣體流量控制器（mfc， flow Controller),用以決定氣體流量。其蒸發溫度在 ΙΰΟ〜2 00 C之間，得到含有鈕成分之化學蒸氣。換言之，上 述方法之化子条氣及反應氣體含有過量的&及，3氣體， 其中〇2及Nh氣體流量皆被控制在1〇〜1〇〇〇sccm範圍内， 在溫度於300〜60(TC範圍内之LpcVD腔體内做表面反應以 付到非結晶型的氮氧化组薄膜。 同樣地’在氮氧化组後製程中，利肖NH”化和H2混 〇乱妝10攻eh氣體其中之一硝化，使用電漿法，溫度 在2。0’0。(：範圍内；或利用-或〇2氣體其中之一氮確 化由於上述所达之氮氧化纽後製程，微小破裂及位於交 界面的針孔等結構缺陷可以被強化，以及均質性也會增 進雖，、、、：口為上逑方法增進了氮氧化叙之特性，故增加 了一個步驟，若在電性上需要在下一步驟做高溫處理，則 此步驟可以省略。牲Η丨丨ώΑ 10 » 特別的疋，在氮氧化鈕薄膜沉積之後， 如果需要使用快速熱處理（RTp，rapid I随i wss) 或電爐，可經由在龍q、W W、日/v γ Ν2和Η2 >吧合氧體、ν2〇或〇2其中之 一種氣體下，經過3 〇糾、$]| 1 9 η八技， ^ 杉到120分鐘的硝化或氧化，溫度在 650〜950 C範圍内，以達到結晶之作用。 此外在上電極形成步驟中，上電極乃是由沉積金屬 5142-4527-PF3 10 1263247 或堆疊金屬結構而來，其、 WSi、RU、Ru0。、J 、刀為多晶石夕、TiN、TaN、W、WN、 1 、或 Pt 。 L貫施方式】 實施例： 茲配合圖式說明本發 ψ λ m ^ ^ X月之較佳實施例。 弟1圖到第5圖Λ备— 意圖。 ”、、虱化钽電容器製造方法之製程示 根據本發明之製程， 形成於半導體基板工。表面。？舉於第1圖’下電極_ MPS之材料包括摻雜：：、。此:夺’下電極成分是由可形成 之矽之其中之一所形 、低摻雜矽、已摻雜混合未摻雜 成非晶之矽笼 、此日守下電極在溫度低於560°C形 成弃日日之矽涛胺，利用含矽 ^ SiH2C1, 〇 , 虱體，其成分為 SiH4、Si2H6、 a mh2ci2。進行MPS摻雜 之氣體，如ΡΗ3· Nsn 混合氣體可為混合PH3~ Use the directional dielectric I 5142-4527-PF3 6 1263247 J to oxidize 1 denier as the dielectric layer of the capacitor to cry, the electric A is the process: Bai Xian, using the undoped stone miscellaneous stone 1 can be long t, low push rock, evening mixed, undoped to form lower electrode 100 (this is (gr〇Wth) to become MPS material to dry the above formed 11 poles into a step), #做湿The residual or the electrode layer, the differential, and the gas form MPS (this Α # , electrode area; use 矽々 矽々 》 成 成 成 MP MP MP MP MP MP MP MP MP MP MP MP MP MP MP MP MP MP MP MP 气体 气体 气体 气体 气体 气体Mixing of Phosphorus ^ Step of Liver s). Next, in order to remove the sputum of the objective lens... ', in the anaerobic process produced in the surface of the sputum-/4 boat or bismuth film hall Step, τ = ^, dirty, H ~ and heart 102, thus forming a 5 ~ 20 A ς 与 与 与 与 与 与 与 与 与 与 与 与 与 与 与 与 与 与 与 与 与 与 与 。 。 。 。 。 。 。 。 。 。 。 。 。 。 The oxidation process before the oxidation process step in the S bucket main ', after, using the strontium-containing composition of the iron # 4 on the surface of the day 0 caused by chemical chemistry swims open 3 而The thin layer of amorphous layer is the step of forming the yttrium oxide yttrium oxide film. '1ϋ4 (This is the last step of nitrating the surface by plasma to strengthen the formed film step at the 纴槿^). After the vertical metal layer of the post process is used as the upper electrode 106, then this f 1 π electric valley Yifancheng (this is the step of forming the upper electrode). In the traditional capacitor process, in the case of the emulsification group, the rabbit 7 is required Adding Si-Ν's bond function, e Lu in order to cause the temperature of the two under the excited state of the plasma, thus (LPC foot: emulsified button film in chemically assisted vapor deposition) deposited unevenly on the wafer It is difficult to meet the conditions for the process. In particular, the deposition temperature of the NOx group needs to be... 咐, 5142~4527-pf3 7 1263247 / kg, and the increase of the degree is likely to cause serious problems in the process of the L ^ after the bundle. In the MPS doping | _ also corpse _ _ / 一 / nitride film step between the cleaning step 'will reduce the 嶙隼 太 τ α ^ ~ 在 在 在 在 在 在 在 在 在 在 。 。 。 。 。 。 。 。 。 。 。 Content] This knowledge mainly lies in The method for manufacturing a nitrogen-oxygen button capacitor, the second step: after the formation of the MPS, the doping of the lower electrode is performed to increase the '', and the film is formed in the same cavity before the formation of the nitrogen oxide button film. - r) concentrated on the surface of the lower electrode, □ after the step of φ into a nitride film and after the step of forming a nitrogen oxide film, the conventional cleaning step is removed to reduce 'and thereby increase the capacitance value of the capacitor. In order to achieve the above-mentioned effects, The present invention provides a specific gas embedding button capacitor manufacturing step: using a doped ytterbium, a low-doped yttrium, a doped mixed undoped shixi one of the semiconductor substrates to form a lower electrode; Or after the electrode is defined by the shape of the electrode, the MPS is formed by using a gas containing (4); the doping with a mixed gas containing phosphorus; before the doping (four)-the cavity is deposited with the nitride film as the nitrogen oxidation group a step of depositing a nitrogen oxide film on the nitride film by using a chemical vapor containing the group; and performing a process on the deposition surface by using a nitrification or nitrogen nitration surface as a nitrogen oxide button; All of the above surfaces are formed by stacking a metal layer to form an upper electrode. In the conventional method, the MPS has a cavity for a long film, a cavity for the Mps doping X, and a cavity for the long flag of the oxynitride group, and the steps of the present invention are used, 5142-4 527-PF3 8 1263247 from the MPS formation step The thin film deposition step to the oxynitride group can be carried out in the same cavity, including the following four steps: an Mps formation step, a "隹v' nitride" step, and a nitrogen oxide button film deposition step. In the method for manufacturing a ytterbium oxynitride capacitor of the present invention, the Ms doping step and the nitride deposition step of the yttrium oxynitride film are performed in the same cavity, so that the cleaning step of removing the oxide layer is not required. Therefore, the electric valley is prevented from being reduced in capacitance value. In addition, according to the method for producing niobium oxynitride according to the present invention, since the MPS doping step and the nitride deposition step before the nitrogen oxidation group deposition step are performed in the same body, There is no problem that the deposition of the nitrogen oxide film is uneven due to the aggregation of the electric blade propagating state. According to the oxynitride manufacturing method of the present invention, the silver etching of the lower electrode can be utilized. The gas containing HF is especially a mixed gas of HF and helium, a mixed gas of hf and (iv), BOE, HF and CH3COOH, and a mixed gas. According to the method for producing a nitrogen oxide button of the present invention, in the MPS forming step, there is a gas of Shi Xi. The composition is Si{h, nCh, wherein the pressure is below 5.00E', and the temperature is lower than 7 (according to the wafer temperature). β, according to the method for producing a nitrogen oxide button of the present invention, wherein The Mps doping house power consumption is around l.0E_03~500t〇rr, and the temperature is 5〇〇~i〇〇“c. The phosphorus-containing mixed gas component is a gas containing mixed Ρίί3. Among them, the mixed J: body composition is included. Mixing a mixture with Ν2, a mixture of 版 and Η2, a mixture with S1, or a mixture of ΡΗ3 and Ar. According to the oxynitride manufacturing method of the present invention, the nitride deposition step is 5142-4527_PF3 9 1263247 NIL · gas and pressure range 〇1~2〇〇t〇rr, temperature between 6 00~850 ° C. In addition, in the NOx thin film deposition step, a mixture of buttons, such as the ethanol of the button ( Such as the ethanol button), placed in a distiller or evaporation tube Through a first-class s controller, such as a gas flow controller (mfc, flow controller), to determine the gas flow rate, the evaporation temperature is between ΙΰΟ~2 00 C, and the chemical vapor containing the button component is obtained. In other words, the above method The gas and the reaction gas contain an excess of & 3 gas, wherein the gas flow rates of 〇2 and Nh are controlled within a range of 1 〇1 to 1 〇〇〇sccm, and the temperature is in the range of 300 to 60 (TC). A surface reaction is carried out in the LpcVD chamber to pay an amorphous type of oxynitride film. Similarly, in the post-nitrogen oxidation process, the Leishu NH and H2 are one of the 10 eh gases, and the plasma is used at a temperature of 2.0°. The use of one of the - or 〇 2 gases to determine the nitrogen oxides due to the above-mentioned process, the micro-rupture and pinholes at the interface can be strengthened, and the homogeneity can be improved, though, The mouth-up method enhances the characteristics of nitrogen oxides, so a step is added. If it is necessary to do high-temperature treatment in the next step, the step can be omitted. Sausage 10 » Special flaws, in After the deposition of the NOx film, if you need to use rapid thermal processing (RTp, rapid I with i wss) or electric furnace, you can pass the oxygen, ν2 〇 or 〇 in the dragon q, WW, day / v γ Ν 2 and Η 2 > 2 Under one of the gases, after 3 〇 、, $]| 1 9 η 八 , ^ 杉 120 120 120 120 120 120 120 120 120 120 120 120 120 120 120 120 120 120 120 120 120 120 120 120 120 120 120 120 120 120 120 120 120 120 120 120 120 120 120 120 In the formation step, the upper electrode is deposited by the metal 5142-4527-PF3 10 1263247 or stacked metal structure, which, WSi, RU, Ru0, J, knife is polycrystalline, Xi, TiN, TaN, W, WN, 1, or Pt. L mode) Example: The drawings illustrate a preferred embodiment of the present invention, λ m ^ ^ X. The first embodiment of the present invention is shown in Fig. 5. The process of manufacturing the tantalum capacitor is shown in accordance with the process of the present invention. The surface of the semiconductor substrate is shown in Fig. 1. The material of the lower electrode _ MPS includes doping::, this: the lower electrode component is formed by one of the formed ruthenium, low doping 矽, which has been doped with a mixture of undoped amorphous, and the lower electrode at this temperature is formed at a temperature lower than 560 ° C to form a discarded day, using 矽 ^ SiH2C1, 〇, 虱, its composition is SiH4, Si2H6, a mh2ci2. The gas doped with MPS, such as ΡΗ3·Nsn mixed gas, can be mixed PH3

SlH4之、、η人铷Du 化5物、PH3與H2之混合物、ph3與 之此合物、ρΐί3與 I#产吾及颅士 △ 此a物其中之一。此步驟之氣SlH4, η human 铷 Du 5, PH3 and H2 mixture, ph3 and this compound, ρΐί3 and I# 产吾和脑士 △ one of this a. The temper of this step

成長技術）。 、擇性夕晶矽成長技術（MPS 接下來，依上述方法 -^ ^ ^ ^ ^ ，成之下電極，利用含有HF之 -口亂體如HF與h2〇之 HF ^ ΓΗ Γπηπ ^ 初 HF 與 H2〇2 之混合物、B0E、 HF與CH3C00H與N〇2之混合 ^ ^ 做乾餘刻或渴ϋ刻，並置 於-定壓保持在… 弋刻I置 下恭榀夕v加 7月工體之内。當MPS形成於Growth technology). Selective crystallization technology (MPS Next, according to the above method - ^ ^ ^ ^ ^, into the lower electrode, using HF - squirrel like HF and h2 〇 HF ^ ΓΗ Γ πηπ ^ initial HF and Mixture of H2〇2, Mix of B0E, HF and CH3C00H and N〇2 ^ ^ Do dry or thirsty engraving, and place in - constant pressure to keep in... Engrave I set down Gongxi Xi v plus July work Within. When MPS is formed

Sl二二利用含碎之氣體，其成分為SiH,、Sl2H6、 2 2-之一，其壓力在5.〇Ε〜〇4ΐ(^以下(Mps形成 5142-4527-PF3 11 1263247 步驟）。但由於MPS之开^ #半跡此丄 、 形成步驟非本發明之特徵，故在圖 式中未標示出。 於上述製程之後’以混合PH3氣體成分為包含服與 之混合物、PH3與^之混合物、服與抓之混合物、M3 與Ar之混合物其中之— 做，备雜，其壓力範圍於 1.0E魯漏町之間，溫度範圍在嶋。c之間（ 摻雜步驟）。第2圖為下電極上部Mps做磷摻雜之示意圖。 接下來，在同-腔體（in —Sltu)，以随3氣體形成氮 化物薄膜102，壓力範圚名〇 1 9〇n + 一视国在ϋ·：1〜200t〇rr且溫度範圍在 6 00〜8 5(TC。關3與下電極之ςι·埒處 ^ ^ 电位之h反應，而在卜電極表面上形 成5〜20 A厚的Sl-N鍵結’如第3圖所示（氮氧化组前製 程步驟）。 在氮氧化鈕前製程步驟之後，以一種鈕的混合物，譬 如鈕的乙醇化物（如乙醇鈕），被置於一蒸餾器或蒸發管 中，透過一流量控制器，譬如氣體流量控制器（MFC，腿“ flow controller)，用以決定氣體流量。其蒸發溫度在 150〜20 0°C之間，得到含有鈕成分之化學蒸氣。換言之，上 述方法之化學蒸氣及反應氣體含有過量的〇2及NH3氣體， 其中〇2及關3氣體流量皆被控制在i〇〜i〇〇〇Sccin範圍内， 在溫度於300〜60(Tc範圍内之LPCVD腔體内做表面反應以 得到非結晶型的氮氧化鉅薄膜丨〇 4。如第4圖所示。 接下來，在氮氧化鈕後製程中，利用NH3、N2和H2混 a氣體、N2 0或〇2氣體其中之一硝，化，.使用電漿法，溫度 在200〜600°C範圍内；或利用10或〇2氣體其中之一氮石肖 5142-4527-PF3 12 1263247 ;上述所述之氮氧化组後製程’微小破裂及位於交 :。咕針孔等結構缺陷可以被強化，以及均質性也會增 +別的疋’在氮氧化钽薄膜沉積之後 快速熱處理⑽，邮dth⑽lp_ss)或 …_3，和H2混合氣體、_或〇2其中 經過3〇秒至M20分鐘的硝化或氧化，、.田产才㈡⑽广 乂儿化服度在6b0〜95(TC範 ’以達到結晶之作用。（氮氧化组後製程步驟）。 在經氮氧化叙後製程步驟之後，如第5圖所示，形成 ^極咖，即可以依本發明完成氮氧化组電容器。依上 二上電極乃是由沉積單一金屬或堆疊數種金屬結構而 /、、成分為多晶矽、TlN、TaN ' [ WN、WSi、Ru、Ru〇2、 Ir、或pt (上電極形成步驟）。 二:所述’本發明在於提供一氮氧化"容器製造方 二门mm於自MPS㈣步驟到氮氧化组前製程步驟均 在同一腔體（ln-Situ)，可以防 冼表面而造成磷 在下电極表面集申減低。因此，本 魃I以月之電各為的電容值 將g杧加，避免因清洗造成Mps 工Μ & 了于間的破壞，而MPS粒 結將更穩固，因而減低元件的位元錯誤。 开，=外’在本發明中’由於自MPS接雜步驟到氮氧化组 形成乂驟均在同一腔體（ln_sltu)以及同—系統中，所以 设備投貧及製程時間將減低，將可增加製程之生產力。 2本發明之較佳實例以揭露如上，然其並非用以限 =内月’:壬何熟習此項技藝者’在不脫離本發明之精神 和辄圍内，仍可做些許的更動和潤飾，因此本發明之保護 5142-4527-PF3 13 1263247 乾圍當視後附之申請專利範圍所界定者為準 【圖式簡單說明】 ，為使本發明之上述目的、特徵和優點能更顯而易懂， »'文，列舉較佳實施例並配合所附圖式做詳細說明。 土弟1圖到第5圖為氮氧化M電容器製造方法之製程示 思、圖，其中。 第1圖為形成下電極以及名 ^ ^ ^以及在下電極上方形成MPS (圖 面未標示）之示意圖。 々第2圖為第i圖之所述材料做㈣摻雜示意圖。 示意^。3圖為沉積氮化物薄媒做為氮氧化叙沉積之前步驟 上部 _第4圖為沉積氮氧化組薄膜在第3圖所述之材料 之示意圖。 上電極，氮氧 化 第5圖為在第4圖所述材料上部形成 起電容器完成示意圖。 【主要元件符號說明】 1 0 0〜下電極； 1 0 2〜氮化物薄膜； 1 〇 4〜氮氧化叙薄膜； 106〜上電極。 5142-4527-PF3 14Sl 22 uses a gas containing a broken gas, and its composition is one of SiH, Sl2H6, and 2 2-, and its pressure is 5.〇Ε~〇4ΐ(^ below (Mps forms 5142-4527-PF3 11 1263247 step). Since the opening of the MPS is not a feature of the present invention, it is not shown in the drawings. After the above process, the mixture of the PH3 gas component is contained, and the mixture of PH3 and ^ is mixed. Mixture of the service and the grip, a mixture of M3 and Ar, which is prepared and prepared, and the pressure range is between 1.0E and the temperature range is between 嶋 and c (doping step). The upper part of the lower electrode is made of phosphorus doping. Next, in the same-cavity (in-Sltu), the nitride film 102 is formed with 3 gases, and the pressure is in the range of 〇1 9〇n + ·: 1~200t〇rr and the temperature range is 6 00~8 5 (TC. Off 3 reacts with the lower electrode ς 埒 ^ ^ ^ potential h, and forms 5~20 A thick Sl on the surface of the electrode -N bond 'as shown in Figure 3 (the pre-oxidation step of the nitriding group). After the step of the nitrogen oxide button, a mixture of buttons, 譬The button's ethanolate (such as the ethanol button) is placed in a distiller or evaporating tube and passed through a flow controller, such as a gas flow controller (MFC, leg "flow controller", to determine the gas flow. The chemical vapor containing the button component is obtained between 150 and 20 ° C. In other words, the chemical vapor and the reaction gas of the above method contain an excess of ruthenium 2 and NH 3 gas, wherein the 〇 2 and off 3 gas flows are controlled at i. In the range of 〇~i〇〇〇Sccin, a surface reaction is carried out in an LPCVD chamber at a temperature of 300 to 60 (Tc range) to obtain an amorphous NOx thin film 丨〇4. As shown in Fig. 4. Down, in the post-nitrogen oxidation button process, using NH3, N2 and H2 mixed a gas, N2 0 or 〇2 gas, one of the nitrates, using plasma method, the temperature is in the range of 200~600 ° C; or Using 10 or 2 gas, one of the nitrogen diatoms 5142-4527-PF3 12 1263247; the above-mentioned nitrogen oxidation group process is 'micro-rupture and located at the intersection: 结构 pinholes and other structural defects can be strengthened, and homogenization Will also increase + other 疋' in the ruthenium oxynitride film deposition After rapid heat treatment (10), mail dth (10) lp_ss) or ... _3, and H2 mixed gas, _ or 〇 2 which after 3 sec to M20 minutes of nitrification or oxidation, , Tian Ma Cai (2) (10) wide 乂 children's clothing in 6b0~95 ( TC Fan's to achieve the role of crystallization. (Nitrogen oxidation group post-process step). After the nitrogen oxidation process step, as shown in Figure 5, the formation of the electrode, can be completed according to the invention . The upper electrode is formed by depositing a single metal or stacking several metal structures, and the composition is polycrystalline germanium, TlN, TaN ' [WN, WSi, Ru, Ru〇2, Ir, or pt (upper electrode formation step) . Two: the 'the present invention is to provide a nitrogen oxidation" container manufacturing side two mm from the MPS (four) step to the nitrogen oxidation group before the process steps are in the same cavity (ln-Situ), can prevent the surface of the surface caused by phosphorus under The surface of the electrode is reduced. Therefore, in this case, the capacitance value of each month is increased by g, so as to avoid the destruction of the Mps process and the MPS, and the MPS grain will be more stable, thereby reducing the bit error of the component. Open, = outside 'in the present invention' because the steps from the MPS mixing step to the formation of the nitrogen oxidation group are all in the same cavity (ln_sltu) and the same system, so the equipment investment and process time will be reduced, which will increase Process productivity. 2 The preferred embodiment of the present invention is disclosed above, but it is not intended to be limited to the inner moon': any skillful person skilled in the art can still make some changes and retouching without departing from the spirit and scope of the present invention. Therefore, the protection of the present invention is 5142-4527-PF3 13 1263247, and the above-mentioned objects, features and advantages of the present invention are more apparent in the light of the scope of the appended claims. It is easy to understand, ''text', the preferred embodiment is listed and explained in detail with the accompanying drawings. Tudi 1 to 5 are process diagrams and diagrams of the manufacturing method of nitrogen oxide M capacitors. Figure 1 is a schematic diagram showing the formation of the lower electrode and the name ^ ^ ^ and the formation of MPS (not shown) above the lower electrode. Figure 2 is a schematic diagram of (4) doping of the material described in Figure i. Indicates ^. Figure 3 shows the deposition of nitride thin medium as a step before nitrogen oxide deposition. The upper part _ 4 is a schematic diagram of the material of the deposited nitrogen oxide group film in Fig. 3. Upper electrode, oxynitride Fig. 5 is a schematic view showing the completion of forming a capacitor in the upper portion of the material described in Fig. 4. [Main component symbol description] 1 0 0~lower electrode; 1 0 2~nitride film; 1 〇 4~nitrogen oxide film; 106~upper electrode. 5142-4527-PF3 14

Claims (1)

修正日期：95.4·ι：ι 號申請專利範圍修正本 十、申請專利範圍： a) 利用摻雜之碎、低摻㈣、已摻雜/未換雜之了 之-者：材料來形成一下電極在半導體基板表面· b) 前述之下電極經濕钱刻或乾姓刻後，利 氣體形成MPS(MPS Metastable p〇iy s⑴⑺…之 c) 利用含磷之混合氣體做Mps之摻雜； d) 沉積氮化物薄膜，在與Mps摻雜用之同一腔體 中’作為氮氧化鈕之前製程步驟； e) 利用包含有鈕之化學蒸氣以化學氣相沉積方式在 氮化物薄膜上沉積氮氧化叙薄膜； f) 在沉積步驟之後，利用硝化或氮硝化處理薄膜表 面，做氮氧化鈕後製程；以及 g)利用堆疊一層金屬在所有材料上形成一上電極； 且上述之MPS形成步驟、mps摻雜步驟 '氮化物沉積 步驟以及氮氧化钽沉積步驟均在同一腔體。 2 ·如申請專利範圍第1項所述之方法，其中在濕蝕 刻或乾餘刻下電極時，是使用包含有HF之氣體。 3 ·如申請專利範圍第2項所述之方法，其中該包含 有HF之氣體，包括肝與to之混合物、HF與H2〇2之混 合物、BOE、或HF與CKhCOOH與N〇2之混合物。 4 ·如申請專利範圍第1項所述之方法，其中使用在 MPS形成步驟含矽之氣體，包括siH4、Si2H6、或SiLCl2。 5·如申請專利範圍第1項所述之方法，其中MPS摻 5142-4527-PF3 15 1263247 雜步驟在壓力範圍於1. 0x10 —s〜5 0 0 torr之間，以及溫度 範圍在5 0 0〜1 〇 〇 〇 t：之間。 6 ·如申請專利範圍第丨項所述之方法，其中該含磷 之混合氣體包括一含有Pfj3之氣體。 L如申請專利範圍第6項所述之方法，其中該含有 PL之氣體包括pi與I之混合物、pH3與H2之混合物、 PL與SiL之混合物、或抑3與之混合物。 8. 如申請專利範圍第丨項所述之方法，其中氮化物 溥膜之沉積步驟使用氣體。 9. 如申請專利範圍第8項所述之方法，其中氮化物 薄膜之沉積步驟，壓力範圍在O.HOhOH之間，以及 溫度範圍在6 0 0〜8 5 0 °C之間。 1〇·如申請專利範圍第1項所述之方法，其中該包含 有叙之化學蒸氣包括蒸發之乙醇組。 11 ·如申請專利範圍第丨項所述之方法，其中氮氧化 钽後製程乃是利用NH3 c或N2與H2混合）氣體硝化表面 或利用10 (或& )氣體氮硝化表面。 12. 如申請專利範圍第丨項所述之方法，其中氮氧化 鈕後製程利用電漿其溫度範圍在於2 〇 〇〜6 〇 〇它之間。 13. 如申請專利範圍第1項所述之方法，其中該上電 極包括多晶矽、TiN、TaN、W、WN、WSi、Ru、Ru〇” 卜、 或Pt之單層結構，或上述單層結構組合之堆疊結構。 5142-4527-PF3 1263247 七、指定代表圖： (一） 本案指定代表圖為：第（5 )圖。 (二） 本代表圖之元件符號簡單說明： 1 0 0〜下電極； 102〜氮化物； 104〜氮氧化钽； 1 0 6〜上電極。 八、本案若有化學式時，請揭示最能顯示發明特徵的化學式 〇 4 5142-4527-PF3 5Amendment date: 95.4·ι:ι No. Patent application scope revision Ten, the scope of patent application: a) Using doped shreds, low doping (four), doped / not replaced - the material to form the lower electrode On the surface of the semiconductor substrate, b) after the electrode is wet or engraved, the gas forms MPS (MPS Metastable p〇iy s(1)(7)...c). The phosphorus-containing mixed gas is used for doping Mps; d) Depositing a nitride film, before the process as a nitrogen oxide button in the same cavity as Mps doping; e) depositing a nitrogen oxide film on the nitride film by chemical vapor deposition using a chemical vapor containing a button f) after the deposition step, the surface of the film is treated by nitrification or nitrogen nitration to perform a nitrogen oxide button post-process; and g) an upper electrode is formed on all materials by stacking a layer of metal; and the above MPS formation step, mps doping The step 'nitride deposition step and the bismuth oxynitride deposition step are all in the same cavity. 2. The method of claim 1, wherein the gas containing HF is used in the case of wet etching or dry etching of the electrode. 3. The method of claim 2, wherein the gas comprising HF comprises a mixture of liver and to, a mixture of HF and H2〇2, BOE, or a mixture of HF and CKhCOOH and N〇2. 4. The method of claim 1, wherein the gas containing ruthenium in the MPS formation step is used, including siH4, Si2H6, or SiLCl2. 5. The method of claim 1, wherein the MPS doping 5142-4527-PF3 15 1263247 is in a pressure range between 1. 0x10 - s~5 0 0 torr, and the temperature range is 5 0 0 ~1 〇〇〇t: between. 6. The method of claim 2, wherein the phosphorus-containing mixed gas comprises a gas containing Pfj3. L. The method of claim 6, wherein the PL-containing gas comprises a mixture of pi and I, a mixture of pH 3 and H2, a mixture of PL and SiL, or a mixture thereof. 8. The method of claim 2, wherein the depositing step of the nitride film uses a gas. 9. The method of claim 8, wherein the nitride film is deposited in a pressure range between O.HOhOH and a temperature in the range of 60 to 850 °C. The method of claim 1, wherein the chemical vapor comprising the vaporized ethanol group is included. 11 • The method of claim 2, wherein the post-nitrogen oxide process is a nitrification surface using NH3 c or N2 and H2 mixed gas or a nitrification surface using 10 (or &) gas nitrogen. 12. The method of claim 2, wherein the post-nitrogen oxide process utilizes a plasma having a temperature in the range of 2 〇 〇 6 6 〇 〇. 13. The method of claim 1, wherein the upper electrode comprises a single layer structure of polycrystalline germanium, TiN, TaN, W, WN, WSi, Ru, Ru, or Pt, or a single layer structure as described above Stacked structure of combination. 5142-4527-PF3 1263247 7. Designation of representative figure: (1) The representative figure of this case is: (5). (2) The symbol of the symbol of this representative figure is simple: 1 0 0~ lower electrode 102~ nitride; 104~ bismuth oxynitride; 1 0 6~ upper electrode. 8. If there is a chemical formula in this case, please reveal the chemical formula 最4 5142-4527-PF3 5 which can best show the characteristics of the invention.
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