1262482 玖、發明說明： (一） 發明所屬之技術領域 本發明係關於一種碼調變方法及裝置、解調變方法及 裝置、以及資訊記錄媒體，係用以記錄或重製數位資料於 一記錄媒體（例如，光碟）之上。 (二） 先前技術 關於記錄資料於一記錄媒體（例如，光碟）之上，資料 調變係以與該記錄媒體相匹配的方式實行，而在資料於該 記錄媒體上的記錄、或是資料自該記錄媒體上的重製方面， 所記錄或重製的信號或碼所包含的直流成份容易導致一光 碟裝置的一伺服控制信號產生波動（FLUCTUATION)、或是 導致產生抖動（JITTER) ’因此，如果可能的話，調變信號 或調變碼中最好不要含有直流成份。 所謂的數位多功能光碟（DVD)係使用8至16(8/16)調 變，其係根據運算長度限制（RLL,RUN LENGTH LIMITING)(2，10)法則將一 8位元的資料位元串調變爲一 16 位元的資料位元串’其中須注意的是，RLL(2,10)係將一資 料位元串轉換成一通道位元串，該通道位元串係包括介於 鄰接的”1”位元之間、不小於2且不大於，，1〇”的，，〇，，位元， 特別是’ RLL(2，l〇)法則中數字，，2”代表介於鄰接的”丨，，位元 之間、連續的”0”位元的最小數目（亦指一最小運算長度）， 另一方面，數字” 1 0 ”代表介於鄰接的”丨，，位元之間、連續 的0位兀的最大數目（亦指一最大運算長度），更進一步來 說’ 8 /1 6 g周變可藉由從以數位總和値（D s v，D〗G T T a [ s U Μ 1262482 V A L U E)爲基礎所構成的複數個表中選取一碼字元（c 〇 d e WORD)、而有助於抑制該直流成份，DSV定義成在不歸零 倒置（NRZI)轉換之後與通道位元串連接在一起，並且代 表”+Γ’的一總和値，其中該總和値係成功地分別將和d 加至自該通道位元串的一領導位元（LEADING BIT)所產生 的”1”和”0”所獲得，DSV係用以指出包含在該通道位元串 中的直流成份的程度，在8/16調變中，一碼字元自複數個 事先準備好的表中被選出，使得DSV變爲最小、而該通道 位元串中的直流成份所造成的波動亦因此獲得抑制。 如上所述，在8/1 6調變中，資料位元串係分成以位元 爲單位的一個個資料字元（DATA WORD)，再被轉換成一16 通道位元的碼字元，資料位元相對於通道位元的比率所顯 示的一編碼率等於1 /2，高編碼率暗示有一段長時間可用於 偵測每個通道位元，其結果是，編碼率是越高越好。 習知技術中另一種碼係根據RLL法則針對光碟或磁碟 所定義，其具有高於8/16調變的2/3的編碼率，即係藉由 2 / 3調變所獲得，更特別的是，在2 / 3調變中，2資料位元 在RLL(1，7)法則下被調變成3通道位元，其中，，〇”的運算長 度等於1或更多以及7或更少，換句話說，，，〇，，的最小運算 長度是”1” ’ ”0”的最大運算長度是，，7 ”。第十五圖係爲傳統 RLL(1，7)中用於2/3調變的一碼轉換表，在第十五圖的碼 轉換表中’藉由將2資料位元當作一調變目標、連同一後 繼的或是後續的資料位元以及前導通道位元的一終端位 元，可獲得3通道位元，在第十五圖中，參考標記” χ，，指出 一 8 - 1262482 在後續資料位元以及前導通道位元中也許會有，，〇，，位元或 是”1”位元，在以RLL(1，7)爲基礎的2/3調變中5資料位元 串轉換成包含”0”位元的通道位元串，其中，，〇，，位元係介於 鄰接的”1”位元之間、不小於1亦不大於7，因此，在NRZI 記錄中，記號或空格被限制於2T或2T以上以及8T或8T 以下（其中參考標記Τ代表一通道位元長度），日本公開特 許第10-3 4〇 5 43號（專利文件1)以及第2000-3 3 26 1 3號（專利 文件2)提供一種在上述的RLL(1，7)法則之下將資料位元串 編碼成爲通道位元串的方法。 其中已被指出的是，在記錄於一高密度的光碟的一重 製信號當中，由於記號和空格長度簡短圖案所造成的信號 振幅減小，使得通道位元的偵測變得困難，偵測窗的寬度 在8/16調變中被資料位元長度標準化成和1/2 —樣狹窄， 卻在（1，7)調變中和2/3 —樣寬廣，然而，最短的記號長度 或是空格長度在8/16調變中和3/2 —樣長，卻在（1，7)調變 中和4/3 —樣短，這樣一種在最短記號長度或是空格長度 方面的減少，對於藉由最短記號或空格而記錄於一記錄部 份以及自該記錄部份而重製的重製信號來說，所帶來的是 振幅方面的減少，當一重製信號藉由一比較器的使用而被 轉換成二進位的資料，則振幅的減少容易導致因雜訊所產 生的抖動的增加。上述由於最小運算長度的連續發生所產 生的問題已於日本公開特許第11-346 1 54號中被指出（專利 文件3 )。 然而，不論最短記號長度或是空格長度哪一方被縮短， -9- 1262482 振幅上的減少皆可藉由使用局部響應最大近似 (P R M L 5 P A R TIA L RESPONSE MAXIMUM LI K E LI Η Ο 0 D ) 1¾ i!j 方法處理該重製信號而獲得補償，在PRML偵測中，一重 製波形先與通道位元串所具有的複數個候選波形的其中之 一相比較，再從通道位元串中選取最有可能成爲重製波形 的候選波形。根據這種偵測，即使當候選波形的一部份具 有信號振幅減小以及其餘的候選波形的信號振幅增大，偵 測錯誤仍會減少，在這個構想之下，前述二種不同的候選 波形便可以彼此區別出來。 習知技術中，應用於根據RLL(1，7)法則所定義的2/3 調變的調變方法具有一個優秀的特徵，即爲編碼率和2/3 一樣高以及偵測窗寬度可更爲寬廣，然而，對於RLL(1，7) 調變之下的通道位元串來說，” 1，，的運算長度似乎具有較高 的可能性，並且2T圖案的最短圖案亦因此容易連續產生（其 中參考標記T代表通道位元長度），上述的最短圖案係對應 於NRZI記錄中的最短記號或是最短空格，在prmL偵測 中，偵測錯誤便因此常產生於包括2 T的連續圖案的重製信 號之中，藉由使用P RM L偵測方法，可以淸楚分辨具有2 T 圖案的重製波形以及具有3T或更多圖案的重製波形之間的 不同，然而，在具有2 T的連續圖案的部份當中，卻很難僅 藉由如前所述之重製波形而明確指出通道位元串的相位。 在PRML偵測中，藉由參考位於每個連續圖案之前或 之後的重製波形所獲得的資訊，可以明確指出位於具有2 T 的連續圖案之部份的通道位元串，重製波形中的雜訊混合 -10- 1262482 容易引起一偵測錯誤，該偵測錯誤係發生於當進行偵測於 欲以一 2 T之較長的連續部份中的T的一通道位元長度、更 換2 T的一整個連續圖案之時，在這種情形之下，一偵測錯 誤便會佈滿藉由一通道位元進行更換以及持續複數個位元 組的一整個偵測範圍之中。 在具有2T之長連續圖案（也就是最小運算長度爲1)的 重製信號之中，一較低的信號振幅狀態會持續一段長時間， 這使得欲自重製信號中抽取一通道時脈變得困難，鑑於通 道時脈抽取的不穩定使得2T圖案的連續性不再受到歡迎， 專利文件1和2皆揭露了 RLL(1，7)法則之下的編碼方法， 更進一步來說，專利文件1和2更揭露了在RLL法則之下 冗位（REDUNDANCY)的減少以及DSV獲得控制的一種技 術，然而，對於最小運算長度1的連續狀態所引起的問題 以及其解決方法卻毫無著墨。其次，專利文件3揭露了藉 由使用具有一轉換區（SECTION)的一轉換表、而將最小運 算長度的連續狀態限制於一預先決定的次數數目，然而， 專利文件3卻只使用一變數長度碼、而從不考慮任何的編 碼率。 除此之外’自光碟重製藉由使用（1，7)調變而被記錄的 信號亦是不利的’其中對於〇,7)調變來說、一低頻成份尙 包括於該重製信號之中’尤有甚者’重製信號中的低頻成 份還會爲了控制一光碟裝置而改變一伺服控制信號。 (三）發明內容 因此，本發明之一目的在於提供一碼調變方法和一碼 -11- 1262482 調變裝置，用以獲得具有與（1，7)調變相同的一編碼率的一 調變碼，該方法可避免或禁止一種圖案的存在，該圖案容 易導致一通道位元串中一重製信號之一偵測錯誤的產生’ 並且適用於高密度記錄，同時直流成份也會減少。 本發明之另一目的在於提供一種解調變方法以及解調 變裝置，用以讀取前述之碼以及一資訊記錄媒體，該資訊 記錄媒體係藉由該碼之使用以記錄資料，並可預防或是禁 止偵測錯誤的產生。 爲了解決上述問題，根據本發明所述之碼調變方法和 碼調變裝置，一運算長度具有與與（1，7)調變相同的2/3的 編碼率、並且指出夾在通道位元串的”1”位元之間的”〇”位 元的數目，一資料位元串被轉換成通道位元串使得運算長 度具有一最小値1以及一最大値1 〇，此外，在轉換任何資 料位元串時，通道位元串並不包括運算長度1連續地重覆 六次或更多次、如”1010101010101”的一圖案。 再者，通道位元串具有一 D S V控制位元用以根據一 D S V 而選取一 ” ”位元或” 1 ”位元，藉由根據D S V以選取D S V控 制位元的一値以及藉由使用用於資料位元串的隨機資料， 一信號的一頻率成份可自通道位元串的NRZI轉換而獲得， 並且自該頻率成份的一最大値減少20dB、更多（當頻率爲 1/10,000)或是更少（當頻率爲一通道時脈頻率）。 此外，根據本發明所述之解調變方法，包括下列步驟： 針對每個碼字元分離該通道位元串之前，偵測於一替換法 則之下被替換的一圖案，其中該替換法則係使用於連續的 -12- 1262482 I勺該圖案； 勺碼字元； 一資料字 道位元串 的該碼字 子兀的一 通道位元 Ϊ含8位 :複數個 的一資料 通道位元 同步圖案 偵測於一 前一圖案 ，含12位 變表，用 丨出12通 由使用顯 該解調變 資料字元 該碼字元；在替換之前藉由前一圖案替換被偵測E 以及將該圖案分離成包含1 2位元的該通道位元串_ 以複數個儲存包含具有8位元的一資料位元串的 元的解調變表，並對應於包含具有1 2位元的該通 的該碼字元，選取該解調變表用以解調變被分離 元，該碼字元係以顯示具有1 2通道位元的後續碼 資訊爲基礎；以及藉由使用指出該碼字元具有1 2 的該資訊以及使用被選取的該解調變表，而獲得4 元的該資料位元串的該資料字元。 此外，根據本發明所述之解調變裝置，包括 解調變表，用以儲存包含8位元的一資料位元串 字元（DATA WORD)，並對應於包含12位元的該 串的該碼字元；自該通道位元串偵測被置入的一 的裝置；針對每個碼字元分離該通道位元串之前 替換法則之下被替換的一圖案、在替換之前藉由 替換被偵測的該圖案、以及將前一個圖案分離成名 元的該通道位元串的碼字元的裝置；選取該解調 以解調變被分離的該碼字元，其中該碼字元係以我 道位元的該後續碼字元的一資訊爲基礎；以及藉 示1 2通道位元的該碼字元的該資訊以及被選取的 表、而獲得包含具有8位元的該資料位元串之該 的裝置。 此外，根據本發明所述之資訊記錄媒體，係用以記錄 藉由一通道位元串之NRZI轉換所獲得、以及製作成對應於 1262482 一凹面長度（PIT LENGTH)和一凹面間隔（PIT INTERVAL)的 一資訊’在該記錄媒體中，該資訊係被記錄使得該通道位 兀串中的一運算長度具有一最小値1以及一最大値10，除 了於一預先決定的期間置入的一同步圖案之外，使得該運 算長度1連續重覆六次或更多次的一圖案的出現係於該通 道位元串中被禁止，一信號的一頻率成份，該信號係自一 凹面（PIT)而被記錄，該凹面具有一功率密度，其中該功率 密度係自該頻率成份的一最大値減少20dB、更多（當頻率爲 1/10,000)或是更少（當頻率爲一通道時脈頻率）。 根據本發明，提供一種碼調變方法以及碼調變裝置， 用以獲侍具有寺於（1，7)調變的一*編碼率的一調變碼、防止 容易產生通道位元串中一重製信號的一偵測錯誤之圖案的 發生、以及適用於具有低直流成份高密度記錄，此外，本 發明之解調變方法和解調變裝置係用以讀取上述碼和一資 訊記錄媒體，該資訊記錄媒體係藉由使用該碼而記錄資料 並且防止偵測錯誤的發生，特別是，本發明之通道位元串 具有一 2 / 3編碼率、一運算長度1的最小値、一最大値1 〇、 以及運算長度1之不多於五次的重覆次數，再者，通道位 兀串具有一足夠低的頻率成份、並且適用於高密度記錄， 考慮到碼字元的範圍時，其有利之處在於，可有效防止對 於三個位元組的影響，更進一步來說，編碼率係爲2/3，且 振幅長度係低於一最大値20dB(當頻率爲1/10, 〇〇〇)或是更 少（當頻率爲一通道時脈頻率），相反的，在解調變之中， 資料係基於1 2通道位元的碼字元單位而處理，再者，在其 一 1 4 一 1262482 之則/之後的碼子兀亦會被參考並且可淸楚了解不會產生偵 測錯誤的電路結構，此外，其有利之處在於，即使在高記 錄密度時通道時脈亦可被穩定地抽取，且不會產生偵測錯 誤。 (五）圖式簡單說明 第一圖係根據本發明的調變方法的一碼轉換表的一部 份； 第二圖係根據本發明的調變方法的該碼轉換表的另一 部份； 第三圖係根據本發明的調變方法的該碼轉換表的另一 部份； 第四圖係根據本發明的調變方法的該碼轉換表的另一 部份； 第五圖（A)係根據本發明的調變方法的一替換法則圖； 第五圖（B)係根據本發明的調變方法的另一替換法則 圖； 第六圖係爲一碼的一頻率特性圖； 第七圖係根據本發明的調變方法的一同步圖案圖； 第八圖係根據本發明的調變方法的一流程圖； 第九圖係根據本發明的調變方法的一調變電路之配置 圖； 第十圖係根據本發明的解調變方法的一流程圖； 第十一圖係根據本發明的解調變方法的一分離法則圖； 第十二圖係根據本發明的解調變方法的一解調變表的 -15- 1262482 一部份； 第十二圖係根據本發明的解調變方法的一解調變表的 另一部份； 第十四圖係根據本發明的解調變方法的一配置圖；以 及 第十五圖係一習知的調變方法的一碼轉換表。 (四）實施方式 爲了淸楚闡明本發明上述及其他的目的、特徵、以及 優點，將配合所附圖示詳細描述本發明實施例。 第一圖至第四圖係根據本發明第一實施例之碼調變方 法的碼轉換表。在第一圖至第四圖中，8位元的資料字元 元〇〇至FF係以十六進位的表示法表示，並配合12通道位 元的對應碼字元以及以S 0至S 2所表示的接續或後續的型 態’在每個表中，上述的資料字元、碼字元、以及接續的 狀態皆是共同地以表的形式呈現，從這裡可以淸楚了解本 發明之碼調變係用以將8位元的資料字元調變成1 2位元的 通道位元、亦係用以實現編碼率（2/3)的8至12調變。 特別是，呈現於第一圖至第四圖中每一個的三個碼轉 換表係分別地使用現今的型態S 0、S 1、S 2 ’需要注意的是 碼轉換表中12通道位元的碼字元除了 ”〇”和”1”之外，還包 括了標記和，，#，，，標記，，*”是用以連鎖二個碼字元的一連 鎖位元，並且當一後續碼字元的一領導位元取得，，1 ”和，’ 〇，， 時其會分別取得，，〇，，和”1”， 標記”#”是一 DSV控制位元， 其可根據因碼字元之連鎖所產生的通道位元串所得到的 _ 1 6 - 1262482 DSV之値，隨意地或選擇性地取得，，〇，，和”〗 第一圖至第四圖中關於型態S 0至S 2的三個碼轉換表 係根據碼轉換表中下一個狀態而相繼地被選取，以產生藉 S碼字元得連鎖而獲得的通道位元串，在由此而獲得的通 道位元串之間，連續資料”〗，，不會出現，且指出資料，，〇，，的 連I買出現數目的運算長度亦總是保持爲1 〇或更少，因此， 資料” 1 ”在通道位元串中不會連續出現，且記錄通道位元串 的NRZI轉換所產生的記號或空格長度亦總是具有不小於2Τ 的一長度（標記Τ代表一通道位元長度），也就是可以令人 淸楚了解’第一圖至第四圖的碼轉換表遵守具有最大運算 長度10的RLL(l，l〇)法則，因此，可以防止小於2Τ的記號 或是空格的產生，因爲其會造成記錄和偵測的困難，上述 的狀況即使當D S V控制位元取得，，〇 ”或，，1，，其中之一時亦可 藉由使用第一圖至第四圖的碼轉換表而保持下去。 再者’第五圖（A)所呈現的連鎖法則係用於連鎖或替換 碼字元，根據該連鎖法則，可以從通道位元串中排除諸 如”1010101010101”等運算長度1重覆六次或更多次的一圖 案，當通道位元串受到NRZI轉換之管轄時，運算長度1 的圖案係以2 T的最短運算長度的一記號或一空格記錄，運 算長度1的連續重覆次數係限制於最多五次，可以避免一 低振幅狀態發生連續或重製，所呈現的連鎖法則係用以連 鎖二個連續的碼字元，以及用以定義藉由在位元序列中不 同於前一個的一碼字元、以替換對應於一預先決定的一位 元串的碼字元之法則。 -17- 1262482 請參閱第五圖（A)，其連鎖法則係應用於連鎖位元” 確定爲或”1”之後藉由碼轉換表所獲得的碼字元，在第 五圖（A)中，替換之前顯示於前一個碼字元的標記”X”代表 了對應於的位元會取得”0，，、”1”、，’#”、以及的其中 之一，對應於”X”的位元位置在替換之前被保持爲一定値且 因此而不會改變，以連鎖法則爲基礎而替換的通道位元串 包括在連鎖的碼字元之中運算長度1可能出現六次或更多 次的重覆次數的所有圖案，根據連鎖法則，通道位元串可 以被無法自碼轉換表中的碼字元所獲得的任何其他圖案所 替換，碼字元的連鎖會先應用於前一個連鎖點，第五圖（A) 的連鎖法則將被適當地應用於每個連鎖點的標誌或是法則 號碼’某些碼字元可被替換二次以連接前一個碼字元以及 後續或接續的碼字元。 藉由第一圖至第四圖之碼轉換表以及第五圖（A)之連鎖 法則可以獲得通道位元串，其具有2/3的編碼率且最小運 算長度爲1、最大運算長度爲10，通道位元串的運算長度 1的重覆次數被限制於五次或更少，當通道位元串受到NRZI 轉換所管轄並且被記錄成資料時，情況被會被滿足使得記 號和空格長度係爲2T或更多以及丨丨T或更少，並且2τ的 記號和空格的連續重覆次數係被限制於五次或更少，在具 有2 T的連續記號和空格的一區域中，重製信號的振幅不會 足夠地被獲得、且因此資料會被錯誤地偵測，藉由限制2T 圖案的連續次數至五次或是更少，可以抑制造成錯誤產生 的圖案的發生。 一 18- 1262482 當2 T圖案的連續產生被限制於五次或更少，即使當2 Τ 圖案連續產生，記號和空格長度業會被限制在i 〇Τ或是更 少’在P R M L偵測中，整個連續的2 T圖案被1 τ所轉換並 且谷易導：(因此1 Τ轉換所造成的一錯誤，然而，如果連續 2 T圖案的數目被限制在五次或更少次，這種由1 τ轉換所 產生的影響會被1 2或更少的通道位元所抑制，因此，即使 考慮到碼字兀的範圍，3位元組的負面影響亦可有效地被 防止。 其次討論包含於碼轉換表中的D S V控制位元，在經由 NRZI轉換所獲得的一信號串中，自通道位元串的領導位元 於每個通道位元加上1(或是-1)可獲得DSV，此時會產生正 或負的極性，DSV係用以指出碼字元的直流成份，當初始 値假設爲0並且因此自領導位元所獲得的D S V之絕對値接 近0時，便可減少直流成份。 根據本發明之碼調變方法，碼字元中DS V控制位元，，#，， 的値可參考碼轉換表獲得，並且碼字元中D S V控制位元，，#，， 的値係決定使得在關於通道位元串的下一個D SV控制位元 之前所計算的DSV之値變爲接近〇，第六圖表示在DSV控 制下經由NRZI轉換之後所獲得之信號的一頻率特徵，橫 座標代表經由通道時脈頻率標準化之後的頻率，縱座標代 表頻率成份的功率密度，請參閱第六圖，根據上述方法而 獲得調變的隨意資料的振幅成份指出頻率的最大値等於通 道時脈頻率的1Μ左右，相反地，很明顯的，振幅成份指 出，一低振幅在頻率等於或少於通道時脈頻率1 /1 0，0 0 0之 1262482 時，該低振幅等於或低於最大値20 dB或是更多，等於或少 於通道時脈1/10,000的通道頻率對應於一伺服控制帶，以 控制一光學讀寫頭的位置，頻帶中的振幅強度自最大値減 少2 0 Db或更多，藉此抑制對於一伺服控制信號具有傷害性 的影響，有利之處在於，位置控制的精確度仍保持著。 本發明還確保第一圖和第四圖之碼轉換表的DSV控制 位元”〇”或”1”不會擾亂對於連續2T圖案之數目的限制以及 運算長度限制，並與碼字元之前或之後的連鎖碼字元無關， 因此’在DSV控制位元出現時，在其之前或之後的通道位 元串的運算長度便無須被檢查，並且”0”或”1”可被當成DSV 控制位元而被任意地選取，其配置電路在結構上亦極其簡 易。 以上所述皆係基於第一圖至第四圖之碼轉換表以及第 五圖（A)之連鎖法則，然而，明顯地，藉由使用調變資料字 元和碼字元之間的對應關係的一調變表可以獲得同樣的好 處’所有在第五圖（A)的連鎖法則之下被替換的圖案皆不包 含具有六個或更多個2T連續圖案的任何圖案，因此，藉由 偵測連續2 T圖案的數目可以忽略一部份的替換，舉例來 說’在第五圖（A)之連鎖法則所包括的圖案當中，只有具 有”1010101010101，，等運算長度i重覆六次或更多次的圖案 可被替換，再者，D S V控制位元的配置亦不限於只有第一 圖至第四圖中碼轉換表的例子，舉例來說，包括作爲一位 元的D S V控制位元的碼字元係分離成具有d S V控制位元，，0，， 的碼字元以及具有DSV控制位元”1”的碼字元等二種型態， - 2 0 - 1262482 分離後的一碼字元可與另一碼字元相結合，除了分離後的 碼字元以及藉此D S V控制位元之位置被改變時，經由上述 運作所獲得的碼轉換表具有D S V控制位元相同的產生頻 率，並且因此而與第一圖至第四圖之碼轉換表具有相同的 特徵。 在長通道位元串的情形之中，常會發生當通道時脈處 於一混亂狀態或是一非同步狀態而造成解調變錯誤的產 生’爲了避免解調變錯誤，一同步圖案常被置入通道位元 串中，因此，即使在重製時同步作業處於混亂狀態，藉由 偵測下一個同步圖案仍可偵測到這樣一種混亂狀態，並且 解調變錯誤的連續性亦可避免。 第七圖係爲應用於本發明之碼調變方法的同步圖案或 碼（以下縮寫爲SYNC碼）的一例，同步圖案或SYNC碼與第 五圖（A)之連鎖法則所得之圖案以及第一至第四圖之碼轉換 表不同，這是因爲第七圖中每個SYNC碼皆包括一運算長 度 12(以 12-運算-長度作代表）的一圖 案” 10000000000001 ”，這個SYNC碼係由四個 SYNC碼或 圖案SY0至SY3(對應於狀態資訊或狀態S0至S2)所構成， 如第七圖所示，同樣的碼或圖案係用於狀態資訊S 1和S 2， 每個SYNC碼或圖案係基於被置入的狀態資訊而被選取， 在同步圖案置入之後的碼字元當中，狀態資訊會提供給S 1 或S 2，並且因此碼運作會繼續，在這種方式之下，即使S YN C 碼被置入，1-運算-長度連續重覆六次或更多次的圖案也不 會以最小運算長度保持在1的方式出現，雖然碼包括了 1 2_ -21- 1262482 運算-長度（運算長度12)的圖案，SYNC碼仍然會以不小於 一運算長度11的圖案形成（也就是11-運算-長度）5這是因 爲這種圖案不會出現於通常的碼字元中。 在使用S YN C碼或圖案的情形中，第五圖（B )的一連鎖 法則以及標記1 0亦可用於連鎖碼字元，使得S Y N C碼不超 過最大運算長度10，換句話說，第五圖（A)的連鎖法則不能 應用於S YN C碼和碼字元之間的連鎖，並且因此，應該使 用連鎖法則1 0，如第五圖（B)所示，連鎖法則或標記1 〇係 包括一預先決定的圖案SY3，其將會於下文進行陳述，並 且S Y 3係被當作一後續或現今的碼字元而連鎖。 每個SYNC碼或圖案皆包括一 DSV控制位元，在碼轉 換表中的DSV控制位元係只用於一部份的碼字元，因此， D S V控制位元不會以附屬於調變資料串的方式出現，根據 本發明之碼調變方法，DSV控制位元之値係直到下一個DSV 控制位元出現後才會決定或固定，有利之處在於，藉由提 供D S V控制位元給每個s YN C碼，D S V控制位元之値便可 在同步圖案的每個期間中決定。 四種SYNC碼或圖案SY0至SY3係被隨意地選取和可 能被規則地選取，用以確定關於被偵測的S YN C碼的通道 位元串的一近似位置，然而，如果不需要確認位置，S yn C 碼SY0至SY3便會被隨意地選取、或是只有同步圖案SY0 被使用’再者，S YNC碼或圖案並不限制於所述之圖案並且 具有一任意長度，藉由SYNC碼或圖案，便可以修改SYNC 碼以及狀態資訊，其中狀態資訊係顯示碼轉換表以及係於 -22 - 1262482 同步圖案之後使用。 第八圖係上述碼調變方法之流程圖，在調變開始時， 資訊情況便初始化成s 1或s 2，並且D s V初始化成〇，S YNC 碼或圖案接著便依序置入位於資訊框架首部的同步圖案 SY0、SY1、SY2、以及SY3，其中該資訊框架係藉由分離 位於一恆常位元組（例如9 1位元組）的資料所獲得，在這種 情形中，調變開始之後的位置係對應於置入S YN C碼或圖 案SYO的一位置，同步圖案SYO係對應於狀態資訊（狀態）S1 或S 2而選取，在置入同步圖案之後，狀態資訊便更新爲S 1 或S2，在置入同步圖案之後同步圖案尙包括DSV控制位 元，然而，在更新狀態資訊之前，同步圖案並不包括DSV 控制位元並且因此位元亦尙未決定。 隨後，資料位元便相繼地被8位元所抽取出直到置入 下一個同步圖案的位置，並且被抽取出的資料位元係藉由 使用碼轉換表而被轉換成碼字元，此外，狀態資訊以碼轉 換表爲基礎而被更新，再者，在碼字元的替換之後，碼字 元係基於連鎖法則而連鎖，由於在置入同步圖案之後的碼 字元應該與前一個同步圖案連鎖在一起，因此碼字元的連 鎖法則不會被應用，當藉由使用碼轉換表所獲得的碼字元 包括DSV控制位元時，舊的DSV控制位元之値便基於DSV 而決定，其中DSV係相對於直到DSV控制位元之前所新獲 得的通道位元串所計算的D S V。 如前所述，同步圖案係定期地置入而編碼亦被進行， 直到下一個DSV控制位元出現之前，DSV控制位元之値都 -23- 1262482 不會被決定，然而，在資料結束時，最後一個D S V控 元之値會基於相對於直到D SV控制位元之前所新獲得 道位元串所計算的DSV而決定，並且接著編碼便會完 如果置入同步圖案的期間決定成大約1 〇 〇位元組，則 圖所顯示的頻率特徵便會不受制如圖案所產生的效率 的影響而獲得，碼轉換表或是同步圖案中所指出的一 的DSV控制位元可用以控制記錄資料的極性，藉由在 決定的位置使用DSV控制位元可以限制記錄於記錄光 的同步圖案。 第九圖係根據本發明之碼調變方法所使用的一調 路，該調變電路包括一碼轉換表參考電路1、一狀態 器2、一多工器3、以及一同步圖案置入電路4，碼轉 參考電路1包括第一至第四圖之碼轉換表1〇1，碼轉 參考電路1係接收每個8位元的一資料串B (t )、以及 態暫存器2所傳輸而來的狀態資訊s (t)，碼轉換表參 路1根據狀態資訊S(t)、參考第一至第四圖之碼轉換表i 輸出具有12通道位元的一碼字元x(t)，其次，碼轉換 考電路1根據碼轉換表1 〇〗而輸出下一個狀態資訊給 器3’多工器3自同步圖案置入電路4接收下一個狀 訊、選取它 '並且輸出下一個狀態資訊s(t+1)以指出 個狀態給狀態暫存器2，狀態暫存器2對應於下一個 串B(t)而輸出狀態資訊s(t)給碼轉換表參考電路1以 步圖案置入電路4。 如前所述’碼轉換表參考電路1係具有複數個碼 一 24 - 制位 的通 成， 第六 降低 部份 預先 碟中 變電 暫存 換表 換表 自狀 考電 01、 表參 多工 態資 下一 資料 及同 轉換 1262482 表1 〇 1、基於狀態暫存器2所保持的狀態資訊s(t)而轉換碼 轉換表1 01、以及對應於所給的資料字元和狀態資訊S (t+ 1 ) 而輸出碼字元S(t)，其中狀態資訊S(t+1)係指出所參考的 下一個碼轉換表，再者，一連接電路，也就是，一連鎖電 路5係連接於第九圖之調變電路於碼轉換表參考電路1以 及同步圖案置入電路4的輸出端，連鎖電路5亦連接於一 DSV控制電路6，一通道位元串係自DSV控制電路6而輸 出。 同步圖案置入電路4基於在一預先決定的期間由狀態 暫存器2所保持的狀態資訊S (t)而輸出同步圖案以置入通 道位元串之中，並且輸出此狀態資訊，自碼轉換表參考電 路1所輸出的狀態資訊以及自同步圖案置入電路4所輸出 的狀態資訊皆如前所述地經由多工器3而傳輸給狀態暫存 器2，狀態暫存器2之運作係使得下一個狀態資訊3(1+1)更 新’並且在每次自碼轉換表參考電路1輸出碼字元時被保 持以及在每次自同步圖案置入電路4輸出同步圖案時保 持。 連鎖電路5之運作係用以連接或連鎖自碼轉換表參考 電路1所輸出的碼字元以及自同步圖案置入電路4所輸出 的同步圖案’藉由產生一連鎖碼字元，爲了連接或連鎖這 些碼字元，連鎖電路5會決定包含於最後碼字元至，，〇，，或，,广 的一合倂或連接位元之値，並且藉由同步圖案而核對第 五圖（Α)之連鎖法則’當連鎖法則對應於同步圖案時，碼字 元會被替換並且結果資料輸出成爲序列資料以指出通道位 - 25 - 1262482 兀串。 D S V控制電路6係對於連鎖電路5所傳送的序列資料 作反應，並且抽取顯示D S V控制位元的資訊，其中D S V控 制位兀係包含於自連鎖電路5所輸出的序列資料，其次，D S V 控制電路6係決定DSV控制位元並且將其輸出以作爲通道 位元串，使得D S V之値接近〇，由於調變電路具有上述結 構，便獲得適用於高密度記錄的通道位元串，同時不會出 現1-運算-長度重覆六次或更多次的圖案產生，這種通道位 兀串會使得低頻成份變得足夠小。 接下來所敘述的是根據本發明編碼調變方法以及編碼 調變電路所獲得的通道位元串之一解調變方法，藉由第十 圖之流程圖可明確陳述解調變方法，首先，由於決定重製 信號，同步圖案自通道位元串中被抽取出，碼字元的範圍 基於被抽取的同步圖案而明確界定在每套的12通道位元， 因此’對於每個圖案的偵測便可進行，其中的每個圖案係 基於藉由連鎖法則的使用而自通道位元串所獲得的範圍而 替換、亦係在替換之前回傳的前一個碼字元或圖案，因此， 該圖案即被分離成碼字元，使用第五圖（A)的連鎖法則有助 於圖案在反轉換以及判斷方面的偵測、或是有助於圖案在 分割方面的決定，此決定可以藉由在第十一圖所示的三個 分離法則替換碼字元而淸楚了解，接著，藉由上述方法所 獲得的碼字元之使用以及參考解調變表所得的解調變結 果，便可獲得8位元的資料字元，在第十一圖中，於替換 之前包含在前一個圖案中的參考標記，，X”代表位元可取 -26- 1262482 得”1”或”0”其中之一，在替換之前，對應於替換之後的參 考標記”x”的位元仍會保持原値。 第十二和第十三圖係代表自1 2通道位元的碼字元而獲 得8位元的資料字元所用的解調變表，請參考第十二和第 十三圖，三個解調變表T0至T2如圖所示，考慮解調變目 標碼字元、在該解調變目標碼字元之後的一後續碼字元、 以及同步圖案，選取所使用的解調變表T0至T2的其中之 一，當該解調變目標碼字元之後的下一個碼字元係以位 元”1”作爲起始、或是當下一個同步圖案指出狀態0的SY0 至SY2，即使用解調變表T0，當該解調變目標碼字元之後 的下一個碼字元係以”〇〇〇〇”作爲起始、或是當下一個同步 圖案指出狀態0的S Y3，即使用解調變表T1，當該解調變 目標碼字元之後的下一個碼字元係以”01”、”001”、或 是”0 0 0 1 ”作爲起始、或是當下一個同步圖案指出狀態1和2 的SY0至SY3，即使用解調變表T2。對應於該解調變目標 碼字元，8位元的資料字元係以1 6進位的表示方法來表示， 當同步圖案以解調變目標碼字元的型態存在之後，即選取 解調變表T0，並且參考當選取解調變表T2時對應於狀態 資訊S 0所產生之同步圖案、以及參考對應於狀態資訊S 1 或S2所產生之同步圖案，因此，資料字元即以上述之方式 產生。 在解調變表中，1 2位元的通道位元串的碼字元係對應 於8位元的碼字元，因此，有利之處在於任何錯誤皆不會 以上述方式散佈或傳播，這是相對於長度可變之轉換表之 - 27 - 1262482 使用所產生的一可變方塊碼（VARIABLE BLOCK CODE)而 言，這對於抑制因對於2 T圖案之重覆次數的限制所造成的 任何錯誤的傳播、以及減少資料率的錯誤是非常有效的。 此外，需要注意的是未以碼字元的方式顯示於表中的 I 2通道位元的圖案、以及在資料字元的行列中以標記被 指定的圖案，這些圖案並不是根據本發明之解調變方法所 產生，當偵測到這些圖案時，無法被解調變的圖案之程序 便會進行，產生一光學資料字元的同時亦產生顯示包含一 錯誤的一資料字元的資訊，附帶一提的是，決定重製信號 的PRML偵測使得排除由未顯示於解調變表中的通道位元 串所決定的大部份圖案變爲可行，是故，決定程序和解調 變中的錯誤便可進一步地減少。 接著配合第十四圖陳述解調變電路的配置。通道位元 串被放入一同步圖案偵測電路7，同步圖案偵測電路7輸 出該通道位元串和藉由參考被偵測同步圖案之位置而指出 碼字元之範圍位置的資訊，因此，一分離和替換電路8偵 測並替換符合第十一圖之分離法則的圖案、並且進一步地 將通道位元串分離成碼字元且將其輸出，一解調變表參考 電路9將由上述所得之碼字元串轉換成具有8位元的資料 字元並將其輸出，爲了解調變具有12通道位元的碼字元， 解調變表參考電路9參考後續的碼字元和同步圖案、選取 一解調變表9 0 1、以及抽取對應該碼字元之資料字元，解 調變表參考電路9輸出顯示關於該碼字元之解調變的不 可行性，其中該碼字元並不會出現於解調變表中，在解調 - 28- 1262482 變之中，1 2通道位元的碼字元單位以及至 調變之前/之後的碼字元會被參考，因此， 可防止解調變錯誤的增加。 根據本發明碼調變方法所獲得之通道 記錄媒體之中，藉由通道位元串的NRZI 號，並且該信號係對應於一凹面長度（PIT 面間隔（PIT INTERVAL)而記錄，這種記錄 使以一高記錄密度實行記錄時，通道時脈 取’並且可以減少偵測錯誤，由凹面所獲 少包括一伺服帶的成份，並且因此用於偵 寫運作的追蹤特性也不會惡化。 以下陳述本發明所述之光學記錄媒體 學記錄媒體中，通道位元串係受到的管制 長度和凹面間隔的圖案記錄於光學記錄媒 光學記錄媒體中，除了同步圖案之外，通 具有一最小運算長度値1以及一最大運算 禁止運算長度1重覆六次或更多次的圖案 同步圖案係在一預先決定的期間被置入， 錄媒體中資訊記錄的方式是，自凹面被讀 成份係低於該頻率成份最大値的20dB、 1 / 1 0,000)或是更少（當頻率爲一通道時脈頻 即使本發明發明係以以上之較佳實施例來 於熟習本項技術者來說，本發明仍不限於 用方法，尤有甚者，凡依本發明所附申請 -19 一 少足夠的位於解 這種電路結構便 位元串的一光學 轉換可獲得一信 LENGTH)和一凹 方式的特徵是即 也可以穩定地抽 得的重製信號極 測信號的光學讀 。在本發明之光 、並且係以凹面 體中，其次，在 道位元串係根據 長度値1 0、以及 :而形成，不用說 再者，在光學記 取的信號的頻率 更多（當頻率爲 率）。 作說明，然而對 這些實施例和使 專利範圍所做的 1262482 均等變化及修飾，皆爲本發明專利範圍所涵蓋。 元件符號說明 1 碼轉換表參考電路 2 狀態暫存器 3 多工器 4 同步圖案置入電路 5 連鎖電路 6 D S V控制電路1262482 玖, Description of the invention: (I) Technical Field of the Invention The present invention relates to a code modulation method and apparatus, Demodulation method and device, And information recording media, Used to record or reproduce digital data on a recording medium (for example, Above the disc). (ii) Prior art regarding the recording of information on a recording medium (for example, Above the disc) The data modulation is performed in a manner that matches the recording medium. And the records on the record medium, Or the material from the reproduction of the recording medium, The DC component contained in the recorded or reproduced signal or code tends to cause a servo control signal fluctuation (FLUCTUATION) of a disc device, Or cause jitter (JITTER) if possible, It is best not to include DC components in the modulation signal or modulation code. The so-called digital versatile disc (DVD) uses 8 to 16 (8/16) modulation. It is based on the operation length limit (RLL, RUN LENGTH LIMITING)(2, 10) The rule converts an 8-bit data bit string into a 16-bit data bit string. RLL (2, 10) Converting a data bit string into a channel bit string, The channel bit string is included between adjacent "1" bits, Not less than 2 and not more than, , 1〇", , Oh, , Bit, Especially the 'RLL (2, L〇) the number in the law, , 2" stands for contiguous" , Between bits, The minimum number of consecutive "0" bits (also referred to as a minimum computation length), on the other hand, The number "1 0 " represents the contiguous "丨, , Between bits, The maximum number of consecutive 0-bits (also referred to as a maximum computation length), Further, the 8/1 6 g cycle can be obtained by taking the sum of digits (D s v, D〗 G T T a [ s U Μ 1262482 V A L U E) Select one code character (c 〇 d e WORD) from the plurality of tables formed by the basis, And help to suppress the DC component, The DSV is defined to be connected to the channel bit string after the non-return to zero (NRZI) conversion. And on behalf of a total sum of "+Γ", The sum of the sums is successfully obtained by adding "d" to "1" and "0" generated by a leader bit (LEADING BIT) of the bit string of the channel, respectively. DSV is used to indicate the extent of the DC component contained in the bit string of the channel. In 8/16 modulation, One code character is selected from a plurality of previously prepared tables. Make DSV to a minimum, The fluctuation caused by the DC component in the channel bit string is also suppressed. As mentioned above, In the 8/1 6 modulation, The data bit string is divided into one data character (DATA WORD) in units of bits. It is then converted into a 16-bit bit code character. The encoding rate of the data bit relative to the channel bit is equal to 1 /2. The high coding rate implies that there is a long period of time available to detect each channel bit. the result is, The higher the coding rate, the better. Another code in the prior art is defined for a disc or a disc according to the RLL rule. It has a 2/3 encoding rate higher than 8/16 modulation. That is obtained by 2 / 3 modulation, More specifically, In 2 / 3 modulation, 2 data bits in RLL (1, 7) The rule is transferred to a 3-channel bit, among them, , 运算" is equal to 1 or more and 7 or less. in other words, , , Oh, , The minimum operation length is "1" ’ ” ” 0”, the maximum operation length is, , 7". The fifteenth picture is the traditional RLL (1, 7) A code conversion table for 2/3 modulation, In the code conversion table of the fifteenth figure, by using 2 data bits as a modulation target, Even the same or subsequent data bits and a terminal bit of the leading channel bit, Get 3 channel bits, In the fifteenth figure, Reference mark" χ, , Point out that an 8 - 1262482 may be in the subsequent data bit and the leading channel bit, , Oh, , Bit or is a "1" bit, In RLL (1, 7) In the base 2/3 modulation, the 5 data bit string is converted into a channel bit string containing "0" bits, among them, , Oh, , The bit system is between adjacent "1" bits, Not less than 1 or not more than 7, therefore, In the NRZI record, Marks or spaces are limited to 2T or more and 8T or less (where the reference mark Τ represents the length of one channel), Japanese Patent Laid-Open No. 10-3 4〇 5 43 (Patent Document 1) and No. 2000-3 3 26 1 3 (Patent Document 2) provide an RLL (1, in the above). 7) The method of encoding a data bit string into a channel bit string under the law. It has been pointed out that Among the reproduced signals recorded on a high-density optical disc, The signal amplitude is reduced due to the short pattern of marks and space lengths, Making the detection of channel bits difficult, The width of the detection window is normalized to a length of 1/2 in the 8/16 modulation, But at (1, 7) Modulation neutralization 2/3 - wide and wide however, The shortest mark length or the length of the space is 8/16 and 3/2. But at (1, 7) Modulation Neutral 4/3 - short Such a reduction in the length of the shortest mark or the length of the space, For a remake signal recorded by a shortest mark or space and recorded in a recorded portion and reproduced from the recorded portion, What is brought about is the reduction in amplitude, When a reproduced signal is converted into binary data by the use of a comparator, The decrease in amplitude is likely to cause an increase in jitter due to noise. The above-mentioned problem due to the continuous occurrence of the minimum calculation length has been pointed out in Japanese Laid-Open Patent Publication No. 11-346 1 54 (Patent Document 3). however, Regardless of the length of the shortest mark or the length of the space, which side is shortened, -9- 1262482 Amplitude reduction can be achieved by using the local response maximum approximation (P R M L 5 P A R TIA L RESPONSE MAXIMUM LI K E LI Η Ο 0 D ) 13⁄4 i! The j method processes the reproduced signal to obtain compensation, In PRML detection, A reconstructed waveform is first compared to one of a plurality of candidate waveforms of the channel bit string, Then select the candidate waveform that is most likely to be the reconstructed waveform from the channel bit string. According to this detection, Even when a portion of the candidate waveform has a reduced signal amplitude and the signal amplitude of the remaining candidate waveforms increases, The detection error will still decrease. Under this concept, The two different candidate waveforms described above can be distinguished from one another. In the prior art, Applied according to RLL (1, 7) The 2/3 modulation method defined by the law has an excellent feature. That is, the coding rate is as high as 2/3 and the detection window width can be wider. however, For RLL (1, 7) For the channel bit string under modulation, " 1, , The length of the operation seems to have a higher probability. And the shortest pattern of the 2T pattern is thus easily generated continuously (where the reference mark T represents the channel bit length), The shortest pattern described above corresponds to the shortest mark or the shortest space in the NRZI record. In prmL detection, Detection errors are often caused by re-signals that include a continuous pattern of 2 T. By using the P RM L detection method, It is possible to distinguish between a reproduced waveform having a 2 T pattern and a reproduced waveform having a 3T or more pattern, however, Among the parts with a continuous pattern of 2 T, It is difficult to clearly indicate the phase of the channel bit string by merely recreating the waveform as previously described. In PRML detection, By referring to the information obtained by reconstructing the waveform before or after each successive pattern, It can be clearly pointed out that the channel bit string located in the portion of the continuous pattern having 2 T, Noise mixing in the remake waveform -10- 1262482 is easy to cause a detection error, The detection error occurs when a channel length of T is detected in a continuous portion of a longer length of 2 T, When replacing a whole continuous pattern of 2 T, In this case, A detection error is filled with a one-channel bit replacement and continues throughout the entire detection range of the plurality of bytes. Among the reproduced signals having a continuous pattern of 2T length (that is, the minimum operation length is 1), A lower signal amplitude state will last for a long time, This makes it difficult to extract a channel clock from the remake signal. In view of the instability of the channel extraction, the continuity of the 2T pattern is no longer welcome. Patent documents 1 and 2 both disclose RLL (1, 7) The coding method under the law, Further, Patent Documents 1 and 2 further disclose a technique for reducing the redundancy (REDUNDANCY) and controlling the DSV under the RLL rule. however, The problem caused by the continuous state of the minimum operation length of 1 and its solution are not in the ink. Secondly, Patent Document 3 discloses that by using a conversion table having a transition zone (SECTION), Limiting the continuous state of the minimum operational length to a predetermined number of times, however, Patent Document 3 uses only one variable length code, Never consider any coding rate. Other than that, since the use of optical disc reproduction (1, 7) The signal that is recorded and modulated is also unfavorable. 7) In terms of modulation, A low frequency component 包括 included in the reproduced signal, particularly the low frequency component of the remake signal, also changes a servo control signal for controlling a disc device. (3) Summary of the invention Therefore, An object of the present invention is to provide a code modulation method and a code -11- 1262482 modulation device, Used to get with and (1, 7) Modulating a modulation code of the same coding rate, This method avoids or prohibits the presence of a pattern, This pattern easily results in the detection of one of the reproduced signals in a channel string, and is suitable for high-density recording. At the same time, the DC component will also decrease. Another object of the present invention is to provide a demodulation method and a demodulation device. For reading the aforementioned code and an information recording medium, The information recording medium uses the code to record data. It can prevent or prohibit the detection of errors. In order to solve the above problems, A code modulation method and a code modulation device according to the present invention, An operation length has an AND with (1, 7) Modulate the same 2/3 encoding rate, And indicate the number of "〇" bits sandwiched between the "1" bits of the channel bit string, A data bit string is converted into a channel bit string such that the operation length has a minimum 値1 and a maximum 値1 〇, In addition, When converting any data bit string, The channel bit string does not include the operation length 1 continuously repeated six or more times, A pattern such as "1010101010101". Furthermore, The channel bit string has a D S V control bit for selecting a "" bit or a "1" bit according to a D S V , By selecting a set of D S V control bits according to D S V and by using random data for the data bit string, A frequency component of a signal can be obtained from the NRZI conversion of the channel bit string. And reducing the maximum 値 of the frequency component by 20 dB, More (when the frequency is 1/10, 000) or less (when the frequency is a channel clock frequency). In addition, According to the demodulation method of the present invention, Includes the following steps: Before separating the channel bit string for each code character, Detecting a pattern that is replaced under a replacement rule, Wherein the replacement rule is used for a continuous -12-1262482 I scoop of the pattern; Spoon code character; A channel bit of the codeword sub-string of a data byte string contains 8 bits: a plurality of data channel bit sync patterns are detected in a previous pattern, With 12-bit variable table, Use the 12-pass to use the demodulation to change the data character. The code character; Substituting the detected E by the previous pattern and separating the pattern into the channel bit string containing 12 bits before the replacement, the solution storing the element containing a data bit string having 8 bits in multiples Modulation table, And corresponding to the code character containing the pass having 12 bits, Selecting the demodulation variable table to demodulate the separated element, The code character is based on displaying subsequent code information having 12 channel bits; And by using the information indicating that the code character has 1 2 and using the selected demodulation table, And the data element of the data bit string of 4 yuan is obtained. In addition, a demodulation device according to the present invention, Including demodulation tables, Used to store a data bit string (DATA WORD) containing 8 bits. And corresponding to the code character of the string containing 12 bits; A device for detecting a placed one from the channel bit string; a pattern that is replaced under the replacement rule before separating the channel bit string for each code character, By replacing the detected pattern, And means for separating the previous pattern into code character elements of the channel bit string of the name; Selecting the demodulation to demodulate the code character that is separated, Wherein the code character is based on a piece of information of the subsequent code character of the own bit; And the information of the code character of the 12-bit bit and the selected table, A device containing the data bit string having 8 bits is obtained. In addition, According to the information recording medium of the present invention, Used to record the NRZI conversion obtained by a channel bit string, And a piece of information corresponding to a concave length (PIT LENGTH) and a concave interval (PIT INTERVAL) in the recording medium, The information is recorded such that an operation length in the channel bit string has a minimum 値1 and a maximum 値10, In addition to a synchronization pattern placed during a predetermined period of time, The occurrence of a pattern in which the operation length 1 is continuously repeated six or more times is prohibited in the channel bit string. a frequency component of a signal, The signal is recorded from a concave surface (PIT). The concave mask has a power density, Wherein the power density is reduced by 20 dB from a maximum 値 of the frequency component, More (when the frequency is 1/10, 000) or less (when the frequency is a channel clock frequency). According to the present invention, Providing a code modulation method and a code modulation device, Used to get a temple with a temple (1, 7) Modulation of a * coding rate of a modulation code, Preventing the occurrence of a pattern of detection errors that easily generate a reproduced signal in the channel bit string, And for high-density recording with low DC components, In addition, The demodulation method and demodulation device of the present invention are for reading the above code and a communication recording medium, The information recording medium records data by using the code and prevents detection errors from occurring. especially, The channel bit string of the present invention has a coding rate of 2 / 3, a minimum length of one operation length 1, One maximum 値1 〇, And the number of repetitions of the operation length 1 no more than five times, Furthermore, The channel bit string has a sufficiently low frequency component, And for high density recording, Considering the range of code characters, It is advantageous in that Can effectively prevent the impact on three bytes, Further, The coding rate is 2/3. And the amplitude length is less than a maximum 値 20dB (when the frequency is 1/10, 〇〇〇) or less (when the frequency is a channel clock frequency), The opposite of, In the demodulation, The data is processed based on the code character unit of 12 channel bits. Furthermore, The code 兀 at or after 1 4 1 1262482 will also be referenced and the circuit structure that does not cause detection errors can be understood. In addition, It is advantageous in that The channel clock can be stably extracted even at high recording densities. There is no detection error. (5) Brief Description of the Drawings The first drawing is a part of a code conversion table of the modulation method according to the present invention; The second figure is another part of the code conversion table according to the modulation method of the present invention; The third figure is another part of the code conversion table according to the modulation method of the present invention; The fourth figure is another part of the code conversion table of the modulation method according to the present invention; Figure 5 (A) is an alternative rule diagram of the modulation method according to the present invention; Figure 5 (B) is another alternative rule of the modulation method according to the present invention; The sixth picture is a frequency characteristic diagram of one code; The seventh figure is a synchronous pattern diagram of the modulation method according to the present invention; Figure 8 is a flow chart of a modulation method according to the present invention; Figure 9 is a configuration diagram of a modulation circuit according to the modulation method of the present invention; Figure 11 is a flow chart of a demodulation method according to the present invention; 11 is a separation rule diagram of a demodulation method according to the present invention; Figure 12 is a part of a demodulation variant of the demodulation variant according to the invention, -15-1262482; Figure 12 is another part of a demodulation table of the demodulation method according to the present invention; Figure 14 is a configuration diagram of a demodulation method according to the present invention; And the fifteenth diagram is a code conversion table of a conventional modulation method. (4) Embodiments In order to clarify the above and other objects of the present invention, feature, And the advantages, Embodiments of the present invention will be described in detail in conjunction with the accompanying drawings. The first to fourth figures are code conversion tables of the code modulation method according to the first embodiment of the present invention. In the first to fourth figures, 8-bit data characters from 〇〇 to FF are expressed in hexadecimal notation. And in conjunction with the corresponding code character of the 12-channel bit and the subsequent or subsequent pattern represented by S 0 to S 2 in each table, The above data characters, Code character, And the state of the connection is presented in the form of a table in common. From here, it can be understood that the code modulation system of the present invention is used to convert an 8-bit data character into a 12-bit channel bit, It is also used to achieve 8 to 12 modulation of the coding rate (2/3). especially, The three code conversion tables presented in each of the first to fourth figures respectively use the current type S 0 , S 1, S 2 ' should note that the code characters of the 12-channel bits in the code conversion table are in addition to "〇" and "1". Also includes the tag and, , #, , , mark, , *" is a interlocking bit used to chain two code characters. And when a leading bit of a subsequent code character is obtained, , 1 "and, 〇 〇, , It will be obtained separately, , Oh, , and 1", The tag "#" is a DSV control bit. It can be based on the _ 1 6 - 1262482 DSV obtained from the channel bit string generated by the chain of code characters. Acquired arbitrarily or selectively, , Oh, , And the three code conversion tables for the patterns S 0 to S 2 in the first to fourth figures are successively selected according to the next state in the code conversion table, a channel bit string obtained by generating a linkage by borrowing S code characters, Between the channel strings thus obtained, Continuous data", , Will not appear, And pointed out the information, , Oh, , The length of the operation of the number of I buys is always 1 〇 or less. therefore, The data "1" does not appear continuously in the channel bit string. And the length of the mark or space generated by the NRZI conversion of the recording channel bit string also always has a length of not less than 2 ( (the mark Τ represents the length of one channel bit), That is, it can be succinctly understood that the code conversion tables of the first to fourth figures obey the RLL (l, which has the maximum operation length of 10). L〇) rule, therefore, It can prevent the generation of marks or spaces smaller than 2Τ. Because it can cause difficulties in recording and detection, The above situation is even when the D S V control bit is obtained, , 〇 ” or, , 1, , One of them can also be maintained by using the code conversion tables of the first to fourth figures. Furthermore, the linkage rule presented in the fifth diagram (A) is used to chain or replace code characters. According to the law of linkage, A pattern such as "1010101010101" whose operation length 1 is repeated six or more times can be excluded from the channel bit string, When the channel bit string is governed by the NRZI conversion, The pattern of the operation length 1 is recorded with a mark or a space of the shortest operation length of 2 T. The number of consecutive repetitions of the operation length 1 is limited to a maximum of five times. It can be avoided that a low amplitude state occurs continuously or reproduces. The linkage rule presented is used to lock two consecutive code characters. And to define a code character by being different from the previous one in the bit sequence, To replace the rule of the code character corresponding to a predetermined one-bit string. -17- 1262482 Please refer to the fifth picture (A), The linkage rule is applied to the code characters obtained by the code conversion table after the chain bit is determined to be "1". In Figure 5 (A), Substituting the mark "X" previously displayed in the previous code character means that the corresponding bit will get "0". , , "1", , ’#”, And one of them, The bit position corresponding to "X" is kept constant before the replacement and thus does not change, A channel bit string that is replaced on the basis of the chain rule includes all patterns in which the length 1 of the chain of characters may appear six or more times in the chain of code characters. According to the law of chains, The channel bit string can be replaced by any other pattern that cannot be obtained from the code character in the code conversion table. The chain of code characters will be applied to the previous chain point first. The linkage rule of the fifth diagram (A) will be applied appropriately to the signature or rule number of each linkage point. 'Some code characters can be replaced twice to connect the previous codeword and subsequent or subsequent codewords. yuan. The channel bit string can be obtained by the code conversion table of the first to fourth figures and the linkage rule of the fifth figure (A). It has a 2/3 encoding rate and a minimum operating length of 1. The maximum operation length is 10, The number of repetitions of the operation length 1 of the channel bit string is limited to five times or less. When the channel bit string is governed by the NRZI conversion and is recorded as data, The situation will be satisfied so that the length of the mark and space is 2T or more and 丨丨T or less. And the number of consecutive repetitions of the mark and space of 2τ is limited to five times or less. In an area with 2 T consecutive signs and spaces, The amplitude of the reproduced signal is not obtained enough, And therefore the data will be detected incorrectly. By limiting the number of consecutive 2T patterns to five or less, It is possible to suppress the occurrence of a pattern that causes an error. A 18- 1262482 when the continuous generation of 2 T patterns is limited to five times or less, Even when the 2 图案 pattern is continuously produced, The length of the mark and space will be limited to i or less. In the P R M L detection, The entire continuous 2 T pattern is converted by 1 τ and is easy to guide: (Therefore, an error caused by the conversion of 1 ,, however, If the number of consecutive 2 T patterns is limited to five or fewer times, This effect of a 1 τ transition is suppressed by 12 or fewer channel bits. therefore, Even taking into account the range of codewords, The negative effects of 3-bits can also be effectively prevented. Secondly, the D S V control bits included in the code conversion table are discussed. In a signal string obtained by NRZI conversion, The DSV can be obtained by adding 1 (or -1) to the leading bit of the channel bit string. This will produce a positive or negative polarity. DSV is used to indicate the DC component of the code character. When the initial 値 is assumed to be 0 and therefore the absolute D V of the D S V obtained from the leading bit is close to 0, It can reduce the DC component. According to the code modulation method of the present invention, DS V control bit in the code character, , #, , The 値 can be obtained by referring to the code conversion table. And the D S V control bit in the code character, , #, , The decision to make the DSV calculated before the next D SV control bit of the channel bit string becomes close to 〇, The sixth graph shows a frequency characteristic of the signal obtained after NRZI conversion under DSV control, The horizontal coordinate represents the frequency after normalization of the channel clock frequency via the channel, The ordinate represents the power density of the frequency component, Please refer to the sixth picture. The amplitude component of the random data obtained by the above method indicates that the maximum frequency of the frequency is equal to about 1 通 of the channel clock frequency. Conversely, obviously, The amplitude component indicates A low amplitude at a frequency equal to or less than the channel clock frequency of 1 / 1 0, 0 0 0 of 1262482, The low amplitude is equal to or lower than the maximum 値20 dB or more, Equal to or less than 1/10 of the channel clock, The channel frequency of 000 corresponds to a servo control band. To control the position of an optical pickup, The amplitude intensity in the frequency band is reduced by 20 Db or more from the maximum ,, Thereby suppressing the harmful effects on a servo control signal, The advantage is that The accuracy of the position control remains. The present invention also ensures that the DSV control bit "〇" or "1" of the code conversion table of the first and fourth figures does not disturb the limitation on the number of consecutive 2T patterns and the operation length limit. And has nothing to do with the chain code characters before or after the code character. So when the DSV control bit appears, The length of the channel bit string before or after it does not need to be checked. And "0" or "1" can be arbitrarily selected as a DSV control bit. The configuration circuit is also extremely simple in structure. All of the above are based on the code conversion table of the first to fourth figures and the linkage rule of the fifth figure (A). however, obviously, The same advantage can be obtained by using a modulation table that modulates the correspondence between data characters and code characters. All the patterns that are replaced under the linkage rule of the fifth figure (A) do not contain six. Any pattern of one or more 2T continuous patterns, therefore, By detecting the number of consecutive 2 T patterns, a partial replacement can be ignored. For example, among the patterns included in the chain rule of Figure 5 (A), Only have "1010101010101, , A pattern in which the operation length i is repeated six or more times can be replaced. Furthermore, The configuration of the D S V control bit is also not limited to the example of the code conversion table only in the first to fourth figures. for example, The codeword element including the D S V control bit as a one-bit element is separated into having a d S V control bit, , 0, , Two types of code characters and code characters with DSV control bit "1", - 2 0 - 1262482 The separated one-character character can be combined with another code character. In addition to the separated codewords and the position of the D S V control bits being changed, The code conversion table obtained through the above operation has the same generation frequency of the D S V control bits, And thus having the same characteristics as the code conversion tables of the first to fourth figures. In the case of long channel bit strings, It is often the case that when the channel clock is in a chaotic state or an asynchronous state, the demodulation becomes erroneous. In order to avoid demodulation errors, A sync pattern is often placed in the channel bit string. therefore, Even when the replay is in sync, the sync job is in a messy state. Such a chaotic state can still be detected by detecting the next sync pattern. And the continuity of demodulation error can also be avoided. The seventh diagram is an example of a synchronization pattern or code (hereinafter abbreviated as SYNC code) applied to the code modulation method of the present invention. The sync pattern or the SYNC code is different from the pattern obtained by the interlocking rule of the fifth figure (A) and the code conversion tables of the first to fourth figures, This is because each SYNC code in the seventh figure includes a pattern of operation length 12 (represented by 12-operation-length) "10000000000001", This SYNC code consists of four SYNC codes or patterns SY0 to SY3 (corresponding to status information or states S0 to S2). As shown in the seventh figure, The same code or pattern is used for status information S 1 and S 2, Each SYNC code or pattern is selected based on the status information being placed. Among the code characters after the sync pattern is placed, Status information will be provided to S 1 or S 2, And therefore the code operation will continue, In this way, Even if the S YN C code is placed, 1-Operation - A pattern in which the length is continuously repeated six or more times does not occur in a manner in which the minimum operation length is maintained at 1. Although the code includes a pattern of 1 2_ -21 - 1262482 operation-length (operation length 12), The SYNC code will still be formed in a pattern not less than an arithmetic length of 11 (i.e., 11-operation-length) 5 because such a pattern does not appear in a normal code character. In the case of using a S YN C code or pattern, A linkage rule of the fifth graph (B) and the marker 10 can also be used for the chain code character. So that the S Y N C code does not exceed the maximum operation length of 10, in other words, The linkage rule of the fifth graph (A) cannot be applied to the linkage between the S YN C code and the code character. And therefore, The linkage rule should be used 10, As shown in the fifth figure (B), The law of linkage or the label 1 system includes a predetermined pattern SY3, It will be stated below. And the S Y 3 system is chained as a subsequent or current code character. Each SYNC code or pattern includes a DSV control bit. The DSV control bits in the code conversion table are only used for a part of the code characters. therefore, The D S V control bit does not appear in the way attached to the modulation data string. According to the code modulation method of the present invention, The DSV control bit is not determined or fixed until the next DSV control bit appears. The advantage is that By providing D S V control bits to each s YN C code, The D S V control bit can be determined in each period of the sync pattern. The four SYNC codes or patterns SY0 to SY3 are randomly selected and may be regularly selected. Used to determine an approximate location of the channel bit string for the detected S YN C code, however, If you do not need to confirm the location, The S yn C codes SY0 to SY3 will be randomly selected, Or only the sync pattern SY0 is used, 'again, The S YNC code or pattern is not limited to the pattern and has an arbitrary length. With a SYNC code or pattern, You can modify the SYNC code and status information. The status information is displayed in the code conversion table and is used after the -22 - 1262482 sync pattern. The eighth figure is a flow chart of the above code modulation method. At the beginning of the modulation, The information situation is initialized to s 1 or s 2, And D s V is initialized to 〇, The S YNC code or pattern is then placed in sequence with the sync pattern SY0 at the head of the information frame. SY1 SY2 And SY3, The information frame is obtained by separating data located in a constant byte (for example, 9 1 byte). In this case, The position after the start of the modulation corresponds to a position where the S YN C code or the pattern SYO is placed. The synchronization pattern SYO is selected corresponding to the status information (state) S1 or S2, After placing the sync pattern, The status information is updated to S 1 or S2. The sync pattern 尙 includes the DSV control bit after the sync pattern is placed. however, Before updating the status information, The sync pattern does not include the DSV control bits and therefore the bits are not yet determined. Subsequently, The data bits are successively extracted by the 8-bit until the position of the next sync pattern is placed. And the extracted data bits are converted into code characters by using a code conversion table. In addition, Status information is updated based on the code conversion table. Furthermore, After the replacement of the code character, Codewords are chained based on linkage rules. Since the code character after the synchronization pattern is placed should be interlocked with the previous synchronization pattern, Therefore, the latching rule of code characters will not be applied. When the code character obtained by using the code conversion table includes the DSV control bit, The old DSV control bit is determined based on the DSV. The DSV is the D S V calculated relative to the newly obtained channel bit string up to the DSV control bit. As mentioned earlier, The sync pattern is periodically placed and the code is also performed. Until the next DSV control bit appears, The DSV control bit is -23- 1262482 and will not be decided. however, At the end of the data, The last D S V control is determined based on the DSV calculated relative to the newly obtained track bit string up to the D SV control bit. And then the encoding will be completed. If the period of placing the sync pattern is determined to be about 1 〇 〇 byte, The frequency characteristics shown in the figure are not affected by the efficiency of the pattern, The code conversion table or the DSV control bit indicated in the synchronization pattern can be used to control the polarity of the recorded data. The sync pattern recorded on the recording light can be limited by using the DSV control bit at the determined position. The ninth diagram is a tuning used in the code modulation method according to the present invention, The modulation circuit includes a code conversion table reference circuit 1. a state 2 a multiplexer 3, And a synchronization pattern is placed in the circuit 4, The code conversion reference circuit 1 includes code conversion tables 1〇1 of the first to fourth figures, The code conversion reference circuit 1 receives a data string B (t ) of each 8-bit, And the status information s (t) transmitted by the state register 2, The code conversion table entry 1 is based on the status information S(t), Referring to the code conversion table i of the first to fourth figures, a code character x(t) having 12 channel bits is output, Secondly, The code conversion test circuit 1 outputs the next state information to the processor 3' according to the code conversion table 1 〇, and the self-synchronization pattern insertion circuit 4 receives the next message, Select it 'and output the next status information s(t+1) to indicate the status to status register 2, The status register 2 corresponds to the next string B(t) and the output status information s(t) is placed into the circuit 4 in a step pattern to the code conversion table reference circuit 1. As described above, the code conversion table reference circuit 1 has a plurality of codes, a 24-bit configuration, The sixth part of the reduction of the pre-disc in the substation, the temporary storage, the change of the table, the change of the form, the self-formed test 01, Parametric multiplexed state of the next data and the same conversion 1262482 Table 1 〇 1, Converting the code conversion table 1 01 based on the state information s(t) held by the state register 2 And outputting the code character S(t) corresponding to the given data character and status information S (t+ 1 ), The status information S(t+1) indicates the next code conversion table to be referred to, Furthermore, a connection circuit, That is, A chain circuit 5 is connected to the modulation circuit of the ninth diagram at the output of the code conversion table reference circuit 1 and the synchronization pattern insertion circuit 4, The chain circuit 5 is also connected to a DSV control circuit 6, A channel bit string is output from the DSV control circuit 6. The sync pattern placing circuit 4 outputs a sync pattern based on the state information S (t) held by the state register 2 for a predetermined period of time to be placed in the channel bit string. And output this status information, The status information output from the code conversion table reference circuit 1 and the status information output from the self-synchronization pattern insertion circuit 4 are transmitted to the status register 2 via the multiplexer 3 as described above. The operation of the state register 2 causes the next state information 3 (1+1) to be updated 'and is held each time the code character is output from the code conversion table reference circuit 1 and is placed in the circuit 4 each time the self-synchronization pattern is placed. Hold when the sync pattern is output. The operation of the chain circuit 5 is for connecting or interlocking the code character output from the code conversion table reference circuit 1 and the synchronization pattern outputted by the self-synchronization pattern insertion circuit 4 by generating a chain code character. In order to connect or chain these code characters, The chain circuit 5 will decide to include in the last code character to, , Oh, , or, , Wide one or a combination of bits, And check the linkage rule of the fifth figure (Α) by synchronizing the pattern' when the linkage rule corresponds to the synchronization pattern, The code character will be replaced and the resulting data will be output as sequence data to indicate the channel bit - 25 - 1262482. The D S V control circuit 6 reacts to the sequence data transmitted by the chain circuit 5, And extracting information showing the D S V control bit, The D S V control bit is included in the sequence data outputted from the interlock circuit 5, Secondly, The D S V control circuit 6 determines the DSV control bit and outputs it as a channel bit string. Bringing D S V closer to 〇, Since the modulation circuit has the above structure, Obtain a channel bit string for high-density recording. At the same time, there will be no 1-operation-length repeating pattern generation of six or more times. This channel bit string makes the low frequency component small enough. Described next is a method for demodulating a channel bit string obtained by the code modulation method and the code modulation circuit according to the present invention. The demodulation method can be clearly stated by the flowchart of the tenth figure. First of all, Due to the decision to reproduce the signal, The sync pattern is extracted from the channel bit string, The range of codewords is clearly defined in each channel of 12 channels based on the extracted sync pattern. Therefore, the detection of each pattern can be performed. Each of these patterns is replaced by a range obtained from the channel bit string by the use of the linkage rule, Also the previous code character or pattern that was returned before the replacement, therefore, The pattern is separated into code characters. Using the linkage rule of Figure 5 (A) helps the detection of patterns in anti-conversion and judgment, Or to help the decision of the pattern in terms of segmentation, This decision can be understood by replacing the code characters with the three separation rules shown in Figure 11. then, The use of the codeword obtained by the above method and the demodulation result obtained by referring to the demodulation variable table, You can get 8-bit data characters. In the eleventh figure, a reference mark included in the previous pattern before the replacement, , X" means that the bit can take -26- 1262482 and get one of "1" or "0". Before the replacement, The bit corresponding to the reference mark "x" after the replacement will remain unchanged. The twelfth and thirteenth figures are demodulation tables used to obtain 8-bit data characters from codewords of 12-channel bits, Please refer to the twelfth and thirteenth figures. The three demodulation tables T0 to T2 are as shown in the figure. Consider demodulating variable target code characters, a subsequent code character after the demodulation variable target code character, And a sync pattern, Select one of the demodulation tables T0 to T2 used, When the demodulation variable target character is followed by the next codeword, the bit "1" is used as a starting point. Or when the next sync pattern indicates SY0 to SY2 of state 0, That is, using the demodulation table T0, When the demodulation variable target code character is followed by the next code character, "〇〇〇〇" is used as the starting point. Or when the next sync pattern indicates S Y3 of state 0, That is, using the demodulation table T1, When the demodulation becomes the target codeword, the next codeword is "01", "001", Or "0 0 0 1 " as the start, Or when the next sync pattern indicates SY0 to SY3 of states 1 and 2, That is, the demodulation table T2 is used. Corresponding to the demodulation variable target code character, The 8-bit data character is represented by a 16-bit representation. When the synchronization pattern exists in the form of demodulating the variable target code character, That is, the demodulation variable table T0 is selected. And referring to the synchronization pattern generated by the state information S 0 when the demodulation table T2 is selected, And referring to the synchronization pattern generated corresponding to the status information S 1 or S2, therefore, The data characters are generated in the manner described above. In the demodulation table, The code character of the 1 2-bit channel bit string corresponds to the 8-bit code character. therefore, The advantage is that no errors will spread or spread in the above manner. This is relative to the variable length conversion table - 27 - 1262482 using a generated VARIABLE BLOCK CODE, This is to suppress any propagation of errors caused by the limitation on the number of repetitions of the 2 T pattern, And errors that reduce data rates are very effective. In addition, It should be noted that the pattern of the I 2 channel bits not displayed in the table in the form of code characters, And marking the specified pattern in the rank of the data character, These patterns are not produced according to the demodulation method of the present invention. When these patterns are detected, The program that cannot be demodulated will proceed. Generating an optical data character also produces information showing a data character containing an error. Incidentally, Determining the PRML detection of the reproduced signal makes it possible to exclude most of the patterns determined by the channel bit strings not displayed in the demodulation table. Therefore, Decisions and demodulation errors can be further reduced. Next, the configuration of the demodulation circuit is explained in conjunction with the fourteenth figure. The channel bit string is placed in a sync pattern detecting circuit 7, The sync pattern detecting circuit 7 outputs the channel bit string and information indicating the position of the range of the code character by referring to the position of the detected sync pattern. therefore, A separating and replacing circuit 8 detects and replaces the pattern conforming to the separation rule of Fig. 11, And further separating the channel bit string into code characters and outputting them, A demodulation variable table reference circuit 9 converts the code character string obtained as described above into a data element having 8 bits and outputs it. In order to demodulate a code character having 12 channel bits, The demodulation variable table reference circuit 9 refers to subsequent code characters and synchronization patterns, Select a demodulation variable table 9 0 1. And extracting the data characters corresponding to the code characters, The output of the modulation table reference circuit 9 outputs an unfeasibility of demodulation with respect to the code character. The code character does not appear in the demodulation table. In the demodulation - 28 - 1262482 change, The code character unit of 1 2 channel bits and the code characters before/after the modulation are referred to. therefore, It can prevent the increase of demodulation error. According to the channel recording medium obtained by the code modulation method of the present invention, By the NRZI number of the channel bit string, And the signal is recorded corresponding to a concave length (PIT INTERVAL). This type of recording enables recording at a high recording density. Channel clocking 'and can reduce detection errors, The concave surface does not include a component of the servo band. And so the tracking characteristics used for the detection operation will not deteriorate. Hereinafter, in the optical recording medium recording medium of the present invention, The pattern of the control length and the concave interval received by the channel bit string is recorded on the optical recording medium optical recording medium. In addition to the sync pattern, A pattern having a minimum operation length 値1 and a maximum operation prohibiting the operation length 1 from being repeated six or more times is placed in a predetermined period of time. The way to record information in the media is, The component to be read from the concave surface is 20 dB below the maximum 该 of the frequency component. 1 / 1 0, 000) or less (when the frequency is one channel, the frequency of the pulse, even if the invention is based on the preferred embodiment above, the person skilled in the art, The invention is still not limited to the method of use, Especially, According to the appended application -19 of the present invention, an optical conversion of a bit string which is obtained by solving such a circuit structure can obtain a letter LENGTH) and a concave mode is a remake which can also be stably extracted. Optical reading of the signal measurement signal. In the light of the invention, And in a concave body, Secondly, In the track, the string is based on the length 値1 0, as well as : And formed, Needless to say, again, The frequency of the signal recorded in the optical is more (when the frequency is the rate). Give instructions, However, these embodiments and the 1262482 equivalent variations and modifications made to the scope of the patent, All are covered by the scope of the invention. Component Symbol Description 1 Code Conversion Table Reference Circuit 2 Status Register 3 Multiplexer 4 Synchronous Pattern Placement Circuit 5 Chain Circuit 6 D S V Control Circuit
7 同步圖案抽取電路 8 分離及替換電路 9 解調變表參考電路 10 1 碼轉換表 901 解調變表7 Synchronous pattern extraction circuit 8 Separation and replacement circuit 9 Demodulation variable table reference circuit 10 1 code conversion table 901 Demodulation variable table
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