200425070 玖、發明說明： (一） 發明所屬之技術領域 本發明係關於一種碼調變方法及裝置、解調變方法及 裝置、以及資訊記錄媒體，係用以記錄或重製數位資料於 一記錄媒體（例如，光碟）之上。 (二） 先前技術 關於記錄資料於一記錄媒體（例如，光碟）之上，資料 調變係以與該記錄媒體相匹配的方式實行，而在資料於該 記錄媒體上的記錄、或是資料自該記錄媒體上的重製方面， 所記錄或重製的信號或碼所包含的直流成份容易導致一光 碟裝置的一伺服控制信號產生波動（fluctuation)、或是 導致產生抖動（JITTER)，因此，如果可能的話，調變信號 或S周變碼中最好不要含有直流成份。 所謂的數位多功能光碟（DVD)係使用8至16(8/16)調 變’其係根據運算長度限制（RLL，RUN LENGTH LIMITING)(2，10)法則將—8位元的資料位元串調變爲一 16 位元的資料位元串，其中須注意的是，RLL(2，1〇)係將一資 料位元串轉換成一通道位元串，該通道位元串係包括介於 鄰接的”1”位元之間、不小於2且不大於”1〇”的，，〇，，位元， 特別是’ RLL(2，l〇)法則中數字，，2”代表介於鄰接的”〗，，位元 之間、連續的”0，，位元的最小數目（亦指一最小運算長度）， 另一方面’數字” 1 0，，代表介於鄰接的”丨，，位元之間、連續 的”〇”位元的最大數目（亦指一最大運算長度），更進一步來 說’ 8 / 1 6調變可藉由從以數位總和値（D s v，D z G i τ a l s U Μ 200425070 VALUE)爲基礎所構成的複數個表中選取一碼字元（CODE WORD)、而有助於抑制該直流成份，DSV定義成在不歸零 倒置（NRZI)轉換之後與通道位元串連接在一起，並且代 表”+Γ’的一總和値，其中該總和値係成功地分別將+1和-1 加至自該通道位元串的一領導位元（LEADING BIT)所產生 的”1”和”0”所獲得，DSV係用以指出包含在該通道位元串 中的直流成份的程度，在8/1 6調變中，一碼字元自複數個 事先準備好的表中被選出，使得DSV變爲最小、而該通道 位元串中的直流成份所造成的波動亦因此獲得抑制。 如上所述，在8/1 6調變中，資料位元串係分成以位元 爲單位的一個個資料字元（DATA WORD)，再被轉換成一 16 通道位元的碼字元，資料位元相對於通道位元的比率所顯 示的一編碼率等於1 /2，高編碼率暗示有一段長時間可用於 偵測每個通道位元，其結果是，編碼率是越高越好。 習知技術中另一種碼係根據RLL法則針對光碟或磁碟 所定義’其具有高於8/1 6調變的2/3的編碼率，即係藉由 2/3調變所獲得，更特別的是，在2/3調變中，2資料位元 在RLL(1，7)法則下被調變成3通道位元，其中，，〇，，的運算長 度等於1或更多以及7或更少，換句話說，，，0，，的最小運算 長度是”1” ’ 的最大運算長度是，，7”。第十五圖係爲傳統 RLL(1，7)中用於2/3調變的一碼轉換表，在第十五圖的碼 轉換表中’藉由將2資料位元當作一調變目標、連同一後 繼的或是後續的資料位元以及前導通道位元的一終端位 元，可獲得3通道位元，在第十五圖中，參考標記，，χ”指出 一 8- 200425070 在後續資料位元以及前導通道位元中也許會有” 0，，位元或 是”1”位元，在以RLL(1，7)爲基礎的2/3調變中，資料位元 串轉換成包含” 0 ”位元的通道位元串，其中” 0 ”位元係介於 鄰接的”1”位元之間、不小於1亦不大於7，因此，在NRZI 記錄中，記號或空格被限制於2T或2T以上以及8T或8T 以下（其中參考標記T代表一通道位元長度），日本公開特 許第1 0-3 40 5 43號（專利文件1)以及第2000-3 3 26 1 3號（專利 文件2)提供一種在上述的RLL(1，7)法則之下將資料位元串 編碼成爲通道位元串的方法。 其中已被指出的是，在記錄於一高密度的光碟的一重 製信號當中，由於記號和空格長度簡短圖案所造成的信號 振幅減小，使得通道位元的偵測變得困難，偵測窗的寬度 在8/16調變中被資料位元長度標準化成和1/2 —樣狹窄， 卻在（1，7)調變中和2/3 —樣寬廣，然而，最短的記號長度 或是空格長度在8/16調變中和3/2 —樣長’卻在（1，7)調變 中和4/3 —樣短，這樣一種在最短記號長度或是空格長度 方面的減少，對於藉由最短記號或空格而記錄於一記錄部 份以及自該記錄部份而重製的重製信號來說’所帶來的是 振幅方面的減少，當一重製信號藉由一比較器的使用而被 轉換成二進位的資料，則振幅的減少容易導致因雜訊所產 生的抖動的增加。上述由於最小運算長度的連續發生所產 生的問題已於日本公開特許第η-346 1 54號中被指出（專利 文件3)。 然而，不論最短記號長度或是空格長度哪一方被縮短’ —9 一 200425070 振幅上的減少皆可藉由使用局部響應最大近似 (PRML，PARTIAL RESPONSE MAXIMUM LIKELIHOOD)偵測 方法處理該重製信號而獲得補償，在PRML偵測中，一重 製波形先與通道位元串所具有的複數個候選波形的其中之 一相比較，再從通道位元串中選取最有可能成爲重製波形 的候選波形。根據這種偵測，即使當候選波形的一部份具 有信號振幅減小以及其餘的候選波形的信號振幅增大，偵 測錯誤仍會減少，在這個構想之下，前述二種不同的候選 波形便可以彼此區別出來。 習知技術中，應用於根據RLL(1，7)法則所定義的2/3 調變的調變方法具有一個優秀的特徵，即爲編碼率和2/3 一樣高以及偵測窗寬度可更爲寬廣，然而，對於RLL(1，7) 調變之下的通道位元串來說，” 1”的運算長度似乎具有較高 的可能性，並且2T圖案的最短圖案亦因此容易連續產生（其 中參考標記T代表通道位元長度），上述的最短圖案係對應 於NRZI記錄中的最短記號或是最短空格，在PRML偵測 中，偵測錯誤便因此常產生於包括2T的連續圖案的重製信 號之中，藉由使用PRML偵測方法，可以淸楚分辨具有2T 圖案的重製波形以及具有3T或更多圖案的重製波形之間的 不同，然而，在具有2T的連續圖案的部份當中，卻很難僅 藉由如前所述之重製波形而明確指出通道位元串的相位。 在PRML偵測中，藉由參考位於每個連續圖案之前或 之後的重製波形所獲得的資訊，可以明確指出位於具有2T 的連續圖案之部份的通道位元串，重製波形中的雜訊混合 -10- 200425070 容易引起一偵測錯誤，該偵測錯誤係發生於當進行偵測於 欲以一 2T之較長的連續部份中的τ的一通道位元長度、更 換2T的一整個連續圖案之時，在這種情形之下，一偵測錯 誤便會佈滿藉由一通道位元進行更換以及持續複數個位元 組的一整個偵測範圍之中。 在具有2T之長連續圖案（也就是最小運算長度爲1)的 重製信號之中，一較低的信號振幅狀態會持續一段長時間， 這使得欲自重製信號中抽取一通道時脈變得困難，鑑於通 道時脈抽取的不穩定使得2T圖案的連續性不再受到歡迎， 專利文件1和2皆揭露了 RLL(1，7)法則之下的編碼方法， 更進一步來說，專利文件1和2更揭露了在RLL法則之下 冗位（REDUNDANCY)的減少以及DSV獲得控制的一種技 術，然而，對於最小運算長度1的連續狀態所引起的問題 以及其解決方法卻毫無著墨。其次，專利文件3揭露了藉 由使用具有一轉換區（SECTION)的一轉換表、而將最小運 算長度的連續狀態限制於一預先決定的次數數目’然而’ 專利文件3卻只使用一變數長度碼、而從不考慮任何的編 碼率。 除此之外，自光碟重製藉由使用〇,7)調變而被記錄的 信號亦是不利的，其中對於㈠，7)調變來說、一低頻成份尙 包括於該重製信號之中’尤有甚者’重製信號中的低頻成 份還會爲了控制一光碟裝置而改變一伺服控制信號。 (三）發明內容 因此，本發明之一目的在於提供一碼調變方法和一碼 - 1 1 - 200425070 調變裝置’用以獲得具有與（1，7)調變相同的一編碼率的一 調變碼，該方法可避免或禁止一種圖案的存在，該圖案容 易導致一通道位元串中一重製信號之一偵測錯誤的產生， 並且適用於高密度記錄，同時直流成份也會減少。 本發明之另一目的在於提供一種解調變方法以及解調 變裝置’用以讀取前述之碼以及一資訊記錄媒體，該資訊 記錄媒體係藉由該碼之使用以記錄資料，並可預防或是禁 止偵測錯誤的產生。 爲了解決上述問題，根據本發明所述之碼調變方法和 碼調變裝置，一運算長度具有與與（1，7)調變相同的2/3的 編碼率、並且指出夾在通道位元串的”1”位元之間的，，〇，，位 元的數目，一資料位元串被轉換成通道位元串使得運算長 度具有一最小値1以及一最大値1 0，此外，在轉換任何資 料位元串時，通道位元串並不包括運算長度1連續地重覆 六次或更多次、如”1010101010101”的一圖案。 再者，通道位元串具有一 DSV控制位元用以根據一 DSV 而選取一 ”〇”位元或”1”位元，藉由根據DSV以選取DSV控 制位元的一値以及藉由使用用於資料位元串的隨機資料， 一信號的一頻率成份可自通道位元串的NRZI轉換而獲得， 並且自該頻率成份的一最大値減少20dB、更多（當頻率爲 1 /1 0,00 0)或是更少（當頻率爲一通道時脈頻率）。 此外，根據本發明所述之解調變方法，包括下列步驟： 針對每個碼字元分離該通道位元串之前，偵測於一替換法 則之下被替換的一圖案，其中該替換法則係使用於連續的 - 1 2 - 200425070 該碼字元；在替換之前藉由前一圖案替換被偵測的該圖案； 以及將該圖案分離成包含1 2位元的該通道位元串的碼字元； 以複數個儲存包含具有8位元的一資料位元串的一資料字 元的解調變表，並對應於包含具有1 2位元的該通道位元串 的該碼字元，選取該解調變表用以解調變被分離的該碼字 元，該碼字元係以顯示具有1 2通道位元的後續碼字元的一 資訊爲基礎；以及藉由使用指出該碼字元具有12通道位元 的該資訊以及使用被選取的該解調變表，而獲得包含8位 元的該資料位元串的該資料字元。 此外，根據本發明所述之解調變裝置，包括：複數個 解調變表，用以儲存包含8位元的一資料位元串的一資料 字元（DATA WORD)，並對應於包含12位元的該通道位元 串的該碼字元；自該通道位元串偵測被置入的一同步圖案 的裝置；針對每個碼字元分離該通道位元串之前偵測於一 替換法則之下被替換的一圖案、在替換之前藉由前一圖案 替換被偵測的該圖案、以及將前一個圖案分離成包含1 2位 元的該通道位元串的碼字元的裝置；選取該解調變表，用 以解調變被分離的該碼字元，其中該碼字元係以指出12通 道位元的該後續碼字元的一資訊爲基礎；以及藉由使用顯 示1 2通道位元的該碼字元的該資訊以及被選取的該解調變 表、而獲得包含具有8位元的該資料位元串之該資料字元 的裝置。 此外，根據本發明所述之資訊記錄媒體，係用以記錄 藉由一通道位元串之NRZI轉換所獲得、以及製作成對應於 200425070 一凹面長度（PIT LENGTH)和一凹面間隔（PIT INTERVAL)的 一資訊，在該記錄媒體中，該資訊係被記錄使得該通道位 元串中的一運算長度具有一最小値1以及一最大値1〇，除 了於一預先決定的期間置入的一同步圖案之外，使得該運 算長度1連續重覆六次或更多次的一圖案的出現係於該通 道位元串中被禁止，一信號的一頻率成份，該信號係自一 凹面（PIT)而被記錄，該凹面具有一功率密度，其中該功率 密度係自該頻率成份的一最大値減少20dB、更多（當頻率爲 1/10,000)或是更少（當頻率爲一通道時脈頻率）。 根據本發明，提供一種碼調變方法以及碼調變裝置， 用以獲得具有等於（1，7 )調變的一*編碼率的一'調變碼、防止 容易產生通道位元串中一重製信號的一偵測錯誤之圖案的 發生、以及適用於具有低直流成份高密度記錄，此外，本 發明之解調變方法和解調變裝置係用以讀取上述碼和一資 訊記錄媒體，該資訊記錄媒體係藉由使用該碼而記錄資料 並且防止偵測錯誤的發生，特別是，本發明之通道位元串 具有一 2/3編碼率、一運算長度1的最小値、一最大値1〇、 以及運算長度1之不多於五次的重覆次數，再者，通道位 元串具有一足夠低的頻率成份、並且適用於高密度記錄， 考慮到碼字元的範圍時，其有利之處在於，可有效防止對 .於三個位元組的影響，更進一步來說，編碼率係爲2/3，且 振幅長度係低於一最大値20dB (當頻率爲1/1 0,000)或是更 少（當頻率爲一通道時脈頻率），相反的，在解調變之中， 資料係基於1 2通道位元的碼字元單位而處理，再者，在其 -1 4 一 200425070 之前/之後的碼字元亦會被參考並且可淸楚了解不會產生偵 測錯誤的電路結構，此外，其有利之處在於，即使在高記 錄密度時通道時脈亦可被穩定地抽取，且不會產生偵測錯 誤。 (五）圖式簡單說明 第一圖係根據本發明的調變方法的一碼轉換表的一部 份； 第二圖係根據本發明的調變方法的該碼轉換表的另一 部份； 弟二圖係根據本發明的調變方法的該碼轉換表的另一 部份； 第四圖係根據本發明的調變方法的該碼轉換表的另一 部份； 第五圖（A)係根據本發明的調變方法的一替換法則圖； 第五圖（B)係根據本發明的調變方法的另一替換法則 圖； 第六圖係爲一碼的一頻率特性圖； 第七圖係根據本發明的調變方法的一同步圖案圖； 第八圖係根據本發明的調變方法的一流程圖； 第九圖係根據本發明的調變方法的一調變電路之配置 圖； 第十圖係根據本發明的解調變方法的一流程圖； 第十一圖係根據本發明的解調變方法的一分離法則圖； 第十二圖係根據本發明的解調變方法的一解調變表的 一 1 5 - 200425070 一部份； 第十三圖係根據本發明的解調變方法的一解調變表的 另一部份； 第十四圖係根據本發明的解調變方法的一配置圖；以 及 第十五圖係一習知的調變方法的一碼轉換表。 (四）實施方式 爲了淸楚闡明本發明上述及其他的目的、特徵、以及 優點，將配合所附圖示詳細描述本發明實施例。 第一圖至第四圖係根據本發明第一實施例之碼調變方 法的碼轉換表。在第一圖至第四圖中，8位元的資料字元 元〇〇至FF係以十六進位的表示法表示，並配合1 2通道位 元的對應碼字元以及以S 0至S 2所表示的接續或後續的型 態，在每個表中，上述的資料字元、碼字元、以及接續的 狀態皆是共同地以表的形式呈現，從這裡可以淸楚了解本 發明之碼調變係用以將8位元的資料字元調變成1 2位元的 通道位元、亦係用以實現編碼率（2 / 3 )的8至1 2調變。 特別是，呈現於第一圖至第四圖中每一個的三個碼轉 換表係分別地使用現今的型態SO、S 1、S2，需要注意的是 碼轉換表中1 2通道位元的碼字元除了，，〇，，和，，1，，之外，還包 括了標記和”#” ’標記是用以連鎖二個碼字元的一連 鎖位元，並且當一後續碼字元的一領導位元取得” 1”和” 0 ” 時其會分別取得”0”和”1”， 標記”#”是一 DSV控制位元， 其可根據因碼字元之連鎖所產生的通道位元串所得到的 一 1 6- 200425070 DSV之値，隨意地或選擇性地取得”〇”和”1 ”。 第一圖至第四圖中關於型態S 0至S 2的三個碼轉換表 係根據碼轉換表中下一個狀態而相繼地被選取，以產生藉 由碼字元得連鎖而獲得的通道位元串，在由此而獲得的通 道位元串之間，連續資料” 1”不會出現，且指出資料”〇”的 連續出現數目的運算長度亦總是保持爲1 0或更少，因此， 資料” 1 ”在通道位元串中不會連續出現，且記錄通道位元串 的NRZI轉換所產生的記號或空格長度亦總是具有不小於2T 的一長度（標記T代表一通道位元長度），也就是可以令人 淸楚了解，第一圖至第四圖的碼轉換表遵守具有最大運算 長度10的RLL(1，10)法則，因此，可以防止小於2T的記號 或是空格的產生，因爲其會造成記錄和偵測的困難，上述 的狀況即使當DSV控制位元取得”0”或”1”其中之一時亦可 藉由使用第一圖至第四圖的碼轉換表而保持下去。 再者，第五圖（A)所呈現的連鎖法則係用於連鎖或替換 碼字元，根據該連鎖法則，可以從通道位元串中排除諸 如”1010101010101”等運算長度1重覆六次或更多次的一圖 案，當通道位元串受到NRZI轉換之管轄時，運算長度1 的圖案係以2T的最短運算長度的一記號或一空格記錄，運 算長度1的連續重覆次數係限制於最多五次，可以避免一 低振幅狀態發生連續或重製，所呈現的連鎖法則係用以連 鎖二個連續的碼字元，以及用以定義藉由在位元序列中不 同於前一個的一碼字元、以替換對應於一預先決定的一位 元串的碼字元之法則。 -17 - 200425070 請參閱第五圖（A)，其連鎖法則係應用於連鎖位元，，*，, 確定爲”〇”或”1”之後藉由碼轉換表所獲得的碼字元，在第 五圖（A)中，替換之前顯示於前一個碼字元的標記，，χ”代表 了對應於的位元會取得”0”、，，1，，、，，#，，、以及，，*，，的其中 之一，對應於”Χ”的位元位置在替換之前被保持爲一定値且 因此而不會改變，以連鎖法則爲基礎而替換的通道位元串 包括在連鎖的碼字元之中運算長度1可能出現六次或更多 次的重覆次數的所有圖案，根據連鎖法則，通道位元串可 以被無法自碼轉換表中的碼字元所獲得的任何其他圖案所 替換，碼字元的連鎖會先應用於前一個連鎖點，第五圖（Α) 的連鎖法則將被適當地應用於每個連鎖點的標誌或是法則 號碼，某些碼字元可被替換二次以連接前一個碼字元以及 後續或接續的碼字元。 藉由第一圖至第四圖之碼轉換表以及第五圖（Α)之連鎖 法則可以獲得通道位元串，其具有2/3的編碼率且最小運 算長度爲1、最大運算長度爲1〇，通道位元串的運算長度 1的重覆次數被限制於五次或更少，當通道位元串受到NRZI 轉換所管轄並且被記錄成資料時，情況被會被滿足使得記 號和空格長度係爲2Τ或更多以及1 1Τ或更少，並且2Τ的 記號和空格的連續重覆次數係被限制於五次或更少，在具 有2Τ的連續記號和空格的一區域中，重製信號的振幅不會 足夠地被獲得、且因此資料會被錯誤地偵測，藉由限制2Τ 圖案的連續次數至五次或是更少，可以抑制造成錯誤產生 的圖案的發生。 -18 - 200425070 當2T圖案的連續產生被限制於五次或更少，即使當2Τ 圖案連續產生，記號和空格長度業會被限制在1 0Τ或是更 少，在PRML偵測中，整個連續的2Τ圖案被1Τ所轉換並 且容易導致因此1 Τ轉換所造成的一錯誤，然而，如果連續 2Τ圖案的數目被限制在五次或更少次，這種由1Τ轉換所 產生的影響會被1 2或更少的通道位元所抑制，因此，即使 考慮到碼字元的範圍，3位元組的負面影響亦可有效地被 防止。200425070 (1) Description of the invention: (1) The technical field to which the invention belongs The present invention relates to a code modulation method and device, a demodulation method and device, and an information recording medium, and is used to record or reproduce digital data in a record Media (for example, discs). (2) In the prior art, data is recorded on a recording medium (for example, an optical disc). Data modulation is performed in a manner that matches the recording medium, and the recording of the data on the recording medium or the data from Regarding the reproduction on the recording medium, the DC component contained in the recorded or reproduced signal or code is likely to cause fluctuations in a servo control signal of an optical disc device, or cause jitter (JITTER). Therefore, If possible, it is best not to include DC components in the modulation signal or S-cycle code. The so-called Digital Versatile Disc (DVD) uses 8 to 16 (8/16) modulation. 'It is based on the calculation length limit (RLL, RUN LENGTH LIMITING) (2, 10). The string becomes a 16-bit data bit string. It should be noted that RLL (2,10) converts a data bit string into a channel bit string. The channel bit string includes Between the adjacent "1" bits, not less than 2 and not more than "1〇", 0 ,, bits, especially the numbers in the 'LLL (2, 10) rule, "2" represents between adjacent "", Between the bits, consecutive "0", the minimum number of bits (also referred to as a minimum operation length), on the other hand, the "number" 1 0, which represents the adjacent "丨," bits The maximum number of consecutive "0" bits (also referred to as a maximum operation length) between elements, and more specifically, the '8/16 modulation can be adjusted by adding the digital sum 値 (D sv, D z G i τ als U M 200425070 VALUE) is based on selecting a code word (CODE WORD) from a plurality of tables formed to help suppress the DC component. DSV is defined as It is connected to the channel bit string after non-return-to-zero inversion (NRZI) conversion and represents a sum 値 of "+ Γ ', wherein the sum 値 successfully adds +1 and -1 to the channel bits respectively. The "1" and "0" generated by a leading bit of a metastring are obtained. DSV is used to indicate the degree of the DC component contained in the bit string of the channel. In this case, a code character is selected from a plurality of tables prepared in advance, so that the DSV becomes the smallest, and the fluctuation caused by the DC component in the channel bit string is also suppressed. As mentioned above, in the 8/16 modulation, the data bit string is divided into one data word (DATA WORD) in bit units, and then converted into a 16-channel bit code character. The ratio of the element to the channel bit shows an encoding rate equal to 1/2. A high encoding rate implies that there is a long time that can be used to detect each channel bit. As a result, the higher the encoding rate, the better. Another code in the conventional technology is defined according to the RLL rule for optical discs or magnetic discs, which has a coding rate of 2/3 that is higher than 8/1 6 modulation, that is, obtained by 2/3 modulation, more In particular, in the 2/3 modulation, the 2 data bits are adjusted to 3 channel bits under the RLL (1, 7) rule, where the operation length of 0, is equal to 1 or more and 7 or Even less, in other words, the minimum operation length of "0" is "1" and the maximum operation length is "7". The fifteenth figure is used for 2/3 in traditional RLL (1,7) A code conversion table of modulation, in the code conversion table of FIG. 15 'by using 2 data bits as a modulation target, connected to the same subsequent or subsequent data bit and the leading channel bit One terminal bit can obtain 3 channel bits. In the fifteenth figure, the reference mark, "χ" indicates that 8-200425070 may have "0", bits in subsequent data bits and leading channel bits. Or "1" bit. In 2/3 modulation based on RLL (1, 7), the data bit string is converted into a channel bit string containing "0" bits, where "0" Bits are between adjacent "1" bits, not less than 1 and not more than 7, so in NRZI records, marks or spaces are restricted to 2T or more than 2T and 8T or less than 8T (where the reference mark T (Represents the bit length of a channel), Japanese Public License No. 1 0-3 40 5 43 (Patent Document 1) and 2000-3 3 26 1 3 (Patent Document 2) provide an RLL (1, 7 ) Method of encoding a data bit string into a channel bit string under the rule of law. Among them, it has been pointed out that in a reproduced signal recorded on a high-density optical disc, a signal caused by a short pattern of marks and spaces The amplitude is reduced, which makes it difficult to detect the channel bits. The width of the detection window is normalized to 1/2 by the data bit length in the 8/16 modulation, but narrow in the (1, 7) modulation. Change in neutral 2/3 —like wide, however, the shortest mark length or space length is in the 8/16 modulation and 3/2 —like length 'is in the (1, 7) modulation and 4/3 — Such as short, such a reduction in the length of the shortest mark or space, for the shortest mark or space What is recorded in a recording portion and a reproduction signal reproduced from the recording portion is a reduction in amplitude. When a reproduction signal is converted into a binary by the use of a comparator, Data, the decrease in amplitude can easily lead to an increase in jitter due to noise. The above-mentioned problems caused by the continuous occurrence of the minimum operation length have been pointed out in Japanese Patent Publication No. η-346 1 54 (Patent Document 3) However, regardless of whether the shortest mark length or space length is shortened. — 9-200425070 The reduction in amplitude can be processed by using the local response maximum approximation (PRML, PARTIAL RESPONSE MAXIMUM LIKELIHOOD) detection method to process the reproduced signal To obtain compensation, in PRML detection, a reproduced waveform is first compared with one of a plurality of candidate waveforms possessed by the channel bit string, and then a candidate waveform most likely to be a reproduced waveform is selected from the channel bit string. . According to this detection, even when a part of the candidate waveform has a decrease in signal amplitude and the signal amplitude of the remaining candidate waveforms increases, detection errors will still decrease. Under this concept, the aforementioned two different candidate waveforms They can be distinguished from each other. In the conventional technology, the modulation method applied to the 2/3 modulation defined by the RLL (1, 7) rule has an excellent feature, that is, the coding rate is as high as 2/3 and the detection window width can be more It is broad. However, for channel bit strings under RLL (1,7) modulation, the calculation length of "1" seems to have a high possibility, and the shortest pattern of 2T pattern is therefore easy to generate continuously ( The reference mark T represents the channel bit length.) The shortest pattern mentioned above corresponds to the shortest mark or shortest space in the NRZI record. Therefore, in PRML detection, detection errors are often generated by repeated patterns including 2T. Among the control signals, by using the PRML detection method, the difference between a reproduced waveform with a 2T pattern and a reproduced waveform with a 3T or more pattern can be discriminated. However, in the part with a continuous pattern of 2T, However, it is difficult to clearly indicate the phase of the channel bit string only by reproducing the waveform as described above. In PRML detection, by referring to the information obtained from the reproduced waveform before or after each continuous pattern, it is possible to clearly indicate the channel bit string located in the part of the continuous pattern with 2T. News Mix-10- 200425070 It is easy to cause a detection error. This detection error occurs when detecting a channel bit length of τ in a long continuous part of 2T, replacing a 2T one. During the entire continuous pattern, in this case, a detection error will fill the entire detection range that is replaced by a channel bit and continues for a plurality of bytes. Among the reproduced signals with a long continuous pattern of 2T (that is, the minimum operation length is 1), a low signal amplitude state will last for a long time, which makes it necessary to extract a channel clock from the reproduced signal. Difficult, in view of the instability of the channel clock extraction, the continuity of the 2T pattern is no longer welcome. Patent Documents 1 and 2 both disclose the encoding method under the RLL (1, 7) rule. Furthermore, Patent Document 1 He 2 further reveals a technique for reducing REDUNDANCY under the RLL rule and DSV gain control. However, the problem caused by the continuous state of minimum operation length 1 and its solution are not clear. Secondly, Patent Document 3 discloses that by using a conversion table with a SECTION, the continuous state of the minimum operation length is limited to a predetermined number of times. However, Patent Document 3 uses only a variable length Code, and never consider any encoding rate. In addition, it is also unfavorable to reproduce a signal recorded from a disc by using a modulation of 0,7). For ㈠, 7) modulation, a low-frequency component 尙 is included in the reproduced signal. The low-frequency component in the reproduction signal of the 'youshishi' also changes a servo control signal in order to control an optical disc device. (3) Summary of the Invention Therefore, it is an object of the present invention to provide a code modulation method and a code-1 1-200425070 modulation device 'for obtaining a code having the same coding rate as (1, 7) modulation. Modulation code. This method can avoid or prohibit the existence of a pattern, which can easily cause the detection error of one of the reproduced signals in a channel bit string, and is suitable for high-density recording. At the same time, the DC component will be reduced. Another object of the present invention is to provide a demodulation method and a demodulation device 'for reading the aforementioned code and an information recording medium, the information recording medium records data by using the code, and can prevent Or prohibit the detection of errors. In order to solve the above problems, according to the code modulation method and the code modulation device according to the present invention, an operation length has a coding rate of 2/3 the same as that of the (1, 7) modulation, and indicates that the channel bit Between the "1" bits of the string, the number of bits, a, 0, and a data bit string is converted into a channel bit string so that the operation length has a minimum of 値 1 and a maximum of 値 1 0. In addition, in When converting any data bit string, the channel bit string does not include a pattern whose operation length 1 is continuously repeated six or more times, such as "1010101010101". Furthermore, the channel bit string has a DSV control bit for selecting a “0” bit or a “1” bit according to a DSV, by selecting a stack of DSV control bits according to the DSV, and by using For random data of the data bit string, a frequency component of a signal can be obtained from the NRZI conversion of the channel bit string, and a maximum value of the frequency component is reduced by 20dB and more (when the frequency is 1/1 0 , 0 0 0) or less (when the frequency is a channel clock frequency). In addition, the demodulation method according to the present invention includes the following steps: before separating the channel bit string for each code word, detecting a pattern replaced under a replacement rule, wherein the replacement rule is Used for consecutive-1 2-200425070 the codeword; replacing the detected pattern with the previous pattern before replacement; and separating the pattern into a codeword of the channel bit string containing 12 bits A plurality of demodulation tables storing a data character including a data bit string having 8 bits, and corresponding to the code character including the channel bit string having 12 bits, selecting The demodulation table is used to demodulate the separated codeword. The codeword is based on displaying information of subsequent codewords having 12 channel bits. The codeword is indicated by using the codeword. The unit has the information of 12-channel bits and the selected demodulation table to obtain the data characters including the 8-bit data bit string. In addition, the demodulation and conversion device according to the present invention includes a plurality of demodulation and conversion tables for storing a data word (DATA WORD) containing a data bit string of 8 bits, and corresponding to 12 The code word of the channel bit string of the bit; a device for detecting a placed synchronous pattern from the channel bit string; detecting a replacement before separating the channel bit string for each code word A device that is replaced under the rule, the detected one is replaced by the previous one before the replacement, and a device that separates the previous one into a code word containing the 12-bit channel bit string; Selecting the demodulation table to demodulate the separated code character, wherein the code character is based on an information indicating the subsequent code character of the 12-channel bit; and by using display 1 A device for obtaining the information of the code character of the 2 channel bits and the selected demodulation table to obtain the data character including the data bit string having 8 bits. In addition, the information recording medium according to the present invention is used to record a channel bit string obtained by NRZI conversion, and is made to correspond to 200425070 a concave length (PIT LENGTH) and a concave interval (PIT INTERVAL). In the recording medium, the information is recorded such that an operation length in the channel bit string has a minimum 値 1 and a maximum 値 10, except for a synchronization that is placed in a predetermined period. Outside of the pattern, the occurrence of a pattern that repeats the calculation length 1 six or more times is forbidden in the channel bit string, a frequency component of a signal, and the signal is from a concave (PIT) And it is recorded that the concave mask has a power density, wherein the power density is reduced by 20 dB from a maximum value of the frequency component, more (when the frequency is 1 / 10,000) or less (when the frequency is a channel clock frequency) ). According to the present invention, a code modulation method and a code modulation device are provided to obtain a 'modulation code having a * coding rate equal to (1,7) modulation, and to prevent the reproducibility of a channel bit string from being easily generated. The occurrence of a detection error pattern of the signal and the high-density recording suitable for low-DC components. In addition, the demodulation method and the demodulation device of the present invention are used to read the code and an information recording medium. The information The recording medium uses the code to record data and prevent detection errors from occurring. In particular, the channel bit string of the present invention has a 2/3 encoding rate, a minimum length of operation length 1, and a maximum length of 1 °. , And the number of repetitions of no more than five operations of length 1. Furthermore, the channel bit string has a sufficiently low frequency component and is suitable for high-density recording. When considering the range of code characters, it is advantageous The reason is that it can effectively prevent the influence on the three bytes. Furthermore, the coding rate is 2/3, and the amplitude length is less than a maximum 値 20dB (when the frequency is 1/1 0,000) or Is less (when the frequency is One channel clock frequency). In contrast, during demodulation, data is processed based on 12-bit codeword units, and the codewords before / after -1 4-200425070 It will also be referenced and can clearly understand the circuit structure that does not generate detection errors. In addition, it is advantageous in that the channel clock can be stably extracted even at high recording densities without detection errors. . (5) The diagram briefly illustrates that the first diagram is a part of a code conversion table according to the modulation method of the present invention; the second diagram is another part of the code conversion table according to the modulation method of the present invention; The second figure is another part of the code conversion table according to the modulation method of the present invention; the fourth figure is another part of the code conversion table according to the modulation method of the present invention; the fifth image (A) FIG. 5 is a replacement rule diagram of the modulation method according to the present invention; FIG. 5 (B) is another replacement rule diagram of the modulation method according to the present invention; FIG. 6 is a frequency characteristic diagram of one yard; Figure 8 is a synchronization pattern diagram of the modulation method according to the present invention; Figure 8 is a flowchart of the modulation method according to the present invention; Figure 9 is a configuration of a modulation circuit according to the modulation method of the present invention The tenth figure is a flowchart of the demodulation method according to the present invention; the eleventh figure is a separation rule diagram of the demodulation method according to the present invention; the twelfth figure is the demodulation method according to the present invention A part of a demodulation method of the method 15-200425070; the thirteenth figure is the root Another part of a demodulation table according to the demodulation method of the present invention; the fourteenth figure is a configuration diagram of the demodulation method according to the present invention; and the fifteenth figure is a conventional modulation A one-code conversion table for the method. (IV) Embodiment In order to clarify the above and other objects, features, and advantages of the present invention, the embodiments of the present invention will be described in detail with reference to the accompanying drawings. The first to fourth figures are code conversion tables according to the code modulation method of the first embodiment of the present invention. In the first to fourth figures, the 8-bit data characters 00 to FF are expressed in hexadecimal notation, and the corresponding code characters of 12-bit bits and S 0 to S are used. The continuation or subsequent type indicated by 2, in each table, the above-mentioned data characters, code characters, and continuity states are collectively presented in the form of a table. From here, you can understand the present invention clearly. Code modulation is used to tune 8-bit data characters into 12-bit channel bits, and it is also used to achieve 8 to 12 modulation of the coding rate (2/3). In particular, the three code conversion tables presented in each of the first to fourth figures respectively use the current types SO, S 1, S2. It should be noted that the 12-channel bits in the code conversion table In addition to, 0, and and 1, 1, the code character also includes a mark and a "#" 'mark, which is a chain bit used to link two code characters, and when a subsequent code character When one of the leading bits obtains "1" and "0", it will obtain "0" and "1" respectively, and the mark "#" is a DSV control bit, which can be generated according to the channel generated by the chain of code characters. One of the 16-200425070 DSVs obtained by the bit string, optionally obtain "0" and "1". The three code conversion tables for the patterns S 0 to S 2 in the first to fourth figures are successively selected according to the next state in the code conversion table to generate a channel obtained by chaining the code characters. Bit string. Between the channel bit strings thus obtained, the continuous data "1" will not appear, and the calculation length of the continuous occurrence number of the data "0" will always remain 10 or less. Therefore, the data "1" does not appear continuously in the channel bit string, and the length of the mark or space generated by the NRZI conversion of the recorded channel bit string always has a length not less than 2T (the mark T represents a channel bit Element length), that is, it can be understood that the code conversion tables of the first to fourth figures follow the RLL (1,10) rule with a maximum operation length of 10, so it can prevent symbols or spaces smaller than 2T , Because it will cause difficulties in recording and detection. The above-mentioned situation can be achieved by using the code conversion tables of the first to fourth pictures even when the DSV control bit obtains one of "0" or "1". And keep it up. Furthermore, the chaining rule presented in Figure 5 (A) is used to chain or replace code characters. According to this chaining rule, operation lengths such as "1010101010101" can be excluded from the channel bit string six times or For a pattern of more times, when the channel bit string is subject to NRZI conversion, the pattern of operation length 1 is recorded with a mark or space of the shortest operation length of 2T, and the number of consecutive iterations of operation length 1 is limited to Up to five times can avoid a low-amplitude state to be continuous or reproduced. The presented chaining rule is used to link two consecutive code characters, and to define the one that is different from the previous one in the bit sequence. A code character to replace a code character corresponding to a predetermined bit string. -17-200425070 Please refer to the fifth figure (A). The chain rule is applied to the chain bits, * ,, determined to be "0" or "1", and the code characters obtained through the code conversion table are used. In the fifth figure (A), the mark previously displayed in the previous code character is replaced, and “χ” represents that the corresponding bit will obtain “0” ,, 1 ,,,, # ,, and, One of, *,, the bit position corresponding to "X" is kept constant before replacement and therefore does not change. The channel bit string replaced based on the chain rule is included in the chain code All patterns of characters of which the operation length 1 may appear six or more repetitions in the character. According to the chain rule, the channel bit string can be obtained by any other pattern that cannot be obtained from the code characters in the code conversion table. Replacement, the chain of code characters will be applied to the previous chain point first. The chain rule of the fifth figure (A) will be appropriately applied to the sign or rule number of each chain point. Some code characters can be replaced. Double to connect the previous codeword and subsequent or subsequent codewords The channel bit string can be obtained by the code conversion tables of the first to fourth pictures and the chain rule of the fifth picture (A), which has a coding rate of 2/3, the minimum operation length is 1, and the maximum operation length is 10. The number of repetitions of the operation length 1 of the channel bit string is limited to five or less. When the channel bit string is subject to NRZI conversion and recorded as data, the situation will be satisfied such that the marks and spaces The length is 2T or more and 1 1T or less, and the number of consecutive repetitions of 2T marks and spaces is limited to five or less. In an area with 2T consecutive marks and spaces, the reproduction is repeated. The amplitude of the signal will not be obtained sufficiently, and therefore the data will be erroneously detected. By limiting the number of consecutive 2T patterns to five or less, the occurrence of patterns that cause errors can be suppressed. -18-200425070 When the continuous generation of 2T patterns is limited to five times or less, even when the 2T patterns are continuously generated, the length of the marks and spaces will be limited to 10T or less. In PRML detection, the entire continuous 2T pattern is 1T converted And it is easy to cause an error caused by 1T conversion. However, if the number of consecutive 2T patterns is limited to five or fewer times, the impact of this 1T conversion will be affected by 12 or fewer channel bits. Therefore, even if the range of codewords is taken into consideration, the negative influence of 3 bytes can be effectively prevented.
其次討論包含於碼轉換表中的D S V控制位元，在經由 NRZI轉換所獲得的一信號串中，自通道位元串的領導位元 於每個通道位元加上1(或是-1)可獲得DSV，此時會產生正 或負的極性，DSV係用以指出碼字元的直流成份，當初始 値假設爲〇並且因此自領導位元所獲得的DSV之絕對値接 近〇時，便可減少直流成份。Secondly, the DSV control bits included in the code conversion table are discussed. In a signal string obtained through NRZI conversion, the leading bit from the channel bit string plus 1 (or -1) for each channel bit. DSV can be obtained. At this time, positive or negative polarity will be generated. DSV is used to indicate the DC component of the code word. When the initial 値 is assumed to be 0 and therefore the absolute 値 of the DSV obtained from the leading bit is close to 0, then Can reduce DC component.
根據本發明之碼調變方法，碼字元中DSV控制位元”#’， 的値可參考碼轉換表獲得，並且碼字元中DSV控制位元”#’， 的値係決定使得在關於通道位元串的下一個DSV控制位元 之前所計算的DSV之値變爲接近〇，第六圖表示在DSV控 制下經由NRZI轉換之後所獲得之信號的一頻率特徵，橫 座標代表經由通道時脈頻率標準化之後的頻率，縱座標代 表頻率成份的功率密度，請參閱第六圖，根據上述方法而 獲得調變的隨意資料的振幅成份指出頻率的最大値等於通 道時脈頻率的1 /4左右，相反地，很明顯的，振幅成份指 出，一低振幅在頻率等於或少於通道時脈頻率1 /1 0，0 0 〇之 -19- 200425070 時，該低振幅等於或低於最大値20dB或是更多，等於或少 於通道時脈1/1〇,〇〇〇的通道頻率對應於一伺服控制帶，以 控制一光學讀寫頭的位置，頻帶中的振幅強度自最大値減 少2 ODb或更多，藉此抑制對於一伺服控制信號具有傷害性 的影響，有利之處在於，位置控制的精確度仍保持著。 本發明還確保第一圖和第四圖之碼轉換表的DSV控制 位元”0”或”1”不會擾亂對於連續2T圖案之數目的限制以及 運算長度限制，並與碼字元之前或之後的連鎖碼字元無關， 因此，在DSV控制位元出現時，在其之前或之後的通道位 元串的運算長度便無須被檢查，並且”0”或”1”可被當成DSV 控制位元而被任意地選取，其配置電路在結構上亦極其簡 易。 以上所述皆係基於第一圖至第四圖之碼轉換表以及第 五圖（A)之連鎖法則，然而，明顯地，藉由使用調變資料字 元和碼字元之間的對應關係的一調變表可以獲得同樣的好 處，所有在第五圖（A)的連鎖法則之下被替換的圖案皆不包 含具有六個或更多個2T連續圖案的任何圖案，因此，藉由 偵測連續2T圖案的數目可以忽略一部份的替換，舉例來 說，在第五圖（A)之連鎖法則所包括的圖案當中，只有具 有”1010101010101”等運算長度1重覆六次或更多次的圖案 可被替換，再者，DSV控制位元的配置亦不限於只有第一 圖至第四圖中碼轉換表的例子，舉例來說，包括作爲一位 元的DSV控制位元的碼字元係分離成具有DSV控制位元”0” 的碼字元以及具有DSV控制位元”1”的碼字元等二種型態， -20- 200425070 分離後的一碼字元可與另一碼字元相結合，除了分離後的 碼字元以及藉此D S V控制位元之位置被改變時，經由上述 運作所獲得的碼轉換表具有DSV控制位元相同的產生頻 率，並且因此而與第一圖至第四圖之碼轉換表具有相同的 特徵。 在長通道位元串的情形之中，常會發生當通道時脈處 於一混亂狀態或是一非同步狀態而造成解調變錯誤的產 生，爲了避免解調變錯誤，一同步圖案常被置入通道位元 串中，因此，即使在重製時同步作業處於混亂狀態，藉由 偵測下一個同步圖案仍可偵測到這樣一種混亂狀態，並且 解調變錯誤的連續性亦可避免。 第七圖係爲應用於本發明之碼調變方法的同步圖案或 碼（以下縮寫爲SYNC碼）的一例，同步圖案或SYNC碼與第 五圖（A)之連鎖法則所得之圖案以及第一至第四圖之碼轉換 表不同，這是因爲第七圖中每個SYNC碼皆包括一運算長 度 12(以 12-運算-長度作代表）的一圖 案” 10000000000001 ”，這個 SYNC碼係由四個 SYNC碼或 圖案SY0至SY3(對應於狀態資訊或狀態S0至S2)所構成， 如第七圖所示，同樣的碼或圖案係用於狀態資訊S 1和S2， 每個SYNC碼或圖案係基於被置入的狀態資訊而被選取， 在同步圖案置入之後的碼字元當中，狀態資訊會提供給S 1 或S2,並且因此碼運作會繼續，在這種方式之下，即使SYNC 碼被置入，1-運算-長度連續重覆六次或更多次的圖案也不 會以最小運算長度保持在1的方式出現，雖然碼包括了 12- - 21- 200425070 運算-長度（運算長度12)的圖案，SYNC碼仍然會以不小於 一運算長度11的圖案形成（也就是11-運算-長度），這是因 爲這種圖案不會出現於通常的碼字元中。 在使用SYNC碼或圖案的情形中，第五圖（B)的一連鎖 法則以及標記1 0亦可用於連鎖碼字元，使得S YNC碼不超 過最大運算長度1 0，換句話說，第五圖（A)的連鎖法則不能 應用於SYNC碼和碼字元之間的連鎖，並且因此，應該使 用連鎖法則1 0，如第五圖（B)所示，連鎖法則或標記1 〇係 包括一預先決定的圖案SY3，其將會於下文進行陳述，並 且SY3係被當作一後續或現今的碼字元而連鎖。 每個SYNC碼或圖案皆包括一 DSV控制位元，在碼轉 換表中的DSV控制位元係只用於一部份的碼字元，因此， D S V控制位元不會以附屬於調變資料串的方式出現，根據 本發明之碼調變方法，DSV控制位元之値係直到下一個DSV 控制位元出現後才會決定或固定，有利之處在於，藉由提 供DSV控制位元給每個SYNC碼，DSV控制位元之値便可 在同步圖案的每個期間中決定。 四種SYNC碼或圖案SY0至SY3係被隨意地選取和可 能被規則地選取，用以確定關於被偵測的SYNC碼的通道 位元串的一近似位置，然而，如果不需要確認位置，SYNC 碼SY0至SY3便會被隨意地選取、或是只有同步圖案SY0 被使用，再者，SYNC碼或圖案並不限制於所述之圖案並且 具有一任意長度，藉由SYNC碼或圖案，便可以修改SYNC 碼以及狀態資訊，其中狀態資訊係顯示碼轉換表以及係於 - 22 - 200425070 同步圖案之後使用。 第八圖係上述碼調變方法之流程圖，在調變開始時， 資訊情況便初始化成S 1或s 2，並且D S V初始化成0，s YNC 碼或圖案接著便依序置入位於資訊框架首部的同步圖案 SY0、SY1、SY2、以及SY3，其中該資訊框架係藉由分離 位於一恆常位元組（例如9 1位元組）的資料所獲得，在這種 情形中’調變開始之後的位置係對應於置入SYNC碼或圖 案SY0的一位置，同步圖案SY0係對應於狀態資訊（狀態）S1 或S 2而選取，在置入同步圖案之後，狀態資訊便更新爲s } 或S2，在置入同步圖案之後同步圖案尙包括DSV控制位 元，然而，在更新狀態資訊之前，同步圖案並不包括DSV 控制位元並且因此位元亦尙未決定。 隨後，資料位元便相繼地被8位元所抽取出直到置入 下一個同步圖案的位置，並且被抽取出的資料位元係藉由 使用碼轉換表而被轉換成碼字元，此外，狀態資訊以碼轉 換表爲基礎而被更新，再者，在碼字元的替換之後，碼字 元係基於連鎖法則而連鎖，由於在置入同步圖案之後的碼 字元應該與前一個同步圖案連鎖在一起，因此碼字元的連 鎖法則不會被應用，當藉由使用碼轉換表所獲得的碼字元 包括DSV控制位元時，舊的DSV控制位元之値便基於DSV 而決定，其中DSV係相對於直到DSV控制位元之前所新獲 得的通道位元串所計算的DSV。 如前所述，同步圖案係定期地置入而編碼亦被進行， 直到下一個DSV控制位元出現之前，DSV控制位元之値都 -23- 200425070 不會被決定，然而，在資料結束時，最後一個DSV控制位 元之値會基於相對於直到DSV控制位元之前所新獲得的通 道位元串所計算的DSV而決定，並且接著編碼便會完成， 如果置入同步圖案的期間決定成大約1 0 0位元組，則第六 圖所顯示的頻率特徵便會不受制如圖案所產生的效率降低 的影響而獲得，碼轉換表或是同步圖案中所指出的一部份 的DSV控制位元可用以控制記錄資料的極性，藉由在預先 決定的位置使用DSV控制位元可以限制記錄於記錄光碟中 的同步圖案。 第九圖係根據本發明之碼調變方法所使用的一調變電 路，該調變電路包括一碼轉換表參考電路1、一狀態暫存 器2、一多工器3、以及一同步圖案置入電路4，碼轉換表 參考電路1包括第一至第四圖之碼轉換表1〇1，碼轉換表 參考電路1係接收每個8位元的一資料串B(t)、以及自狀 態暫存器2所傳輸而來的狀態資訊S(t)，碼轉換表參考電 路1根據狀態資訊S(t)、參考第一至第四圖之碼轉換表1〇1、 輸出具有12通道位元的一碼字元X(t)，其次，碼轉換表參 考電路1根據碼轉換表1 〇 1而輸出下一個狀態資訊給多工 器3，多工器3自同步圖案置入電路4接收下一個狀態資 訊、選取它、並且輸出下一個狀態資訊s(t+1)以指出下一 個狀態給狀態暫存器2，狀態暫存器2對應於下一個資料 串B(t)而輸出狀態資訊S(t)給碼轉換表參考電路1以及同 步圖案置入電路4。 如前所述，碼轉換表參考電路1係具有複數個碼轉換 -24- 200425070 表101、基於狀態暫存器2所保持的狀態資訊s(t)而轉換碼 轉換表101、以及對應於所給的資料字元和狀態資訊s(t+1) 而輸出碼字元s(t)，其中狀態資訊S(t+1)係指出所參考的 下一個碼轉換表，再者，一連接電路，也就是，一連鎖電 路5係連接於第九圖之調變電路於碼轉換表參考電路1以 及同步圖案置入電路4的輸出端，連鎖電路5亦連接於一 DSV控制電路6，一通道位元串係自DSV控制電路6而輸 出。 同步圖案置入電路4基於在一預先決定的期間由狀態 暫存器2所保持的狀態資訊S(t)而輸出同步圖案以置入通 道位元串之中，並且輸出此狀態資訊，自碼轉換表參考電 路1所輸出的狀態資訊以及自同步圖案置入電路4所輸出 的狀態資訊皆如前所述地經由多工器3而傳輸給狀態暫存 器2，狀態暫存器2之運作係使得下一個狀態資訊S(t+1)更 新，並且在每次自碼轉換表參考電路1輸出碼字元時被保 持以及在每次自同步圖案置入電路4輸出同步圖案時保 連鎖電路5之運作係用以連接或連鎖自碼轉換表參考 電路1所輸出的碼字元以及自同步圖案置入電路4所輸出 的同步圖案，藉由產生一連鎖碼字元，爲了連接或連鎖這 些碼字元，連鎖電路5會決定包含於最後碼字元至，，〇，，或”1” 的一合倂或連接位元” ”之値，並且藉由同步圖案而核對第 五圖（A)之連鎖法則，當連鎖法則對應於同步圖案時，碼字 元會被替換並且結果資料輸出成爲序列資料以指出通道位 -25- 200425070 元串。 DSV控制電路6係對於連鎖電路5所傳送的序列資料 作反應，並且抽取顯示DSV控制位元的資訊，其中DSV控 制位元係包含於自連鎖電路5所輸出的序列資料，其次，DSV 控制電路6係決定D S V控制位元並且將其輸出以作爲通道 位元串，使得DSV之値接近0，由於調變電路具有上述結 構，便獲得適用於高密度記錄的通道位元串，同時不會出 現1-運算-長度重覆六次或更多次的圖案產生，這種通道位 元串會使得低頻成份變得足夠小。 接下來所敘述的是根據本發明編碼調變方法以及編碼 調變電路所獲得的通道位元串之一解調變方法，藉由第十 圖之流程圖可明確陳述解調變方法，首先，由於決定重製 信號，同步圖案自通道位元串中被抽取出，碼字元的範圍 基於被抽取的同步圖案而明確界定在每套的12通道位元， 因此，對於每個圖案的偵測便可進行，其中的每個圖案係 基於藉由連鎖法則的使用而自通道位元串所獲得的範圍而 替換、亦係在替換之前回傳的前一個碼字元或圖案，因此， 該圖案即被分離成碼字元，使用第五圖（A)的連鎖法則有助 於圖案在反轉換以及判斷方面的偵測、或是有助於圖案在 分割方面的決定’此決疋可以藉由在第十一圖所示的三個 分離法則替換碼字元而淸楚了解，接著，藉由上述方法所 獲得的碼字兀之使用以及參考解調變表所得的解調變結 果，便可獲得8位元的資料字元，在第十一圖中，於替換 之前包含在前一個圖案中的參考標記”X”代表位元可取 一 26- 200425070 掊’’1”或”〇”其中之一，在替換之前，對應於替換之後的參 考檩記，，x”的位元仍會保持原値。 第十二和第十三圖係代表自12通道位元的碼字元而獲 得8位元的資料字元所用的解調變表，請參考第十二和第 十二圖，三個解調變表T0至T2如圖所示，考慮解調變目 標碼字兀、在該解調變目標碼字元之後的一後續碼字元、 以及同步圖案，選取所使用的解調變表至T2的其中之 一’當該解調變目標碼字元之後的下一個碼字元係以位 元” 1 ”作爲起始、或是當下一個同步圖案指出狀態〇的S Y 0 至SY2，即使用解調變表T0，當該解調變目標碼字元之後 的下一個碼字元係以”0000”作爲起始、或是當下一個同步 圖案指出狀態0的S Y 3，即使用解調變表τ 1，當該解調變 目標碼字兀之後的下一個碼字元係以，，〇 1，，、，，〇 〇丨，，、或 是”000 1 ”作爲起始、或是當下一個同步圖案指出狀態1和2 的s Y0至SY3，即使用解調變表T2。對應於該解調變目標 碼字兀’8位兀的資料字元係以16進位的表示方法來表示， 當同步圖案以解調變目標碼字元的型態存在之後，即選取 解調變表T 0，並且參考當選取解調變表τ 2時對應於狀態 資訊S0所產生之同步圖案、以及參考對應於狀態資訊S1 或S2所產生之同步圖案，因此，資料字元即以上述之方式 產生。 在解調變表中，1 2位元的通道位元串的碼字元係對應 於8位元的碼字元，因此，有利之處在於任何錯誤皆不會 以上述方式散佈或傳播，這是相對於長度可變之轉換表之 -27- 200425070 使用所產生的一可變方塊碼（VARIABLE BLOCK CODE)而 言，這對於抑制因對於2T圖案之重覆次數的限制所造成的 任何錯誤的傳播、以及減少資料率的錯誤是非常有效的。 此外，需要注意的是未以碼字元的方式顯示於表中的 12通道位元的圖案、以及在資料字元的行列中以標記被 指定的圖案，這些圖案並不是根據本發明之解調變方法所 產生，當偵測到這些圖案時，無法被解調變的圖案之程序 便會進行，產生一光學資料字元的同時亦產生顯示包含一 錯誤的一資料字元的資訊，附帶一提的是，決定重製信號 的PRML偵測使得排除由未顯示於解調變表中的通道位元 串所決定的大部份圖案變爲可行，是故，決定程序和解調 變中的錯誤便可進一步地減少。 接著配合第十四圖陳述解調變電路的配置。通道位元 串被放入一同步圖案偵測電路7，同步圖案偵測電路7輸 出該通道位元库和藉由參考被偵測同步圖案之位置而指出 碼字元之範圍位置的資訊，因此，一分離和替換電路8偵 測並替換符合第十一圖之分離法則的圖案、並且進一步地 將通道位元串分離成碼字元且將其輸出，一解調變表參考 電路9將由上述所得之碼字元串轉換成具有8位元的資料 字元並將其輸出，爲了解調變具有12通道位元的碼字元， 解調變表參考電路9參考後續的碼字元和同步圖案、選取 一解調變表90 1、以及抽取對應該碼字元之資料字元，解 調變表參考電路9輸出顯示關於該碼字元之解調變的不 可行性，其中該碼字元並不會出現於解調變表中，在解調 -28~ 200425070 變之中，1 2通道位元的碼字元單位以及至少足夠的位於解 調變之前/之後的碼字元會被參考，因此，這種電路結構便 可防止解調變錯誤的增加。 根據本發明碼調變方法所獲得之通道位元串的一光學 記錄媒體之中，藉由通道位元串的NRZI轉換可獲得一信 號，並且該信號係對應於一凹面長度（PIT LENGTH)和一凹 面間隔（PIT INTERVAL)而記錄，這種記錄方式的特徵是即 使以一高記錄密度實行記錄時，通道時脈也可以穩定地抽 取，並且可以減少偵測錯誤，由凹面所獲得的重製信號極 少包括一伺服帶的成份，並且因此用於偵測信號的光學讀 寫運作的追蹤特性也不會惡化。 以下陳述本發明所述之光學記錄媒體。在本發明之光 學記錄媒體中，通道位元串係受到的管制、並且係以凹面 長度和凹面間隔的圖案記錄於光學記錄媒體中，其次，在 光學記錄媒體中，除了同步圖案之外，通道位元串係根據 具有一最小運算長度値1以及一最大運算長度値10、以及 禁止運算長度1重覆六次或更多次的圖案而形成，不用說 同步圖案係在一預先決定的期間被置入，再者，在光學記 錄媒體中資訊記錄的方式是，自凹面被讀取的信號的頻率 成份係低於該頻率成份最大値的20dB、更多（當頻率爲 1/10,00 0)或是更少（當頻率爲一通道時脈頻率）。 即使本發明發明係以以上之較佳實施例來作說明，然而對 於熟習本項技術者來說，本發明仍不限於這些實施例和使 用方法’尤有甚者，凡依本發明所附申請專利範圍所做的 - 2 9 - 200425070 均等變化及修飾，皆爲本發明專利範圍所涵蓋。 元件符號說明According to the code modulation method of the present invention, the DSV control bit "# '" in the codeword can be obtained by referring to the code conversion table, and the DSV control bit "#'" in the codeword is determined such that The DSV calculated before the next DSV control bit of the channel bit string becomes close to 0. The sixth figure shows a frequency characteristic of the signal obtained after conversion by NRZI under DSV control. The frequency after the pulse frequency is normalized. The ordinate represents the power density of the frequency component. Please refer to the sixth figure. The amplitude component of the random data obtained according to the above method indicates that the maximum frequency is equal to about 1/4 of the channel clock frequency. On the contrary, it is clear that the amplitude component indicates that a low amplitude is equal to or lower than the maximum 値 20dB at a frequency equal to or less than the channel clock frequency of 1/1, 10, 0, -19 to 200425070. Or more, the channel frequency equal to or less than the channel clock 1 / 1,00,00 corresponds to a servo control band to control the position of an optical read-write head, and the amplitude intensity in the band is reduced from the maximum 値 by 2ODb or more, thereby suppressing the harmful effects on a servo control signal, the advantage is that the accuracy of the position control is still maintained. The invention also ensures that the DSV control bit "0" or "1" of the code conversion tables of the first and fourth figures does not disturb the limit on the number of consecutive 2T patterns and the calculation length limit, and is equal to or before the code word The subsequent chain code characters are irrelevant. Therefore, when the DSV control bit appears, the operation length of the channel bit string before or after it need not be checked, and "0" or "1" can be used as the DSV control bit. It is chosen arbitrarily, and its configuration circuit is extremely simple in structure. The above are all based on the code conversion tables of the first to fourth figures and the chain rule of the fifth figure (A). However, it is obvious that by using the correspondence between the modulation data character and the code character A modulation table can obtain the same benefits. All the patterns replaced under the chain rule of the fifth figure (A) do not contain any patterns with six or more 2T continuous patterns. Therefore, by detecting The number of consecutive 2T patterns can be ignored in part of the replacement. For example, among the patterns included in the chain rule of the fifth figure (A), only the calculation length 1 with "1010101010101" and so on is repeated six times or more. The second pattern can be replaced. Furthermore, the configuration of the DSV control bit is not limited to the example of the code conversion table in the first to fourth figures. For example, it includes the code of the DSV control bit as a bit. The characters are separated into two types: a code character with a DSV control bit "0" and a code character with a DSV control bit "1". -20- 200425070 A separated code character can be used with another One code character is combined, except that the separated code characters start with When the position of the DSV control bit is changed, the code conversion table obtained through the above operation has the same generation frequency of the DSV control bit, and therefore has the same characteristics as the code conversion tables of the first to fourth figures. . In the case of long channel bit strings, demodulation errors often occur when the channel clock is in a chaotic or asynchronous state. In order to avoid demodulation errors, a synchronization pattern is often placed in In the channel bit string, even if the synchronization operation is in a chaotic state during re-production, such a chaotic state can still be detected by detecting the next synchronization pattern, and the continuity of demodulation errors can be avoided. The seventh figure is an example of a synchronization pattern or code (hereinafter abbreviated as SYNC code) applied to the code modulation method of the present invention. The synchronization pattern or SYNC code and the fifth rule (A) are obtained by the chain rule and the first The code conversion tables in the fourth to fourth figures are different. This is because each SYNC code in the seventh figure includes a pattern "10000000000001" with a calculation length of 12 (represented by 12-operation-length). This SYNC code consists of four SYNC codes or patterns SY0 to SY3 (corresponding to state information or states S0 to S2), as shown in the seventh figure, the same codes or patterns are used for the state information S1 and S2, each SYNC code or pattern It is selected based on the placed state information. In the code characters after the synchronization pattern is placed, the state information will be provided to S 1 or S2, and therefore the code operation will continue. In this way, even SYNC The code is placed, and the pattern of 1-operation-length repeated six or more times will not appear in a way that the minimum operation length remains at 1, although the code includes 12--21- 200425070 operation-length (operation Pattern with length 12), the SYNC code will still start with A length of less than 11 patterning operation (i.e. 11- calculation - the length), which is because such a pattern does not occur in a normal code of the characters. In the case of using a SYNC code or pattern, a chaining rule of the fifth figure (B) and the mark 10 can also be used for chaining code characters, so that the S YNC code does not exceed the maximum operation length of 10, in other words, the fifth The linkage rule of graph (A) cannot be applied to the linkage between the SYNC code and the code character, and therefore, the linkage rule 10 should be used. As shown in the fifth figure (B), the linkage rule or label 1 0 includes one The predetermined pattern SY3 will be described below, and SY3 is linked as a subsequent or present code character. Each SYNC code or pattern includes a DSV control bit. The DSV control bit in the code conversion table is only used for a part of the code word. Therefore, the DSV control bit is not attached to the modulation data. It appears as a string. According to the code modulation method of the present invention, the system of DSV control bits will not be determined or fixed until the next DSV control bit appears. The advantage is that by providing DSV control bits to each For each SYNC code, the number of DSV control bits can be determined in each period of the synchronization pattern. The four types of SYNC codes or patterns SY0 to SY3 are randomly selected and may be selected regularly to determine an approximate position of the channel bit string with respect to the detected SYNC code. However, if it is not necessary to confirm the position, SYNC The codes SY0 to SY3 will be selected arbitrarily, or only the synchronous pattern SY0 will be used. Furthermore, the SYNC code or pattern is not limited to the pattern described and has an arbitrary length. With the SYNC code or pattern, it can be Modify the SYNC code and status information, where the status information is used to display the code conversion table and after the synchronization pattern of-22-200425070. The eighth figure is a flowchart of the above code modulation method. At the beginning of the modulation, the information situation is initialized to S 1 or s 2 and the DSV is initialized to 0. The s YNC code or pattern is then sequentially placed in the information frame. Synchronous pattern SY0, SY1, SY2, and SY3 in the header, where the information frame is obtained by separating data located in a constant byte (for example, 91 bytes). In this case, 'modulation starts The subsequent position corresponds to the position where the SYNC code or pattern SY0 is placed. The synchronization pattern SY0 is selected corresponding to the status information (state) S1 or S2. After the synchronization pattern is placed, the status information is updated to s} or S2. After the synchronization pattern is placed, the synchronization pattern does not include the DSV control bit. However, before the status information is updated, the synchronization pattern does not include the DSV control bit and therefore the bit is not determined. Subsequently, the data bits are successively extracted by 8 bits until the position of the next synchronization pattern is placed, and the extracted data bits are converted into code words by using a code conversion table. In addition, The status information is updated based on the code conversion table. Furthermore, after the code character is replaced, the code character is linked based on the chain rule. Since the code character after the synchronization pattern is placed should be the same as the previous synchronization pattern Chained together, so the chain rule of code characters will not be applied. When the code characters obtained by using the code conversion table include DSV control bits, the old DSV control bit will be determined based on DSV. The DSV is a DSV calculated with respect to the channel bit string newly obtained up to the DSV control bit. As mentioned earlier, the synchronization pattern is placed periodically and the encoding is performed. Until the next DSV control bit appears, the number of DSV control bits is 23- 200425070. However, at the end of the data, , The last DSV control bit will be determined based on the DSV calculated with respect to the channel bit string newly obtained up to the DSV control bit, and then the encoding will be completed. If the synchronization pattern period is determined to be About 100 bytes, the frequency characteristics shown in the sixth figure will not be affected by the efficiency reduction caused by the pattern. The DSV control of the code conversion table or a part of the synchronization pattern is indicated. Bits can be used to control the polarity of recorded data. By using DSV control bits at predetermined locations, the sync pattern recorded on the recording disc can be limited. The ninth figure is a modulation circuit used in the code modulation method according to the present invention. The modulation circuit includes a code conversion table reference circuit 1, a state register 2, a multiplexer 3, and a Synchronization pattern placement circuit 4, code conversion table reference circuit 1 includes code conversion tables 101 of the first to fourth figures, and code conversion table reference circuit 1 receives a data string B (t) of each 8-bit, And the status information S (t) transmitted from the status register 2, the code conversion table reference circuit 1 according to the status information S (t) and the code conversion table 101 referring to the first to fourth figures, the output has A code word X (t) of 12-bit bits. Second, the code conversion table reference circuit 1 outputs the next status information to the multiplexer 3 according to the code conversion table 1 〇1, and the multiplexer 3 inserts the self-synchronization pattern. The circuit 4 receives the next state information, selects it, and outputs the next state information s (t + 1) to indicate the next state to the state register 2, which corresponds to the next data string B (t) The state information S (t) is output to the code conversion table reference circuit 1 and the synchronization pattern placing circuit 4. As mentioned earlier, the code conversion table reference circuit 1 has a plurality of code conversions. 24-200425070 Table 101, the conversion code conversion table 101 based on the state information s (t) held by the state register 2, and corresponding to all Given the data character and the state information s (t + 1) and output the code character s (t), where the state information S (t + 1) indicates the next code conversion table referred to, and further, a connection circuit That is, a chain circuit 5 is connected to the modulation circuit of the ninth figure to the output terminal of the code conversion table reference circuit 1 and the synchronization pattern insertion circuit 4, and the chain circuit 5 is also connected to a DSV control circuit 6. The channel bit string is output from the DSV control circuit 6. The synchronization pattern placement circuit 4 outputs a synchronization pattern based on the state information S (t) held by the state register 2 for a predetermined period to be placed in the channel bit string, and outputs this state information. The state information output by the conversion table reference circuit 1 and the state information output by the synchronization pattern placement circuit 4 are transmitted to the state register 2 through the multiplexer 3 as described above, and the operation of the state register 2 The next state information S (t + 1) is updated, and is maintained each time the self-code conversion table reference circuit 1 outputs a code word, and the interlocking circuit is maintained each time the self-synchronization pattern placing circuit 4 outputs a synchronization pattern. The operation of 5 is used to connect or chain the code characters output from the reference code 1 of the code conversion table and the synchronization pattern output from the self-synchronization pattern placement circuit 4, by generating a chain code character, in order to connect or chain these For the code word, the interlocking circuit 5 will determine the combination of the last code word to ,, 0, or "1" or the connection bit "", and check the fifth figure (A by the synchronization pattern) The chain rule of Danglian When the lock rule corresponds to the synchronization pattern, the code characters are replaced and the result data is output as sequence data to indicate the channel bit -25- 200425070 meta string. The DSV control circuit 6 responds to the sequence data transmitted by the interlocking circuit 5 and extracts and displays information of DSV control bits. The DSV control bit is included in the sequence data output from the interlocking circuit 5. Secondly, the DSV control circuit The 6 series decides the DSV control bit and outputs it as the channel bit string, so that the DSV is close to 0. Because the modulation circuit has the above structure, it can obtain the channel bit string suitable for high-density recording, while not A pattern of 1-calculation-length repetition occurs six or more times, and such a channel bit string will make the low-frequency component sufficiently small. What is described next is a demodulation method for one of the channel bit strings obtained by the coding modulation method and the coding modulation circuit according to the present invention. The demodulation method can be clearly stated by the flowchart of the tenth figure. First, As it is decided to reproduce the signal, the synchronization pattern is extracted from the channel bit string. The range of code characters is clearly defined in each set of 12 channel bits based on the extracted synchronization pattern. Therefore, the detection of each pattern The test can be performed. Each of these patterns is replaced based on the range obtained from the channel bit string through the use of the chain rule. It is also the previous code character or pattern returned before the replacement. Therefore, the The pattern is separated into code characters. Using the chain rule of the fifth figure (A) can help the pattern to detect reverse conversion and judgment, or it can help the pattern's segmentation decision. It is understood by replacing the codewords with the three separation rules shown in the eleventh figure. Then, using the codewords obtained by the above method and the demodulation results obtained by referring to the demodulation table, Available An 8-bit data character. In the eleventh figure, the reference mark "X" included in the previous pattern before replacement indicates that the bit can take one of 26- 200425070 掊 `` 1 '' or 〇. Before the replacement, corresponding to the reference note after the replacement, the bit of "x" will remain the same. The twelfth and thirteenth diagrams are demodulation conversion tables used to obtain 8-bit data characters from the code characters of the 12-channel bits. Please refer to the twelfth and twelfth diagrams, three demodulation The conversion tables T0 to T2 are shown in the figure. Considering the demodulation target codeword, a subsequent codeword after the demodulation target codeword, and the synchronization pattern, the demodulation table to be used is selected to T2. One of the 'When the next codeword after the demodulation target codeword is starting with bit "1", or when the next synchronization pattern indicates the state SY0 to SY2, the solution is used. Modulation table T0, when the next codeword after the demodulation target codeword starts with "0000" or when the next synchronization pattern indicates SY 3 of state 0, the demodulation table τ is used 1. When the next codeword element after the demodulation and conversion of the target codeword is based on, 〇1 ,,,,, 〇〇 丨 ,, or "000 1" as the start, or the next synchronization The pattern indicates s Y0 to SY3 for states 1 and 2, ie, using demodulation table T2. The data character corresponding to the demodulation target codeword '8-bit data is represented by a hexadecimal representation method. When the synchronization pattern exists in the form of the demodulation target codeword, the demodulation conversion is selected. Table T 0, and referring to the synchronization pattern corresponding to the state information S0 when the demodulation conversion table τ 2 is selected, and the synchronization pattern corresponding to the state information S1 or S2, so the data characters are Way to produce. In the demodulation table, the codeword of the 12-bit channel bit string corresponds to the 8-bit codeword. Therefore, it is advantageous that any errors will not be spread or propagated in the above manner. It is relative to a variable length conversion table of -27- 200425070. A variable block code (VARIABLE BLOCK CODE) is used to suppress any errors caused by the limitation of the number of repetitions of 2T patterns. Spreading and reducing data rate errors is very effective. In addition, it should be noted that the 12-channel bit patterns that are not displayed in the table as code characters and the designated patterns are marked in the ranks of the data characters. These patterns are not demodulated according to the present invention. As a result of the method, when these patterns are detected, the process of the patterns that cannot be demodulated will be performed, and an optical data character will be generated, and the information including an error data character will also be displayed. It is mentioned that the PRML detection that determines the reproduced signal makes it possible to exclude most of the patterns determined by the channel bit strings that are not shown in the demodulation table. Therefore, errors in the decision process and demodulation are therefore determined. Can be further reduced. Next, the configuration of the demodulation circuit is described with reference to the fourteenth figure. The channel bit string is put into a synchronization pattern detection circuit 7, and the synchronization pattern detection circuit 7 outputs the channel bit library and the information indicating the range position of the code character by referring to the position of the detected synchronization pattern. A separation and replacement circuit 8 detects and replaces the pattern conforming to the separation rule of the eleventh figure, and further separates the channel bit string into code words and outputs it. A demodulation table reference circuit 9 will be described by the above. The obtained codeword string is converted into a data character having 8 bits and outputted. In order to demodulate a codeword having 12 channels, the demodulation table reference circuit 9 refers to subsequent codewords and synchronization. Pattern, selecting a demodulation table 90 1, and extracting data characters corresponding to the code character, the demodulation table reference circuit 9 output shows the feasibility of demodulation of the code word, where the code word The unit does not appear in the demodulation table. In the demodulation -28 ~ 200425070, the code unit of 12 channel bits and at least enough code words before / after the demodulation will be changed. Reference, therefore, this circuit structure can be Prevent the increase of demodulation errors. In an optical recording medium of the channel bit string obtained according to the code modulation method of the present invention, a signal can be obtained by NRZI conversion of the channel bit string, and the signal corresponds to a concave length (PIT LENGTH) and Recording at a concave interval (PIT INTERVAL). This recording method is characterized in that the channel clock can be stably extracted even when recording is performed at a high recording density, and detection errors can be reduced. The reproduction obtained by the concave surface The signal rarely includes a servo band component, and therefore the tracking characteristics of the optical read-write operation for detecting the signal will not deteriorate. The following describes the optical recording medium according to the present invention. In the optical recording medium of the present invention, the channel bit string is controlled and recorded on the optical recording medium in a pattern of concave length and concave interval. Second, in the optical recording medium, in addition to the synchronization pattern, the channel The bit string is formed based on a pattern having a minimum operation length 値 1 and a maximum operation length 値 10, and a prohibition operation length 1 from being repeated six or more times. Needless to say, the synchronization pattern is formed in a predetermined period. The information is recorded in the optical recording medium in such a way that the frequency component of the signal read from the concave surface is 20dB below the maximum value of the frequency component and more (when the frequency is 1/10, 00 0 ) Or less (when the frequency is a channel clock frequency). Even though the present invention is described with the above preferred embodiments, for those skilled in the art, the present invention is not limited to these embodiments and methods of use. All changes and modifications made by the patent scope-2 9-200425070 are covered by the patent scope of the present invention. Component symbol description
1 碼 轉 換 表 參 考 電 路 2 狀 態 暫 存 器 3 多 工 器 4 同 步 圖 案 置 入 電 路 5 連 鎖 電 路 6 DS V 控 制 電 路 7 同 步 圖 案 抽 取 電 路 8 分 離 及 替 換 電 路 9 解 調 變 表 參 考 電 路 10 1 碼 轉 換 表 90 1 解 調 變 表1 Code conversion table reference circuit 2 State register 3 Multiplexer 4 Synchronous pattern placement circuit 5 Interlocking circuit 6 DS V control circuit 7 Synchronous pattern extraction circuit 8 Separating and replacing circuit 9 Demodulation table reference circuit 10 1 Code conversion Table 90 1 Demodulation table
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