TWI261843B - Voltage generator with reduced noise - Google Patents

Abstract

A voltage generator with reduced noise features a detector, a controller, a sub-booster, a main booster and a voltage adder. The detector receives an output voltage, a first reference voltage and a second reference voltage lower than the first reference voltage, and then outputs a first sensing signal and a second sensing signal. The controller receives the first sensing signal and the second sensing signal and an action signal to output a first control signal and a second control signal. The sub-booster boosts a voltage in response of the first control signal. The main booster boosts a voltage in response to the second control signal. The voltage adder adds output signals from the sub-booster and main booster, to provide the output voltage.

Description

1261843 玖, invention description: [Technical field to which the invention pertains], the invention is broadly related to a voltage generator, and in the case of a clock, the invention is related to the charge-extraction type voltage generation of the species cry. [Prior Art] In the conventional DRAMs, charges are extracted to generate a driving voltage of a material driving word line and a bit line without losing a threshold voltage. During the operation (for example, word line driving and bit line pre-charging), a large amount of energy is consumed, which in turn causes the level of the driving voltage to become a lower level. In this case, in the prior art, it is detected that the level of the driving voltage becomes a time point lower than a target level in order to extract the electric charge and maintain the level of the driving voltage. Figure 1 shows a block diagram of a conventional voltage generator. The conventional voltage generator includes a detector 1 -, a oscillating device 20, a control driver 3 〇, and a gangster. Photo detection _ Measure the level of a driving voltage Vpp. The cry comes from the pastor-output signal. The control driver; should;: an output signal of the far-reaching 20. The read charge is extracted by 1 Λ U and 帛 flat 40 in response to the -output signal ' from the control driver 30 to output the drive voltage Μ. 2a and 2b are diagrams for explaining the voltage generation (four) circuit shown in Fig. i. The detector 10 divides the driving power

Vpp has a detection voltage

Vpps. Then, the 10 compares the detection power, the VPPS and the reference voltage Vrc, and outputs a low level signal if the detection voltage Vpps is greater than the reference voltage Vrc, and vice versa. The detection voltage Vp is ν ___Αϋ__χ, and the PPS is expressed by the following tens of programs: pps R, + R2 + R3 + R4 卯 If the output signal from the detection device 1 is a low level signal, that is, 89019 1261843 d ' The detection voltage Vpps is smaller than the reference voltage νιχ 〜,

Turned out a ring of Lu signal. The control driver outputs control signals Η, 1叩 gi and g2, "responsive to the vibration 4 signal from the oscillator mQ. S The control signal pl 2 of the control driver 30: "self, clock i 8 is controlled to control the drive voltage Vpp. The plurality of capacitors c and c, 甩' in response to the II temple control signal? And p2. The charge stored in the capacitors clfDC2 is transmitted in response to the controls gl and g2 being greater than an externally applied voltage Vext to the voltage Vext. Figure 3 is shown for illustrating the operation of a conventional voltage generator Timing diagram. When the word line or the pre-potential Tt line is activated, the level of the driving voltage Vpp starts to decrease. At the time...the detector i (H贞 measures the level of the driving force voltage V pp : low to At the target level, at time t2 'the pump 4 〇 starts to draw the charge: due to the charge extraction operation of the pump 40, the level of the driving voltage vpp starts to rise. At time t3, the detector 1 〇 detecting that the level of the driving force voltage ^ is equal to the target bit # ' and instructing the pump 40 to stop extracting the charge. However, due to the circuit response time, the actual charge extraction operation of the system is at time 14 Stop. As mentioned above, in the study In the voltage generator, a time difference between the time when the detector 1 actually detects the target level and the time when the pump 4 is turned on or off, the fluctuation of the driving voltage Vpp is changed by Δν. Large, which in turn leads to unnecessary power consumption. The important point is that the fluctuation of the driving voltage causes noise that makes the power supply unstable. [Invention] The object of the present invention is that when the driving voltage Vpp reaches a target level before a target 89019 1261843 The predetermined amount of charge is extracted according to the operation of a DRAM in order to reduce the variation of the driving voltage Vpp. In a specific embodiment of the invention, the present invention provides a voltage generator, including a detector for comparing an output voltage with a first reference voltage and a second reference voltage lower than the first reference voltage to output a first sensing signal and a second sensing signal; a controller, configured to receive the first sensing signal, the second sensing signal, and an action signal to output a first control signal and a second control signal; a booster for increasing a voltage responsive to the first control signal; a primary booster for boosting a voltage in response to the second control signal; and a voltage adder for receiving the secondary booster and the primary boost The output signals of the devices are added to provide the output voltage.The present invention will be described in detail with reference to the accompanying drawings. Fig. 4 is a block diagram showing a voltage generator according to an embodiment of the present invention. In an embodiment, the disclosed voltage generator includes a detector 100, a controller 200, a main oscillator 300, a sub-oscillator 310, a main control driver 400, a sub-control driver 410, a main The pump 500, a pair of pump 510 and a voltage adder 600. The detector 100 has more than two detection levels. After the driving voltage Vpp passes a pre-detection level, and before a driving voltage Vpp reaches a target level, the controller 200 outputs a control signal when an action signal ACT is input. The main oscillator 300 and the sub-oscillator 3 10 output a plurality of oscillating signals in response to the controller 200 transmitting the 琢 technique signal of 89019 1261843. The main control driver 400 and the sub control driver 4 10 output an interpolation control signal responsive to the main oscillator 3 〇〇 and the oscillating signals output by the sub oscillating state 3 10 . The master pump $(9) and the slave pump 51〇 output the pull voltage ' in response to the master control driver 400 and the slave control driver 4 1 〇 output of the child extraction control signal. The voltage adder 6 相 adds the voltages from the king pump 500 and the sub pump 5 1 ,, and then outputs the added voltage as a driving voltage. The drive voltage is fed back to the detector 100. Since the memory or charge leakage consumes a charge, the k-rate of the driving voltage Vpp decreases. Stimulus can be used to predict the point and magnitude of charge consumption due to a particular effect. The next four lines are taken as examples of starting word lines or pre-charging bit lines. Based on the purpose of this example, assume that the charge consumed during the start of the word line is Q1 (obtained through stimulation) and that the capacitor capacitance is C1. When the word line is activated, the variation range of the driving voltage ν 变成 becomes Q1/C1. Further, if the charge consumption is Q2, the variation of the driving voltage VPP becomes Q2/C1. Accordingly, the fluctuation of the driving voltage Vpp can be reduced by extracting and supplying a predetermined amount of charge in advance. In order to prevent the level of the driving voltage Vpp from rising too high and above the target level, a predetermined level higher than the target level is set as a pre-detected '/, 彳 position, and only when The charge is pre-extracted when the level of the driving voltage Vpp becomes lower than the pre-pulse, //,] bit. If the driving voltage V叩 is low, and a pre-detection k is applied, and an action command is input when the target level is still applied, the voltage generator disclosed in the present invention pre-tests according to a predetermined action command. The charge of 舄. As a result, the fluctuation of the driving voltage Vpp can be reduced in the voltage generator 89019 1261843 disclosed in the present invention. When the amount of charge consumed by the three passes is greater than the expected amount, the drive takes Vpp

The level will become lower than the target level. Here, the extraction of the voltage generator of ::VPP is "expressed". The equation is the same as that of the conventional voltage generator. When the amount of charge actually consumed is less than the expected amount: drive, the level of P is maintained above the target level, and 〇_corrects the coin operation. In addition, since the charge operation is started only when the drive voltage Vpp = position is measured, the pre-detection level can be prevented to prevent the Vpp from rising excessively due to the charge extraction operation. Although the preferred embodiment of the present invention uses only two detection levels, the detection level is used as the pre-detection level and the other detection level is used as the standard position, but other preferred ones are preferred. Specifically, the number of I can be detected to increase the number of levels to more than two detection levels. Figure 5 shows a timing diagram for illustrating a voltage generator in accordance with the present invention. When the detector 1 detects a pre-detected level detl and a target level det2 (tl, t2), a pre-detected level signal detl-en and a target level signal det2 are activated. —en. If the pre-detection level signal is activated, an action signal ACT is input before the target level signal det2_en is activated, and the controller 200 activates a pair of control signals (3). When the grandchild control signal sub_pump_ei1^ is activated, the sub-oscillator 31〇, the sub-control driver 410 and the sub-switch 5 1〇 will start operating in sequence. If the target level signal det2-en is activated, the main pump 5 will start operating after a pre-required full response time. The action signal ACT determines the total time of the sub-89019 -10- 1261843 ^ execution-extraction operation. Here, the auxiliary pump 5 1 = = the time period of the extraction operation overlaps the extraction operation of the main pump 500. According to the preferred embodiment, the W extraction operation can be rejected during the main extraction operation. . At time t3, the detector 100 detects that the drive power is restored to the target level. At time t4, the main pump 500 stops extracting charge after determining the response time first. The circuit diagram of the detector 1 shown in FIG. 4 is read. The detection port, the 〇L includes a detecting unit 1 20, a first comparator 1 1 0 and a second ratio, and the 130 side detecting unit 120 divides the driving voltage vpp to obtain two detectives: Pps丨 and VPPS2. The first comparator 11 compares the detected voltage into a voltage vrci corresponding to the read pre-detected level.

Vpps2 corresponds to the p p s 1 and V p p s 2 in comparison with the second comparator 130 to compare the voltage V"2 of the detected voltage target level. The detection voltage V is expressed by:

V PPS\ V. PPS2

-xV when the detection voltage vppsl becomes small

When the PP voltage is vrel, the comparator 丨1() is fortunately out of the alignment apostrophe. When the voltage v is detected, the second comparator 130 outputs a high level signal. (4) is a block diagram showing the effect decoder for generating the time number ACT shown in FIG. The active decoder includes a command decoder 50, a memory bank control cry 60 and an address buffer and an address decoder 70. The command decoder 50 is connected to: and pps2 is smaller than the voltage v 89019 -1! - 1261843 to decode a chip select signal /CS, a column address strobe signal /ras, a row of address strobe signal /CAS and a write enable signal /WE to output a relative command signal CMD. Command signals include start, read, precharge, and reconfigure signals. The address buffer and address decoder 70 receives and decodes the address. The command signal CMD and the output signals of the address buffer and the address decoder are input to the memory bank controller 60. The memory bank controller 6 outputs an action signal ACT. The action signal ACT includes activation of each memory group, pre-charging of each memory group, reading of each memory group, and writing of each memory group. Figures 6c and 6d show block diagrams for illustrating the controller 200 shown in Figure 4. The circuit shown in FIG. 6c is used to activate the circuit shown in FIG. 6c when the pre-detection level signal detl_en is activated and before the target level signal det2-en is activated. A pump select signal pmp_sel 「 "reverse" gate NAND1 performs "reverse" (NAND) for the pre-detected level signal deti__en and a signal obtained by inverting the target level signal det2-en Operation. A "reverse" gate NAND2 performs a "reverse" (NAND) operation on the action signal ACT and a signal obtained by inverting the output signal of the "reverse" gate NANDI. If the action signal ACT is input when the pre-detection level signal detl_en is "鬲" level and the target level signal det2 - (3) is "low" level, the "reverse" gate NAND2 is activated. output signal. A latch latches the output signal of the "reverse" gate NAND2, and then outputs the latched signal as the pump selection signal pmp_sel. The purpose of the circuit shown in Figure 6d is to output an oscillator control signal sub_osc_el^osc-en in response to the active signal act and the pump selecting 89019, 1261843 signal pmp-sel. In the preferred embodiment shown in FIG. 6d, since the logical levels of the oscillating suppression signals sub_osc_en and osc-en are opposite to each other, the main _3 is operated when the second oscillator 31 〇 operates. 〇〇 will not work. However, in other specific embodiments of the present invention, reading the φTangtang crying T 々 Wang Zhen quo state 300 and the sub-oscillator 31 〇 can operate simultaneously. Input a plurality of pulses with different startup times to a multiplexed crying #. Each of the chunks (chunk i, group: 2, ..., chunk n) used to generate the plurality of pulses includes a delay circuit 211 (eg, an inverter chain delay of the delay circuit 2Η) The time is configured to be different according to the action signal act, and the salty state 2 is selected according to the action signal ACT and outputted from the blocks (block 1, block 2, . . . , the plurality of output signals of the block n) - 'so that the vibration control signal - (3) maintains the time in an active state, the action signal ACT varies. Since only the vibration control signal sub The sub-vibrator 310 outputs the ring signal when it is in the middle of the action, so the amount of charge extracted can be throttled according to the action signal ACT. Accordingly, in the voltage generator disclosed in the present invention, In the operation of the main pump, the auxiliary pump is operated to prevent the level of the driving voltage V卯 from excessively fluctuating. As a result, the noise that causes the driving voltage to fluctuate can be reduced. In addition, since Ik is driven to see the pressure 'smile Decrease so that the amount of charge to be extracted is decremented, so the drive is made The power required to maintain the voltage Vpp above the target level is reduced. Although the invention is susceptible to various modifications and alternatives, specific embodiments of the invention are shown by way of example in the formula 89019 - 13 - 1261843 And the present invention is not limited to the specific open y formula disclosed. However, the present invention covers all modifications, equivalents and alternatives, and is a genus; The spirit and scope of the present invention as defined by the scope of the patents is hereinafter referred to in the scope of the patents. [Simplified Description of the Drawings] ::: The non-limiting teachings of the present invention are specifically described by way of example. Reference will also be made to the accompanying drawings. Figure 1 shows a conventional voltage generator _. = and Figure 2: shows a circuit diagram for explaining a conventional voltage generator. A timing diagram of a port voltage generator. The method of the voltage generator according to the embodiment of the present invention (4) (4) The present invention - the voltage product of the embodiment: the circuit diagram of the detector shown by m:: m4. The block diagram of the acting decoder. 4 are not used to generate a letter of action Figure 6c of the ACT shows a block diagram for explaining the controller shown in Figure 4. 89019 -14- 1261843 [Description of Symbols] 10 Detector 210 Block 20 Oscillator 211 Delay Circuit 30 Control Driver 212 1 In contrast, (Nand) 40 pump 213 "Nand" gate 50 command decoder 214 multiplexer 60 memory group controller 300 main oscillator 70 address buffer and decoder 310 sub oscillator 100 detect Detector 400 main controller 110 first comparator 410 sub-controller 120 detection unit 500 main pump 130 second comparator 510 sub-pull 200 controller 600 voltage adder 89019, 15

Claims (1)

126^^^3386 Patent Application Replacement of Chinese Patent Application (October 94) Pickup, Patent Application Range: 1. A voltage generator comprising: a detector for comparing one of the voltage generators The output voltage is coupled to a first reference voltage and a second reference voltage lower than the first reference voltage to output a first sensing signal and a second sensing signal; a controller for receiving the first sense Measuring a signal, the second sensing signal and an action signal to output a first control signal and a second control signal; a booster for boosting a voltage in response to the first control signal; a booster for boosting a voltage in response to the second control signal: and a voltage adder for summing output signals from the secondary booster and the primary booster to provide the output voltage . 2. The voltage generator of claim 1, wherein the detector comprises: an induced voltage generator for dividing the output voltage to generate a first induced voltage and a lower than the first induced voltage a second induced voltage: a first comparator for comparing the first induced voltage with the first reference voltage to output the first sensing signal; and a second comparator for comparing the second induced voltage And the second reference voltage to output the second sensing signal. 3. The voltage generator of claim 1, wherein the controller comprises: an active detector for combining the first sensing signal and the second sensing signal to generate an output signal a latch for latching the output signal 1261843 from the active detector; and a controller for receiving an output signal from the latch and the active signal to output the first control signal. 4. The voltage generator of claim 3, wherein the sub-controller comprises: a plurality of pulse generating blocks, each pulse generating block outputs a pulse 'in response to the action signal and from the latch The output signal; and a multiplexer for selecting a pulse among the plurality of pulses in response to the active signal to output the selected pulse as the first control signal. 5. The voltage generator of claim 4, wherein the pulse generating block comprises: a first computing component configured to perform a "reverse" on the output signal from the latch and the action signal (NAND) operation; a delay circuit for delaying an output signal from the first computing component by a predetermined time according to the action signal; and a second computing component 'for targeting from the first computing component The output signal and an output signal from the delay circuit perform a "NAND" operation. 6. The voltage generator of claim </ RTI> wherein the main booster comprises: a vibrator for outputting an oscillating signal in response to the second control signal; 89019-941007.doc -2- 1261843 a control driver for decoding the oscillating signal to output a plurality of capacitor precharge signals and a plurality of charge transfer signals; and a pump circuit for charging the plurality of capacitors in response to the plurality of capacitor precharge signals, And extracting the charge stored in the capacitors to boost the output voltage in response to the plurality of charge transfer signals. 7. The voltage generator of claim 1, wherein the sub-booster includes: an oscillator for outputting an oscillating signal in response to the second control signal; and a control driver for decoding the oscillating signal And outputting a plurality of capacitor precharge signals and a plurality of charge transfer signals; and a pump circuit for charging the plurality of capacitors in response to the plurality of capacitor precharge signals and extracting the charge stored in the capacitors The output voltage is boosted in response to the plurality of charge transfer signals. 8. The voltage generator of claim 1, wherein the detector further compares the output voltage with a third reference voltage greater than the first reference voltage to output a third sensing signal; and the controller Further receiving the third sensing signal and the action signal to output a third control signal; further comprising a second sub-supercharger for boosting a voltage in response to the third control signal, and wherein the voltage adder The output signals from the secondary booster, the second secondary booster, and the primary booster are summed, 89019-941007, doc 1261843 to provide the output voltage. 9-- a method for generating - having an output voltage for reducing noise, comprising: receiving an action signal; generating a first voltage when the voltage of the wheel is small, a voltage of ^4z. i &quot;, 罘 reference voltage The signal is responsive to the active signal; when the output voltage is less than a second reference % voltage lower than the first reference voltage, generating a second voltage signal responsive to the active signal; and the first voltage signal and the first The two voltage signals are summed to produce the output voltage. The method for generating an output voltage having reduced noise, as in claim 9, further comprising generating a first The three voltage signals are responsive to the active signal; wherein adding the first voltage signal and the second voltage signal further adds the second voltage signal to generate the output voltage. 11 . The method of claim 9 for generating an output voltage having reduced noise, further comprising: dividing the output voltage to generate a first, induced voltage and a lower than the first induced voltage Comparing the first induced voltage with the first reference voltage, and generating the first sensing signal in response to the comparison result; and comparing the second induced voltage with the second reference voltage, and generating the The second sensing signal. H A voltage generator comprising: 89019-941007.doc 1261843 a first voltage sub-supercharger configured to provide a first voltage signal when the output voltage is less than a first reference voltage; a voltage converter configured to provide a second voltage signal when the output voltage is less than a second reference voltage lower than the first reference voltage; and a voltage adder configured to the first voltage The signal and the second voltage signal are summed to provide the output voltage. 13. The voltage generator of claim 12, further comprising a second voltage sub-booster configured to provide when the output voltage is less than a third reference voltage that is higher than the first reference voltage a third voltage signal; and wherein the voltage adder is configured to add the first voltage signal, the second voltage signal, and the third voltage signal to provide the output voltage. 89019-941007.doc