TWI261359B - Method for forming a complementary metal-oxide semiconductor thin film transistor - Google Patents

Abstract

A method for forming a complementary metal-oxide semiconductor thin film transistor (CMOS TFT) is provided. Firstly, a first TFT and a second TFT that have not been treated with source/drain doping processes are formed on a substrate. Then, the first TFT is doped with dopants of a first conductive type so as to form a source and a drain of the first TFT. Subsequently, a high pressure anneal is performed to repair crystal defects in the first TFT and the second TFT. Finally, the second TFT is doped with dopants of a second conductive type so as to form a source and a drain of the second TFT.

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of fabricating a thin film transistor, and more particularly to a method of fabricating a complementary metal-oxide semiconductor thin film transistor (CMOS TFT). The prior art has been widely used in notebook computers, personal digital assistants (PDAs), etc. because of its thinness, low power consumption, and no radiation pollution. Information products. Most of the current TFT-LCDs use a complementary thin film transistor (CM〇s TFT) process technology to integrate a standard driver integrated circuit (丨C) on the liquid crystal display panel, thereby reducing the size of the display, Reduce production costs and reduce module processing time. Please refer to FIG. 1 to FIG. 3 . FIG. 1 to FIG. 3 are not intended to fabricate a complementary thin film transistor 10 . As shown in FIG. 1, an amorphous layer (not shown in FIG. 1) is first formed on a glass substrate 12, and then the amorphous layer is subjected to a tempering process, such as a quasi-molecular laser annealing ( The excimer laser annealing (ELA) process causes the amorphous germanium layer to recrystallize into a polycrystalline layer (not shown in Figure 1). Subsequently, a photolithography and etching process is performed on the polysilicon layer on the glass substrate 丨2.

Page 6 1261359 V. DESCRIPTION OF THE INVENTION (2) A plurality of patterned polycrystalline germanium (p a 11 e r n e d ρ ο 1 y s i 1 i c 〇 n ) layers 14 4 and 16 are formed. In addition, the tempering process can also be performed after the lithography and engraving process, and a buffer layer (not shown in FIG. 1) can be additionally formed between the glass substrate 12 and the amorphous layer to protect the back. After the fire, the polycrystalline stone layer does not contaminate the impurities of the glass substrate, and the glass substrate 12 is prevented from being damaged by the tempering and etching process.

By ^, as shown in FIG. 1, a low temperature deposition process is performed to form a gate insulating (GI) layer 18 overlying the patterned/crystalline fossils "14 and 126; The material of the gate insulating layer 18 may be a dioxygen layer or a nitrogen-phosphorus. Then, a gate electrode is formed on the gate insulating layer 18, and then the conductive layer is lithographically etched and electrically conductive 14#, respectively, a gate is formed thereon, and then a gate is formed. Ξ Ξ ΐ ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' And on the two sides of the gate conductive layer 22, if two form a gambling source 16s, an N-type U pole, and a 匕 1 〇 〇 〇 17 , , , , , , , , , , , , , , , , , , , , , , , , , , , Electrical t and N-type thin film t 4曰骐 transistor i〇b, and P-type thin germanium transistor

1 〇. The electric raft body 10 b is a conventional complementary film 曰 1 〇a 2 , electric Japanese body 1261359

In addition, since the patterned polysilicon layers 14 and 16 themselves contain a large number of crystal defects, and in the ion doping process described above, the patterned polysilicon layers 14 and 16 are patterned. And the gate insulating layer 18 will cause lattice defects to be generated by ion bombardment, which may cause electrons to be trapped in the defect and affect the normal operation of the complementary thin film transistor. Therefore, as shown in FIG. 3, in order to repair the aforementioned lattice defects, the conventional method is to perform the above-mentioned all ion doping processes, and then simultaneously perform the p-type thin transistor 10a and the N-type thin film transistor 10b. A high pressure anneal (ΗΡΑ) process is used to repair the lattice defects in the patterned reticular layer 14 and 16 and the gate insulating layer 18. Generally, the high temperature and high pressure tempering process is to pass a suitable gas 30' under high temperature and high pressure, and the gas molecules of the gas 30 will generate bonds under high temperature and high pressure, and the high temperature and high pressure will drive the broken key. The gas particles diffuse into the patterned germanium layer 14 and 16 and the gate insulating layer 18 to fill the dang 1 ingb ο nd of the crystal sample, thereby achieving the effect of repairing the crystal defects. 0 However, since P-type thin film transistor 丨〇a and N-type thin film transistors are doped with different kinds of doping ions, different doping ions are different for the high temperature and high pressure gas systems provided by the fire process. The reaction ^ $ back In general, in the high-pressure tempering process, if the p-type film is selected. 1 有利a favorable gas and process conditions, tend to reduce the repair effect of the N-type film (5) 曰 body body 10 b, and vice versa, if the choice of n-type thin 臈 transistor crystal gas and process conditions, it will reduce the confrontation Type thin film transistor 1

1261359 V. Description of the invention (4) The repairing effect reduces the repairing efficiency of the high-pressure tempering process. SUMMARY OF THE INVENTION It is an object of the present invention to provide a method of fabricating a complementary thin film transistor to solve the aforementioned problems.

According to an aspect of the present invention, in a preferred embodiment of the present invention, first, a first thin film transistor and a second thin film transistor doped with a source and a drain are formed on a surface of a substrate, and then a first thin film transistor is formed. a dopant of a first conductivity type is doped in the first thin film transistor to form a source and a drain of the first thin film transistor, and then performing a high voltage tempering process to repair the first thin film transistor and A lattice defect of the second thin film transistor is finally doped into a second thin film transistor to form a source and a drain of the second thin film transistor.

Since the present invention performs the high-voltage tempering process after completing the fabrication of the source and the drain of the first thin film transistor, the source and drain of the second thin film transistor are finally completed. Therefore, the present invention can adjust the pressure of the high-pressure tempering process, the temperature, and the gas used in the process according to the characteristics of the doping ions of the first conductivity type, thereby improving the performance of the high-pressure tempering process. Implementation

Page 9 1261359 V. Description of the Invention (5) Please refer to FIG. 4 to FIG. 10, which are schematic diagrams of the method for fabricating the complementary thin film transistor 40 of the present invention. As shown in FIG. 4, a substrate 4 2 is first provided, which may be a glass substrate or a quartz substrate, and the substrate 42 includes a P-type thin film transistor region 42a and an N-type thin film transistor region 42b. Next, an amorphous germanium layer (not shown in FIG. 4) is formed on the substrate 4 2 , and then the amorphous germanium layer is subjected to a tempering process, such as a pseudo-molecular laser annealing process, so that the amorphous germanium layer is recrystallized. A polycrystalline layer (not shown in Figure 1). Subsequently, a photolithography and etching process is performed on the polysilicon layer to form a plurality of patterned polysilicon layers 4 4 and 46 on the substrate 42. In addition, a buffer layer (not shown in FIG. 4) may be formed between the substrate 42 and the amorphous germanium layer to protect the tempered polysilicon layer from impurities of the glass substrate and avoid the substrate 4. 2 Damaged by the tempering process and the etching process. Alternatively, the tempering process can be performed after the lithography and etching process. As shown in FIG. 4, a low temperature deposition process is performed to form a germanium dioxide layer or a tantalum nitride layer over the patterned polysilicon layer 44, 46 and the substrate 4 2 for use as a gate. The pole insulating layer 48. Subsequently, a conductive layer (not shown in FIG. 4) is formed over the gate insulating layer 48, and a lithography and etching process is performed on the conductive layer to respectively form the patterned germanium layers 44 and 46. The gate conductive layers 50 and 52 are formed, and the conductive layer may be composed of aluminum, titanium, molybdenum (Mo), tungsten, tantalum (Ta), doped polysilicon or the like.

Page 10 1261359 V. Description of invention (6)

As shown in FIG. 5, a lithography process is performed to form a patterned photoresist layer 54 overlying the P-type thin film transistor region 42a. Thereafter, a plurality of ion implantation processes are sequentially performed to form an N-type source 4 6 s and an N-type in the patterned polycrystalline layer 4 6 on both sides of the gate conductive layer 52; The fabrication of the N-type thin film transistor 40b is completed by 4 6 d, and two N-type lightly doped gates 4 7 'finally using the solvent to remove the patterned photoresist layer 5 4 '. In addition, there are many methods for forming a \-type source 4 6 s, an N-type dipole 4 6 d, and an N-type light doping; and a pole 4 7 , one of which may first utilize the gate conductive layer 52 as a Masking and performing an ion implantation process, and forming two N-type light-changing > and poles 4 7 in the polysilicon layer 4 6 on both sides of the gate conductive layer 52, and then using a patterned light A resist layer (not shown in FIG. 5) is overlaid on the N-type lightly doped gate 4 7 and the gate conductive layer 52, and then an ion implantation process is performed to form an n-type source 4 6 s and The N-type immersion 4 6 d 'final' is followed by an activation process to move the dopant ions to the correct lattice position.

As shown in Fig. 6, a high-pressure tempering process is performed to pass the gas 60' at high temperature and high pressure to repair the lattice defects in the patterned polycrystalline quartz layer 4 4, 4 6 and the gate insulating layer 48. . In the high-pressure tempering process of the present invention, the operating pressure is between 5 and 20 atmospheres, the operating temperature is between 3 〇〇 ° c and 600 00, and the gas 60 can be water and gas. (h2〇), nitrogen (N 2 ), or ammonia (NH 3) exclusively, and the processing time is between 30 minutes and 2 hours. It should be noted that the present invention is based on the high-pressure tempering process to repair the lattice defects after the N-type thin film transistor 40 b is completed. Therefore, the present invention can be replaced by the N-type.

1261359 V. INSTRUCTIONS (7) Characteristics of hetero ions, adjusting the pressure, temperature and gas used in the high-pressure tempering process to more effectively repair the patterned polysilicon layer 4 4, 46 and the gate insulating layer Lattice defects within 48. In addition, a thin oxide layer (not shown in FIG. 6) may be selectively formed over the substrate 4 2 to protect the gate conductive layer 5 0, 5 2 and the gate before the high-pressure tempering process is performed. Pole insulating layer 58. Next, as shown in FIG. 7, a patterned photoresist layer 56 is formed over the N-type thin film transistor 40b by a lithography process. Then, an ion implantation process is performed to form a P-type source 44s and a P-type drain 44d in the patterned polysilicon layer 44 on both sides of the gate conductive layer 50, and finally use a solvent to pattern The photoresist layer 56 is removed and an activation process is performed to move the dopant ions to the correct lattice position, so that the fabrication of the P-type thin film transistor 40a is completed. As shown in FIG. 8, an interlayer dielectric (ILD) 58 is formed on the substrate 4 2 by a chemical vapor deposition process, and the interlayer dielectric layer 58 may be a nitride layer or It is formed by stacking a layer of germanium dioxide and a layer of tantalum nitride. Then, a heat treatment process may be further performed to drive the hydrogen ions in the tantalum nitride layer in the interlayer dielectric layer 58 to diffuse into the patterned polysilicon layer 44 and fill up the ion implantation process. Lattice defects. In addition, in other embodiments of the present invention, a plasma processing process may be performed to fill the lattice defects in the P-type thin film transistor 40 a with plasma, and then use a chemical vapor deposition.

Page 12 1261359 V. Description of the Invention (8) The process is to form an interlayer dielectric layer 58 on the substrate 4 2 .

Subsequently, as shown in FIG. 9, a patterned photoresist layer (not shown in FIG. 9) is formed on the glass substrate 4 2, and an anisotropic dry etching process is performed, for example, using carbon tetrafluoride (CF 4 ). The plasma is subjected to a dry etching process to remove the interlayer dielectric layer 5 8 not covered by the patterned photoresist layer to form a plurality of access sources 4 4 s, 4 6 s and drain electrodes 4 4 d, 4 6 Contact hole 62 of the d surface, and then the patterned photoresist layer is removed using a solvent. Then, as shown in FIG. 10, a conductive layer (not shown in FIG. 10) is formed on the interlayer dielectric layer 58, and the conductive layer is filled in each contact hole 62, and finally a lithography and etching is performed. In the process, a wire 64 is formed in each contact hole 62, and each wire 64 is used to electrically connect the p-type thin film transistor 40a, the N-type thin film transistor 40b and other electronic components. In general, since the transfer carrier of the N-type thin film transistor 40b is an electron' and the sensitivity of electrons to lattice defects is high, the N-type thin film transistor 40b usually has a poor electrical performance. Therefore, in the method for fabricating a complementary thin film transistor of the present invention, the present invention first completes the fabrication of the N-type thin film electrode 40b, and then performs a high-pressure tempering process to repair the patterned ruthenium layer 4 4 . 4 6 and the lattice defects in the gate insulating layer 48, and finally the fabrication of the P-type thin film transistor 40a is completed. In this way, the method of the present invention can not only improve the repairing performance of the high-pressure tempering process, but also increase the electron mobility of the thin-film transistor to 100 cm 2 /V-Si^, and make the P-type thin film transistor and N Voltage difference of the starting voltage of a thin film transistor

1261359 V. Description of invention (9) Reduced to less than 2V. It should be noted that the present invention can also complete the fabrication of the P-type thin film transistor 40 a, and then perform a high-pressure tempering process to repair the patterned polysilicon layer 4 4 , 4 6 and the gate insulating layer 4 8 . The lattice defect inside, and finally the fabrication of the thin film transistor 40b. Compared with the prior art, the present invention is performed after the source and the drain of the first conductivity type thin film transistor are completed, and a high voltage tempering process is performed to repair the lattice defects, and finally the second conductive type is fabricated. The source and drain of the thin film transistor. Therefore, the present invention can adjust the pressure, temperature and the gas used in the process according to the characteristics of the doping ions of the first conductivity type to more effectively repair the patterned polysilicon layer and the gate insulating layer. The lattice defects inside can improve the performance of the high-pressure tempering process. The above are only the preferred embodiments of the present invention, and all equivalent changes and modifications made to the patent scope of the present invention should fall within the scope of the present invention. .

Page 14 1261359 Brief Description of the Drawings Brief Description of the Drawings Figures 1 to 3 are conventional methods for fabricating complementary thin-film transistors 10 τ] Intended Figures 4 to 10 are the inventions. The secondary method of crystal 40 is not intended. Symbols of the figure: 10 complementary thin film transistor 10a Ρ type thin film transistor 10b N type thin film transistor 12 glass substrate 14 patterned polycrystalline germanium layer 14s Ρ type source 14d P type drain 16 patterned polycrystalline layer 16s N-type source 16d Ν-type drain pole 17 N-type lightly doped drain electrode 18 gate insulating layer 20 gate conductive layer 22 gate conductive layer 30 gas 40 complementary thin film transistor 40a P-type thin film transistor 40b Ν type Thin film transistor 42 Substrate 42a Ρ-type thin film transistor region 42b N-type thin film transistor region 44 Patterned polysilicon layer 44 s P-type source 44d Ρ-type drain 46 Patterned polysilicon layer 46s Ν-type source 46d N-type drain 47 Ν type lightly doped immersion 48 gate insulation layer 50 gate conductive layer

Page 15 1261359

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Claims (1)

1261359 VI. Patent Application Range 1. A method for fabricating a complementary thin film transistor, the method comprising the following steps: forming an unfinished source and a drain doped with a first thin film transistor and a first surface on a substrate surface a thin film transistor; doping a first conductivity type dopant into the first thin film transistor to form a source and a drain of the first thin film transistor; performing a high pressure anneal process And repairing a lattice defect of the first thin film transistor and the second thin film transistor; and doping a dopant of a second conductivity type into the second thin film transistor to form a rite; The source of the thin film transistor is > and the pole. 2. The method of claim 1, wherein after forming the source and the drain of the second thin film transistor, the method further comprises: forming an interlayer dielectric layer on the substrate and covering the first a thin film transistor and the second thin film transistor; forming a plurality of contact holes in the interlayer dielectric layer, the contact holes respectively reaching the source and the drain of the first and the second thin film transistors; And filling a conductive layer in the contact holes. 3. The method of claim 2, wherein the interlayer dielectric layer comprises a nitrogen layer. Page 17 1261359 VI. Scope of Application Patent 4. The method of claim 3, wherein the interlayer dielectric layer further comprises a layer of oxidized layer covering the layer of nitrogen. 5. The method of claim 4, wherein the method further comprises: performing a heat treatment process to drive hydrogen ions in the tantalum nitride layer to fill the lattice defects in the second thin film transistor. 6. The method of claim 2, wherein the method further comprises: performing a plasma treatment process to repair the lattice defects in the second thin film transistor. 7. The method of claim 1, wherein the method of forming the first source and the second thin film transistor with the uncompleted source and drain doping comprises the steps of: forming a first a patterned polycrystalline stone (pa 11 ernedp ο 1 ysi 1 ic ο n ) layer and a second patterned polycrystalline layer; a gate insulating layer (GI) layer is formed on the substrate, And covering the first patterned polysilicon layer and the second patterned polysilicon layer; and the surface of the gate insulating layer above the first and the second patterned polysilicon layer respectively Forming a first gate conductive layer and conducting a second gate. 8. The method of claim 1, wherein the high pressure tempering is performed Page 18 1261359 6. Prior to the application of the patent range process, the method further includes: forming a protective layer over the first thin film transistor and the second thin film transistor to protect the first thin film transistor Two thin film transistors. 9. The method of claim 7, wherein the gate conductive layer is a metal layer. The method of claim 7, wherein the gate conductive layer is composed of doped polysilicon. 1 1. The method of claim 1, wherein the gas system used in the high pressure tempering process comprises water gas (Η 20), nitrogen (N 2 ), or ammonia gas (ΝΗ3) 〇 1 2 . The method of claim 11, wherein the operating pressure of the high pressure tempering process is between 5 and 20 atmospheres, and the operating temperature is between 300 and 600 degrees. The processing time (pr 〇cessingtime ) is between 30 minutes and 2 hours. The method of claim 1, wherein the substrate is a glass substrate or a quartz substrate. The method of claim 1, wherein the first conductivity type is an N-type conductivity type, and the second conductivity type is a P-type conductivity Page 19 1261359 Page 20