1260756 九、發明說明： 【發明所屬之技術領域】 本發明係有關一種埋入式晶片之散熱結構及其製 去尤拍種應用整合於電路板中之埋入式晶片之散熱結 構及其製法。 【先前技術】 匆為滿足在電子產品輕薄短小、多功能、高速及高頻化 =趨勢，必須強化電子元件積集化、高速處理化、小型輕 二化舁回速處理化等功能，故而印刷電路板（pCB)或積 妝電路（ic)封裝底板技術已朝向細線路及小孔徑發展。 目前，印刷電路板或1C封裝底板製程已從傳統100_以 t ^ ^路尺寸（包括導線寬（Line Width)、導線間距（SPace) ”覓匕（Aspect lat10))降至約30μιη，並朝更小之線路精 度進行研發。 同時，隨著電子產品朝向高功能性與小型尺寸之發层 趨勢，電路板的疊層（LaminatiGn)技術也就必須具備厚^ 缚、多層數與高密度之特點，於是發展出鑲埋有被動元件 、 夕曰日片之夕層電路板，以更進一步縮小電路板空間 然而’當電子產品需求之操作頻率越來越高以及晶片 越，越夕¥ ’伴隨晶片而來之熱能亦越來越高，而須解決 與散熱有關之問題。 以在，係以例如為環氧樹脂（Epoxy resin)、聚乙醯胺 (Polymude)、亂脂（Cyanaie &叫、破璃纖維⑹㈣别灯）、 17811 5 1260756 雙順丁烯二酸驢亞胺/三氮_τ，加也幻 或混合環氧樹脂與玻璃纖維（FR5)等材質所製成之底板來 承載晶片’並提供晶片散熱之用，如美國專利第6，如州 號案即在底板及/或加強板頂面上安置Ic晶片。， 但，由於底板之導熱能力較差，且晶片係由底板所間 隔開，而令晶片之熱能傳遞有著相當高之阻力 ^Theta-JB) ’導致無法將熱能自疊層之電路板中逸散出 。·而且’底板與Ic晶片之熱膨脹係數（cte)之不匹配 ismatch) ’而令熱應力加諸於1(：晶片與銲球上，而令 勹罪度降低。 片愈真用於打線接合之散熱板上的缺口將減少圯晶 邊緣：熱連接’造成熱能限制於IC晶月與底板黏 者之&域，而在底板周邊區域則無法有效散埶。 不敷：用單载晶片之底板本身進行散熱之方式已 便用而有了下列之解決方式。 底部m,’有人提f增設較多之鲜球至1α片下的《 样_又 以由5亥等銲球將熱能傳導出去。鈇而，这 :將=以的銲球，令成本隨著録球之數量而增II 人提出—種整合散熱件於底板中之結構及製法， =熱空間’如美國專利第6,706 ， = 熱件將增大電子元件之體積，並不利疋 口口輕溥短小之趨勢。 展 造業r產般,首先由晶片承载件製 、月且衣置之晶片承載件（如底板或 17811 1260756 導線架）之後，再將該些晶片承載件交由半導體封裝業者 ，行置晶、模壓、以及植球等製程，最後，方可完成客·戶 需之電子功能之半導體裝置。由於其間涉及不同製程 菓者（即，包含有晶片承載件製造業者與半導體封裝業 ^)’因此，上述習知技術於實際製造過程中，不僅步驟繁 “，二面一不易°況^ ^客戶端欲進行變更功能設計 牽涉變更與整合層面更是複雜，亦不符合需求佈局 上之變更彈性與經濟效益。 因此’#於上述之問題，如何避免習知技術所造成之 問題，以解決成本提高、以及可靠度與散熱效率 寺問題者’實已成目前亟待探討之課題。 【發明内容】 提供馨Γ上所述f知技術之缺點，本發明之主要目的在 式晶片之散熱結構及其製法，俾使晶片上所 熱ΐί 為有效擴大散熱面積之散熱結構，以提升散 之气Ιΐί上揭及其它目的’本發明提供一種埋入式晶片 月丈产、、、、、σ構及其製法。 一且=發Γ之埋入式晶片之散熱結構之製法中，首先提供 第二：二弟面與一第二表面之晶圓，其中，該晶圓之 非主動面糸:::曰，主動面’該晶圓之第二表面係為晶圓之 牛π中於该晶圓之第一表面形成一外接金屬層。於此 擇:：二， 曰口之母個預疋切割為晶片之電性連 1781] 1260756 接墊::成有對應之外接金屬層。 r f 將形成有該外接金屬層之晶圓之第一表面接置 ^入=反。於此步驟前，係可選擇先於該晶圓之第一表面 上全面形成一纟士人 由該結合層將：：二！結合層係覆蓋該外接金屬層，以 y 曰曰0之弟一表面接置於該底板上。 之後’於該晶圓夕馀 擇於該晶圓之第表面形成一晶f導熱層。可選 ，呈，以於道(_一 盲孔，並於該晶圓區域中形成複數個 熱層。其中，可選擇 ，之後將該晶圓磨薄，以提昇散熱效率。 下來私除该底板，並將該晶圓切判為彳f意 片，以將該複數個晶片置入 二彻數個晶 可於該電路板中整合該晶片。'路板之開口中。如此，便 知後，進行壓合與開口作業。於此牛 ^ 於該電路板上下表面上屋合形成一絕緣層:、，，係可選擇 孔技術、曝光顯影方式或電漿银刻方式^亚利用雷射鑽 表面上之局部絕緣層，俾使該絕緣層=有移除該電路板 及局部晶背導熱層而形成，藉：外接金⑽ 墊部分以及局部晶背導熱層。 出4曰曰片之電性連接 金二導熱層，形成一 片散熱結構’賴散熱結構係以心=== 17811 I260756 將該晶片所產生之熱能傳導出去。 由於本發明係將晶片直接埋入於電路板中，並且形成 2連接晶片之晶料熱層所形成之晶片散熱結構供傳導熱 故可解決習知技術中因底板之導熱能力較差、以及底 =對晶片之熱能傳遞所產生之高阻力所導致之熱能無法逸 :文2缺失，且無底板與IC晶片之熱膨脹係數之不匹配而令 可罪度降低之問題。 :然’可選擇於該絕緣層上形成有防銲層（soIder 個Li該防鮮層定義有複數個防薛層開口，以由該複數 壯開口外露出該金屬導線層及該散熱層以供與外界 可且古#田’、、、：若"亥放熱層未覆有防銲層而與空氣接觸， 業1 =佳散熱效果。或者，重複進行包括壓合與開口作 成一以及於該外接金屬層及該晶背導熱層上分別形 孟蜀導線層及一散熱層之步驟之增層作業。 姓=’便可使該金屬導線層及該散熱層能夠與外界連 :板單t切單作業後，便可得到複數個歲埋有晶片之電 雕曰 可矣，δ亥埋入式晶片之散熱結構包括至少一半導 脰曰曰片、—形成於各該晶片主動面 形細:晶片非主動面之晶背導熱層。W -導：：片非主動面係具有複數個盲孔供覆蓋形成該晶 晶片1其中，各該盲孔之深度可選擇為小於或等於該 :二而該晶背導熱層則包括-第—導電層以及一 卜導電層之第一金屬層’其中該第-導電層形成 17811 9 1260756 於°亥曰_曰圓之第二表面上與各該盲孔表面。 路板门二:::月:提供-種具備上述晶片散熱結構之電 曰ΰ '路板包括：至少-開口設於電路板中；至少― : 曰片，且該晶片具有一主動面與一 電，1口中，外接金屬層，形成於各該晶;= 形成於各該晶片加 德再=非主動面之電路板表面，以覆蓋晶背導熱層，之 個絕緣層開口；以及一散熱層，至少形成於 =:::¥熱層上絕緣層之部分表面及該絕緣層之開口中， =^散熱層使該晶料熱層與外界相連，可將該晶片 :紅作期間所產生之熱能傳導出去。 ^發明於職熱結構中，亦可以另—絕緣層形成於該 :曰曰片主動面之電路板表面以覆蓋該外接金屬層，且該絕 ，層對應之外接金屬層表面具有複數個開口；以及一金屬 ㈣層’至少形成於該外接金屬層上之絕緣層開口中，俾 藉由該金屬導線層與外接金屬層相連。 :各該晶片與各該電路板之開口間之縫隙中係填充 有4占著di ’以將各该晶片固定於該電路板之開口中。該散 熱層可選擇延伸連接至少—晶片之晶背導熱層，以將埋藏 於该電路板中之晶片加以連接。 由於晶片本身所形成之散熱結才冓可確實將操作期間 所產生之熱能由散熱導線傳導出去，不僅可擴大散熱面 積，更可有效率地進行散熱，故可解決f知技術中僅倚靠 承載晶片之底板本身進行散熱之缺失’且無習知技術中增 17811 1260756 加銲球數量及整合散敛 VI ^ - 之成本、佈局及體積拇去# 式二错由特定的具體實施例說明抑明:問題' 式，熟習此技藝之人士 '月之霄施方 昤魅*代 可由本說明書所揭示之内六, ::本备明之其他優點與功效。本發 ：：輕易地 的具體實施例加以施行或應用，本說明=其他不同 可基於不同觀點與瘅 曰中的各項細節亦 種修飾與變更。 予雕不毛月之精神下進行各 【實施方式】 非以下之實施例係進—步詳細說明本發明之觀點/ 非以任何觀點限制本發明之範·。 …點’但並 請參閱第！至第1〇圖，係 散熱結構及其製法之示意圖。 入式S曰片之 如弟1圖所示，孫接板—曰ΓΠ -表面U與一第、、圓卜該晶圓1具有-第 弟—表面13，該第一表面11例如定義為主 二表面13則例如定義為非主動面。於該晶圓 昂-表面η之複數電性連接墊上，係藉由例如複數個 氐。ρ金屬化製程形成外接金屬層丨i工。 所謂底部金屬化製程係指利用諸如濺鍍技術 (SpUttedng)、蒸鍍技術（EvaP〇ratl0n)、及電鍍技術 (Plating)等方法，於該晶圓1上進行製程，以由諸如錄-金-銅、鈦-銅、鈦-鎳釩-銅或其他適當成分之金屬疊合形成 例如包括複數個電性連接墊之外接金屬層ηι。其中，由 於濺鍍技術、蒸鍍技術、及電鍍技術等方法皆為習知技術， 故省略其說明。 17811 11 1260756 雖本κ知例中係形成有由兩個半導體元件以及四個 .又方、肩等半導體兀件間之盲孔為例說明者，然而，應了解 的疋，本發明可以多種形式實施之，所述内容及圖式係為 本ι明之較佳貫施例，而非用以限制本發明之範圍，合先 敘明。 / 、如第2圖所示，係於該晶圓丨之第一表面u上全面 瓜成結合層5，該結合層5覆蓋該外接金屬層⑴，以由 #結合層5將該晶圓之第—表面丨丨接置於諸如藍寶石板材 ^曰板或其他底層貼片（Tape )上。此時，係可選擇將 口亥曰曰圓1磨薄，以提高該晶圓ι之散熱效率。其中，該结 合層5可選擇為一液能 、 合 、夜心既（Wax)層，由於液態蠟遇高溫 ^ 低，里日守則會固化，故而有助於固定該晶圓1 ;w & f 3上，且亦易於日後剝離該底板3。 如弟3圖所示，俾於命曰 曰北 係於。亥日日SI 1之弟二表面13上進行 :二:二;以: 定切割為晶片似：中段至η，線段間之區域即為預 .(、〃之5域。其中，各該晶背盲孔131之深度可 ’…於或寺於該經磨薄之晶圓1/晶片之深度。 料實施例所形成之各該盲孔131係等於 日日® 1之深度，而達外 i /辱之 備深達該第-表面之、、果；4 層之深度者（即，具 熱通道之面产ίΓΓ 本實施例後續形成之散 度及寬卢^ 須注意的是’各該盲孔⑶之深 同時，於本實施例中，_===他變化或修改。 于k擇使用例如微影蝕刻之方 17811 12 1260756 式形成各該盲孔131。當然，亦可選用苴他 成各該盲孔131，而非以此為限。由於”二=式形 理及作則具為習知者，故於此不再為文贅述_方式之原 如第4圖所示，係於該晶圓丨之第二= 該盲孔131中形成-晶背導熱層133。二面13上及各 包括一第一導電層咖、以及藉由電錄=月=層⑴ 所形成之覆蓋於該晶圓i之第二表面 、屯層1332 中之第一金屬層133b。其中，該第 居、“亥目孔13! 於該晶圓1之第二表面13上與各該盲 為一諸如鈦（Ti) /銅（Cu)或導恭古八 且可例如 層(Seed layer)’該第一金屬層心：；：：::之晶種 所形成之銅層或金層，當然亦可選擇 :〇电鑛銅或金 金屬材質鑛覆。 、一蛤无、效果較佳之 同時，由於該第一導電層133a及該第 %金屬結構，故可為晶背之良好散熱 曰 如第5圖所示，係、自該晶圓】 該底板3，而留下該外接金屬層！〗1 义 上剝離 實施例中，可採用諸如加敎之;^ =於該晶圓卜於本 合層5炫融揮發。#然 ^ 7例如為液態虫襄之結 底板、埶水、酸、容、夜於^底板3之材質以加熱該 板3。 夂冷液、驗溶液或其他適當方式來移除該底 切割Π:?示’係將完成上述積體電路製程之晶圓^ 為萨數：” 1〇。其中，將該晶圓1以預定區域切割 讀個晶片1〇之技術均為習知者，故不多作說明。 17811 13 1260756 山士 ♦ 7A及㊉7B圖所示，係將該複數個晶）W0分別 ::電路板（c_itboard)7中，其中，該晶片10具備 /接&屬層111以及該晶背導熱層。該電路板7係 =先形成有複數開口 71’各該開π 71係略大於各該晶片 十， 〇 μ日日片1 〇。其中，本實施例係以注入黏著 、：9於各忒晶片10與電路板7之開口 71間之縫隙中，經 作業後’藉由例如為熱固性材質之液態膠將該晶片！ 〇 固定於該電路板7巾。其中，該黏著劑9可例如為液態膠 (Glue)或其他膠黏性較佳材料所製成。 此日寸，该電路板7係具有複數個整合於其中之晶片 〇形成於各该晶片丨〇主動面之外接金屬層丨丨卜以及形 成於各该晶片1〇非主動面之晶背導熱層133，而於各該晶 片10與>開口 71間之縫隙中係由該黏著劑9所精確固定者。 如第8圖所示，於該整合有晶片1〇之電路板7上下 表面上分別以例如壓合方式形成一絕緣層73。利用例如雷 射鑽孔、曝光顯影或電漿蝕刻等開口技術，可移除該電： 板7上下表面上局部之絕緣層乃，俾使該絕緣層73形成 有複數個絕緣層開口 731，而該等絕緣層開口 731係例如 對應於該晶片10之外接金屬層Π1(例如電性連接墊位置） 以及局部晶背導熱層133,藉以外露出該晶片1〇之外接金 屬層111以及局部晶背導熱層133。其中，該絕緣層乃可 為非纖維之樹脂型材料，例如ABF(Ajinomoto Build-up Film)或聚丙烯（pp )，亦或纖維含浸樹脂材料，例如為雙 順丁烯一酸醯亞胺/三氮阱（BT，Bismaleimide…犯丨加）加玻 17811 14 1260756 璃纖維或混合環氧樹脂與麵纖維（FR4)等或感光絕緣層。 准’當利用雷射鑽孔技術時，復需進行除膠渣 (:,叫作業，以移除_孔所殘留於該複數個絕緣層 膠m如該絕緣層73係採用光感應絕 則可湘曝光、顯料方式形成有該複數個絕 緣層開口川’其後復需進行除渣滓（De_s_)作業，以移 除因蝻影所殘留於該複數個絕緣層開口 731内之渣滓。 如第9圖所示，經圖案化線路製程後，形成金屬導線 -以及散熱層。於本實施例中’係以例如電鍍、無電電鍍、 物理沉積、化學沉積或其他適當方式，至少於該外接金屬 層m上之各該絕緣層開口 731中形成金屬導線層別； 而該局部晶背導熱層133下，則形成連接晶f導熱層i33 的散熱層735。 此日守"亥电路板7係具有整合於複數個埋入其中之晶 片1〇、形成於各該晶片10主動面之外接金屬層u卜形成 於各該晶片1G非主動面之晶f導熱層133、局部形成於該 夕曰卜：金屬们"上之金屬導線層733、以及局部形成於該 晶背導熱層133之散熱層73”且該散熱層735係可選擇 k伸連接至少兩相鄰晶片丨〇之晶背導熱層1 3 3。當然，該 散熱層735以可連接一個或兩個以上之晶片1〇，並非偈限 於此。 如此，便可將所有埋入於該電路板7中之各該晶片^ 〇 予以連接，而使各該晶片10中之熱能藉由該散熱層735 傳導出去。 17811 15 1260756 ，弟]G圖所不，於本實施例中，可先 綠漆之防銲層㈤dei.Mask)75於該絕緣層 =層75係定義有複數個防銲層開口 = 暴露出局部之金屬導線層-以及:；層懈 以供與外界裝置連接。當然 層而與空氣接觸，可具有較佳散熱效果未後有防知 之，=明=、Γ重f第8至第9圖之步驟進行增層’·換言 以本每^丨I、用於具有多層線路導通之電路板中，並非 說明:&歹，戶斤述者為限，且增層技術亦屬習知而不另作 7切割形成複數個 隨後，進行切單作業以將該電路板 電路板單元（未圖示）。 導教m片1〇具有延伸於半導體元件附近之晶背 納二二、/而7该晶背導熱層U3接觸各該晶片10之接 ㈣曰1^大者，故可增加有效之散熱面積；而連接各該 相^:片1〇之晶背導熱層133的散熱層735，以配合該晶 :期為散熱之用，故可確實將各該晶片10於操 作…月間所產生之熱能傳導出去。 ^上述μ鈀例僅為例示性說明本發明之原理及其功 效二而非用於限制本發明。任何熟習此技藝之人士均可在 =違背本發明之精神及範嘴下，對上述實施例進行修飾與 又^1 °因此’本發明之權利保護範圍，應如後述之申請專 利範圍所列。 【圖式簡單說明】 17811 16 1260756 第1圖至第10圖為說明本發明之埋入式晶片之散熱 結構及其製法之較佳實施例之示意圖。 【主要元件符號說明】 1 晶圓 11 第一表面 111 外接金屬層 13 第二表面 131 盲孑L 133 晶背導熱層 133a 第一導電層 133b 第一金屬層 3 底板 5 結合層 7 電路板 71 開口 73 絕緣層 731 絕緣層開口 733 金屬導線層 735 散熱層 739 鋅錫材料 75 防鋅層 751 防銲層開口 9 黏著劑 10 晶片 AA 線段 A，A’ 線段 17 17811BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a heat dissipating structure for a buried wafer and a heat dissipating structure for a buried wafer integrated in a circuit board and a method for manufacturing the same. [Prior Art] In order to meet the trend of light, short, versatile, high-speed, and high-frequency electronic products, it is necessary to strengthen the functions of electronic component integration, high-speed processing, small-scale light-weight, and slow-speed processing. Circuit board (pCB) or build-up circuit (ic) package backplane technology has evolved toward thin lines and small apertures. At present, the process of printed circuit board or 1C package backplane has been reduced from the traditional 100_ by t ^ ^ road size (including line width (Line Width), wire spacing (SPace) 觅匕 (Aspect lat10)) to about 30μιη, and Smaller line precision is being developed. At the same time, as electronic products are oriented toward high functionality and small size, LaminatiGn technology must be thick, multi-layered and high-density. Features, so the development of a passive circuit board, the eve layer of the circuit board to further reduce the board space. However, when the electronic product demand operation frequency is higher and higher, and the wafer is more, the Eve The thermal energy from the wafer is also getting higher and higher, and the problems related to heat dissipation must be solved. For example, it is Epoxy resin, Polymude, and chaotic fat (Cyanaie & , glass fiber (6) (four) lamp), 17811 5 1260756 bis-succinimide / trinitro- τ, plus illusion or mixed epoxy resin and glass fiber (FR5) and other materials to support the bottom plate Wafer' and provide crystal For heat dissipation, such as U.S. Patent No. 6, such as the state case, the Ic wafer is placed on the top surface of the bottom plate and/or the reinforcing plate. However, since the heat conductivity of the bottom plate is poor, and the wafer is separated by the bottom plate, The thermal energy transfer of the wafer has a relatively high resistance ^Theta-JB) 'There is no way to dissipate thermal energy from the laminated board. · And 'the thermal expansion coefficient (cte) of the backplane and Ic wafer does not match isctatch'' Add thermal stress to 1 (: wafer and solder ball, and reduce the sin. The more the film is used for the wire bond, the gap on the heat sink will reduce the twin edge: the thermal connection will cause thermal energy to be limited to the IC crystal. The sum of the month and the bottom plate is not able to effectively dissipate in the area around the bottom plate. Not enough: The way to dissipate heat from the bottom plate of the single-loaded chip itself has been used and the following solutions are available. Bottom m, ' Some people have suggested that more fresh balls will be added to the 1α film. The heat will be transmitted from the solder balls such as 5 Hai. In other words, this will be the ball with the ball, so that the cost will follow the number of the ball. And the addition of II people proposed a kind of integrated heat sink in the bottom of the knot And the method of production, = hot space 'such as US Patent No. 6,706, = hot parts will increase the volume of electronic components, and it is not conducive to the trend of short and light mouth. The production industry is the first, the wafer carrier, the month After the wafer carrier of the clothing (such as the bottom plate or the 17811 1260756 lead frame), the wafer carrier is transferred to the semiconductor package manufacturer for processing, molding, and ball-planting, and finally, the guest is completed. The semiconductor device of the electronic function required by the household. Since the process involves different process makers (ie, including the wafer carrier manufacturer and the semiconductor packaging industry), the above-mentioned conventional technology is not only complicated in the actual manufacturing process. Two sides are not easy. ^ ^ The client wants to change the function design involves the change and integration level is more complicated, and does not meet the change flexibility and economic benefits of the demand layout. Therefore, in the above-mentioned problems, how to avoid the problems caused by the conventional technology to solve the problem of cost improvement, reliability and heat dissipation efficiency has become an urgent issue to be discussed. SUMMARY OF THE INVENTION The present invention provides a heat dissipation structure and a method for fabricating the same, and the heat dissipation structure on the wafer is used to effectively expand the heat dissipation structure of the heat dissipation area to enhance the dispersion. The present invention provides a buried wafer, a product, a sigma structure, and a method thereof. In the method of fabricating the heat dissipation structure of the embedded wafer, the first method is to provide a second wafer of the second surface and a second surface, wherein the inactive surface of the wafer is:::曰, active The second surface of the wafer is a wafer of π which forms an external metal layer on the first surface of the wafer. Here choose:: Second, the mother of the mouth of the mouth is cut into the electrical connection of the chip 1781] 1260756 pad:: has a corresponding external metal layer. r f The first surface of the wafer on which the external metal layer is formed is placed in the opposite direction. Before this step, a gentleman can be formed on the first surface of the wafer. The bonding layer will be: 2! The bonding layer covers the external metal layer, and the surface of the y 曰曰0 is placed on the bottom plate. Thereafter, a crystalline f-conducting layer is formed on the surface of the wafer. Optionally, in the form of a blind hole, and forming a plurality of thermal layers in the wafer area. Among them, the wafer can be selected to be thinned to improve heat dissipation efficiency. And cutting the wafer into sf, to insert the plurality of wafers into the plurality of crystals to integrate the wafer in the circuit board. In the opening of the road board, then, The pressing and opening operations are performed on the lower surface of the circuit board to form an insulating layer:,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, The partial insulating layer is formed on the insulating layer = the circuit board and the partial crystal back heat conducting layer are formed, by: external gold (10) pad portion and partial crystal back heat conducting layer. The gold two heat conducting layer forms a heat dissipating structure. The heat dissipating structure is conducted by the heart === 17811 I260756. The heat energy generated by the wafer is conducted out. Since the present invention directly embeds the wafer in the circuit board, and forms a two-connected wafer. Wafer thermal junction formed by the thermal layer of the crystal For conduction heat, it can solve the thermal energy failure caused by the poor thermal conductivity of the bottom plate and the high resistance generated by the thermal energy transfer to the wafer in the prior art: the absence of the text 2, and the thermal expansion coefficient of the substrate and the IC chip The problem of lowering the degree of guilt is not matched. : However, it is optional to form a solder resist layer on the insulating layer (soIder Li). The anti-fresh layer defines a plurality of anti-slip layer openings for the plurality of openings. The metal wire layer and the heat dissipation layer are exposed to be externally accessible to the outside world, and if the hot layer of the sea is not covered with the solder resist layer and is in contact with the air, the heat dissipation effect is good. Repeating the layering operation including the step of forming the bonding and the opening, and forming the monk wire layer and the heat dissipating layer on the outer metal layer and the back surface heat conducting layer respectively. The heat dissipating layer can be connected to the outside world: after the single sheet t-cutting operation, a plurality of electric embossed embossed wafers can be obtained, and the heat dissipating structure of the δ hai buried wafer includes at least half of the guiding dies. - formed on each of the wafers actively Thin: a crystal back thermally conductive layer of the inactive surface of the wafer. W-guide: The non-active surface of the wafer has a plurality of blind holes for covering the crystal wafer 1 , wherein the depth of each blind hole can be selected to be less than or equal to And the crystalline back thermally conductive layer comprises a first conductive layer and a first metal layer of a conductive layer, wherein the first conductive layer forms 17811 9 1260756 on the second surface of each of The blind hole surface. The road plate door 2::: month: provides a type of electric circuit having the above-mentioned chip heat dissipation structure. The road board includes: at least - the opening is disposed in the circuit board; at least - a cymbal, and the wafer has An active surface and an electric, one port, an external metal layer formed on each of the crystals; = formed on the surface of each of the wafers plus the non-active surface of the circuit board to cover the crystal back thermally conductive layer, the opening of the insulating layer And a heat dissipation layer formed at least on a portion of the surface of the insulating layer on the =:::¥ thermal layer and in the opening of the insulating layer, the heat dissipation layer connects the thermal layer of the crystal material to the outside, and the wafer: red The heat generated during the process is conducted out. In the invention, the insulating layer may be formed on the surface of the circuit board of the active surface of the cymbal to cover the external metal layer, and the surface of the insulating layer has a plurality of openings corresponding to the surface of the external metal layer; And a metal (four) layer 'is formed at least in the opening of the insulating layer on the external metal layer, and the metal wire layer is connected to the external metal layer. The gap between each of the wafers and the openings of the respective circuit boards is filled with 4 occupies di' to fix each of the wafers to the opening of the circuit board. The heat dissipation layer may optionally extend to connect at least a wafer back thermally conductive layer to connect the wafers buried in the circuit board. Since the heat dissipation formed by the wafer itself can surely conduct the heat energy generated during the operation from the heat dissipation wire, not only the heat dissipation area can be enlarged, but also the heat dissipation can be efficiently performed, so that only the carrier chip can be solved in the technology. The bottom plate itself is lack of heat dissipation' and there is no conventional technology to increase the number of 17811 1260756 plus the number of solder balls and the integration of the scattered VI ^ - the cost, layout and volume of the thumb to go to the second wrong by specific specific examples to illustrate: The problem is that the person who is familiar with this skill's 月 昤 昤 昤 * * * 代 代 代 代 代 代 代 代 代 代 代 代 代 代 代 代 代 代 :: :: :: :: :: :: :: :: :: </ RTI> <RTIgt; </ RTI> <RTIgt; </ RTI> <RTIgt; </ RTI> <RTIgt; </ RTI> <RTIgt; </ RTI> <RTIgt; [Embodiment] The following embodiments are not intended to limit the scope of the present invention in any way. ...point’ but please see the first! To the first drawing, it is a schematic diagram of the heat dissipation structure and its manufacturing method. As shown in Figure 1 of the S-type film, the Sun-plate-曰ΓΠ-surface U and a first, the wafer 1 has a -the younger-surface 13, the first surface 11 is defined as The two surfaces 13 are for example defined as inactive surfaces. On the plurality of electrical connection pads of the wafer ang-surface η, for example, a plurality of ridges are used. The ρ metallization process forms an external metal layer. The so-called bottom metallization process refers to the process of performing the process on the wafer 1 by using methods such as sputtering technology, vapor deposition technology (EvaP〇ratl0n), and plating technology (Plating), such as recording-gold- The metal, copper, titanium-copper, titanium-nickel-vanadium-copper or other suitable composition is superposed to form, for example, a plurality of electrical connection pads and a metal layer ηι. Among them, methods such as a sputtering technique, a vapor deposition technique, and a plating technique are conventional techniques, and the description thereof will be omitted. 17811 11 1260756 Although a blind hole between two semiconductor elements and semiconductor components such as four squares and shoulders is formed as an example, the present invention can be embodied in various forms. The content and the drawings are intended to be a preferred embodiment of the present invention and are not intended to limit the scope of the present invention. And as shown in FIG. 2, the bonding layer 5 is entirely formed on the first surface u of the wafer, and the bonding layer 5 covers the external metal layer (1) to form the wafer by the # bonding layer 5. The first surface is placed on a sapphire sheet or other underlying patch (Tape). At this time, it is optional to thin the mouth 1 to improve the heat dissipation efficiency of the wafer. Wherein, the bonding layer 5 can be selected as a liquid energy, a combined, and a night-hearted (Wax) layer. Since the liquid wax meets the high temperature and low temperature, the Japanese-Japanese code can be cured, thereby helping to fix the wafer 1; w & It is also easy to peel off the bottom plate 3 in the future. As shown in the picture of brother 3, it is tied to the fate of Yubei. On the second day of the SI 1st, the second surface of the SI 1 is carried out on the surface 13: two: two; to: cut into a wafer like: middle to η, the area between the line segments is pre-. (, 〃5 domain. Among them, each of the crystal back The depth of the blind hole 131 can be '... or the depth of the temple 1 to the wafer. The blind hole 131 formed by the material embodiment is equal to the depth of the day ® 1 , and the outer i / The depth of the surface is the depth of the surface, and the depth of the 4th layer (that is, the surface with the hot channel). The divergence and width of the subsequent formation of this embodiment must be noted. (3) At the same time, in the present embodiment, _=== he changes or modifies. Each of the blind holes 131 is formed by using a method such as lithography etching 17811 12 1260756. Of course, it is also possible to select each other. The blind hole 131 is not limited thereto. Since the "two-form" theory and the method are conventional, the description of the method is not shown here, as shown in Fig. 4, The second wafer wafer = a crystalline back heat conduction layer 133 is formed in the blind via 131. The two sides 13 and each of the first conductive layer and the surface formed by the electric recording = month = layer (1) a second surface of the wafer i, a first metal layer 133b of the germanium layer 1332. wherein the first and second holes 13 are on the second surface 13 of the wafer 1 and each of the blind layers is titanium (Ti) / copper (Cu) or a conductive layer, and may be, for example, a layer of a copper layer or a gold layer formed by a seed crystal of the first metal layer:::::: : 〇 矿 矿 或 或 或 或 或 矿 矿 矿 矿 矿 矿 矿 矿 矿 矿 矿 矿 矿 矿 矿 矿 矿 矿 矿 矿 矿 矿 矿 矿 矿 矿 矿 矿 矿 矿 矿 矿 矿 矿 矿 矿 矿 矿 矿 矿 矿 矿Show, from the wafer] the bottom plate 3, leaving the external metal layer! 〗 1 In the upper peeling embodiment, such as twisting; ^ = in the wafer Melt volatilization. #然^7 For example, the bottom of the liquid worm, the water, the acid, the capacity, and the material of the bottom plate 3 to heat the plate 3. The chilling liquid, the test solution or other suitable means to remove the The bottom cut Π: indicates that the wafer will be completed by the above-mentioned integrated circuit process: "1", wherein the wafer 1 is cut and read by a predetermined area. The technology is well-known, so it is not explained. 17811 13 1260756 Yamashita ♦ 7A and 10B show the multiple crystals W0:: circuit board (c_itboard) 7, where the wafer 10 The circuit board 7 is formed with a plurality of openings 71', each of which is slightly larger than each of the wafers 10, 〇μ日片1 〇. In this embodiment, the adhesive is adhered to the gap between the wafers 10 and the openings 71 of the circuit board 7, and after the operation, the wafer is made by liquid glue such as a thermosetting material!固定 Fixed on the board 7 towel. The adhesive 9 can be made, for example, of a liquid glue (Glue) or other adhesively preferred material. In this case, the circuit board 7 has a plurality of wafers integrated therein, formed on the active surface of each of the wafers, and a metal back layer formed on the active surface of each of the wafers. 133, and the gap between each of the wafer 10 and the opening 71 is precisely fixed by the adhesive 9. As shown in Fig. 8, an insulating layer 73 is formed on the upper and lower surfaces of the circuit board 7 on which the wafer 1 is integrated, for example, by press-bonding. The electricity can be removed by an opening technique such as laser drilling, exposure development or plasma etching: a partial insulating layer on the upper and lower surfaces of the board 7 is formed such that the insulating layer 73 is formed with a plurality of insulating layer openings 731. The insulating layer openings 731 are corresponding to, for example, the external metal layer Π1 (for example, the electrical connection pad position) and the partial crystalline back thermal conductive layer 133 of the wafer 10, and the external metal layer 111 and the partial crystal back are exposed. Thermal conductive layer 133. Wherein, the insulating layer is a non-fibrous resin type material, such as ABF (Ajinomoto Build-up Film) or polypropylene (pp), or a fiber impregnated resin material, such as bis-succinimide/imide/ Triazo trap (BT, Bismaleimide... 加加) plus glass 17811 14 1260756 glass fiber or mixed epoxy resin and face fiber (FR4), etc. or photosensitive insulation layer. When using the laser drilling technology, it is necessary to remove the slag (:, called the operation, to remove the _ holes left in the plurality of insulating layers of glue. If the insulating layer 73 is optically sensitive, In the exposure and display mode, the plurality of insulating layers are formed, and then a de-slag removal operation (De_s_) is performed to remove the residue remaining in the plurality of insulating layer openings 731 due to the shadow. As shown in FIG. 9, after the patterned circuit process, metal wires-and heat-dissipating layers are formed. In this embodiment, 'for example, electroplating, electroless plating, physical deposition, chemical deposition, or other suitable means, at least the external metal layer. A metal wire layer is formed in each of the insulating layer openings 731 on the m; and a heat dissipating layer 735 is formed under the partial crystal back heat conducting layer 133 to form a thermally conductive layer i33. Integrating a plurality of wafers embedded therein, forming a metal layer formed on each of the active faces of the wafer 10, and forming a crystal f heat-conducting layer 133 formed on each of the inactive faces of the wafer 1G, is partially formed at the eve: Metals on the metal wire layer 7 33, and a heat dissipation layer 73" partially formed on the back surface of the heat conduction layer 133, and the heat dissipation layer 735 is selected to be connected to at least two adjacent wafers of the wafer back heat conduction layer 133. Of course, the heat dissipation layer 735 In order to connect one or more wafers, it is not limited thereto. Thus, all the wafers buried in the circuit board 7 can be connected, and the heat energy in each of the wafers 10 can be made. The heat dissipation layer 735 is conducted out. 17811 15 1260756, the second figure is not shown. In this embodiment, the green paint solder resist layer (5) dei. Mask 75 is defined in the insulating layer = layer 75. The solder mask opening = the exposed metal wire layer - and :; layering for connection with the external device. Of course, the layer and the air contact, can have better heat dissipation effect, no anti-knowledge, = Ming =, Γ The steps of the steps 8 to 9 are to increase the layer'. In other words, in the circuit board with multi-layer line conduction, it is not stated: & Layer technology is also known without the need to make 7 cuts to form a plurality of subsequent Circuit board circuit board unit (not shown). The teaching m piece 1 has a crystal backing diode extending in the vicinity of the semiconductor element, and 7 the crystal back heat conducting layer U3 contacts each of the wafers 10 (4) 曰 1^ The larger one can increase the effective heat dissipation area; and the heat dissipation layer 735 of the crystal back heat conduction layer 133 of each of the layers is connected to match the crystal: heat dissipation, so that the wafer can be surely The thermal energy generated during the operation of the month is conducted out. The above-mentioned μ palladium is merely illustrative of the principles of the present invention and its effects, and is not intended to limit the present invention. Anyone skilled in the art can The above embodiments are modified and further modified by the spirit and scope of the invention. Therefore, the scope of protection of the present invention should be as set forth in the appended claims. BRIEF DESCRIPTION OF THE DRAWINGS 17811 16 1260756 FIGS. 1 to 10 are schematic views showing a preferred embodiment of a heat dissipation structure of a buried wafer of the present invention and a method of manufacturing the same. [Main component symbol description] 1 wafer 11 first surface 111 external metal layer 13 second surface 131 blind 孑 L 133 crystal back heat conduction layer 133a first conductive layer 133b first metal layer 3 bottom plate 5 bonding layer 7 circuit board 71 opening 73 Insulation 731 Insulation opening 733 Metal wire layer 735 Heat sink 739 Zinc tin material 75 Zinc-proof layer 751 Solder mask opening 9 Adhesive 10 Wafer AA Segment A, A' Segment 17 17811