TW200616185A - Heat sink structure for embedding chips and method for fabricating the same - Google Patents

Heat sink structure for embedding chips and method for fabricating the same

Info

Publication number
TW200616185A
TW200616185A TW093134247A TW93134247A TW200616185A TW 200616185 A TW200616185 A TW 200616185A TW 093134247 A TW093134247 A TW 093134247A TW 93134247 A TW93134247 A TW 93134247A TW 200616185 A TW200616185 A TW 200616185A
Authority
TW
Taiwan
Prior art keywords
chip
layer
fabricating
circuit
same
Prior art date
Application number
TW093134247A
Other languages
Chinese (zh)
Other versions
TWI260756B (en
Inventor
Chi-Ming Chen
Original Assignee
Phoenix Prec Technology Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Phoenix Prec Technology Corp filed Critical Phoenix Prec Technology Corp
Priority to TW093134247A priority Critical patent/TWI260756B/en
Publication of TW200616185A publication Critical patent/TW200616185A/en
Application granted granted Critical
Publication of TWI260756B publication Critical patent/TWI260756B/en

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/04105—Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/12105—Bump connectors formed on an encapsulation of the semiconductor or solid-state body, e.g. bumps on chip-scale packages
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L2224/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
    • H01L2224/24—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
    • H01L2224/241—Disposition
    • H01L2224/24135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/24137—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being arranged next to each other, e.g. on a common substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L2224/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
    • H01L2224/25—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of a plurality of high density interconnect connectors
    • H01L2224/251—Disposition
    • H01L2224/2518—Disposition being disposed on at least two different sides of the body, e.g. dual array

Landscapes

  • Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)

Abstract

A heat sink structure for embedding chips and a method for fabricating the same are proposed. An external metal layer is formed on the surface of a chip with pads and a wafer backside heat conduction layer is formed on the inactive surface of the chip. At least one chip is embedded into one opening of a circuit board. The circuit board integrated with at lease one chip is formed with a circuit layer and a heat dissipating layer. The circuit layer is connected to the external metal layer and the heat dissipating layer is connected to the wafer backside heat conduction layer of at least one chip, so as to electrically connect to the chip embedded into the circuit board. Thus, the chip is electrically connected to outer circuit and the heat generated during operation of the chip is conducted to exit.
TW093134247A 2004-11-10 2004-11-10 Heat sink structure for embedding chips and method for fabricating the same TWI260756B (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
TW093134247A TWI260756B (en) 2004-11-10 2004-11-10 Heat sink structure for embedding chips and method for fabricating the same

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
TW093134247A TWI260756B (en) 2004-11-10 2004-11-10 Heat sink structure for embedding chips and method for fabricating the same

Publications (2)

Publication Number Publication Date
TW200616185A true TW200616185A (en) 2006-05-16
TWI260756B TWI260756B (en) 2006-08-21

Family

ID=37874843

Family Applications (1)

Application Number Title Priority Date Filing Date
TW093134247A TWI260756B (en) 2004-11-10 2004-11-10 Heat sink structure for embedding chips and method for fabricating the same

Country Status (1)

Country Link
TW (1) TWI260756B (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI647581B (en) * 2017-11-22 2019-01-11 緯創資通股份有限公司 Board and layout structure
CN111128922A (en) * 2018-10-30 2020-05-08 台湾积体电路制造股份有限公司 Semiconductor device, circuit board structure and manufacturing method thereof
CN113675174A (en) * 2021-08-17 2021-11-19 青岛佳恩半导体科技有限公司 Preparation method for improving Mark point morphology of power device

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8547709B2 (en) 2010-02-12 2013-10-01 Cyntec Co. Ltd. Electronic system with a composite substrate
TWI720921B (en) 2020-07-14 2021-03-01 欣興電子股份有限公司 Embedded component structure and manufacturing method thereof

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI647581B (en) * 2017-11-22 2019-01-11 緯創資通股份有限公司 Board and layout structure
CN111128922A (en) * 2018-10-30 2020-05-08 台湾积体电路制造股份有限公司 Semiconductor device, circuit board structure and manufacturing method thereof
CN111128922B (en) * 2018-10-30 2023-05-16 台湾积体电路制造股份有限公司 Semiconductor device, circuit board structure and manufacturing method thereof
CN113675174A (en) * 2021-08-17 2021-11-19 青岛佳恩半导体科技有限公司 Preparation method for improving Mark point morphology of power device

Also Published As

Publication number Publication date
TWI260756B (en) 2006-08-21

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Legal Events

Date Code Title Description
MM4A Annulment or lapse of patent due to non-payment of fees