TWI260629B - Programming circuit for a programmable microelectronic device, system including the circuit, and method of forming the same - Google Patents

Programming circuit for a programmable microelectronic device, system including the circuit, and method of forming the same Download PDF

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Publication number
TWI260629B
TWI260629B TW92100098A TW92100098A TWI260629B TW I260629 B TWI260629 B TW I260629B TW 92100098 A TW92100098 A TW 92100098A TW 92100098 A TW92100098 A TW 92100098A TW I260629 B TWI260629 B TW I260629B
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circuit
switch
coupled
programmable
region
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TW92100098A
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Chinese (zh)
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TW200301896A (en
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Michael N Kozicki
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Axon Technologies Corp
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    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C13/00Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
    • G11C13/0002Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
    • G11C13/0009RRAM elements whose operation depends upon chemical change
    • G11C13/0011RRAM elements whose operation depends upon chemical change comprising conductive bridging RAM [CBRAM] or programming metallization cells [PMCs]
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C13/00Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
    • G11C13/0002Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
    • G11C13/0021Auxiliary circuits
    • G11C13/0069Writing or programming circuits or methods
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C13/00Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
    • G11C13/0002Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
    • G11C13/0021Auxiliary circuits
    • G11C13/0069Writing or programming circuits or methods
    • G11C2013/009Write using potential difference applied between cell electrodes
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C2213/00Indexing scheme relating to G11C13/00 for features not covered by this group
    • G11C2213/10Resistive cells; Technology aspects
    • G11C2213/15Current-voltage curve
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C2213/00Indexing scheme relating to G11C13/00 for features not covered by this group
    • G11C2213/70Resistive array aspects
    • G11C2213/72Array wherein the access device being a diode
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C2213/00Indexing scheme relating to G11C13/00 for features not covered by this group
    • G11C2213/70Resistive array aspects
    • G11C2213/79Array wherein the access device being a transistor

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  • Semiconductor Memories (AREA)

Abstract

A circuit for programming a microelectronic device is disclosed. The circuit is configured to provide a reversible bias across the microelectronic device to perform erase and write functions. One configuration of the programming circuit includes one or more inputs coupled to the programmable device and a complimentary metal-oxide semiconductor circuit coupled to the programmable device. This design allows for writing and erasing of the programmable cell using a low and high voltage input.

Description

1260629 五、發明說明(1) '~' -------- 相關申請案的對照: 本申請案為2002年1月3曰提出申請之美國專利 案號60/345, 931「用於可程式金屬化細胞元之可程g = (PROGRAMMABLE CIRCUITRY FOR THE PROGRAMMABLE 路 METALLIZATION CELL)」一案的延續。 一、【發明所屬之技術領域】 本發明係與可程式微電子裝置有關,特別是與一種 施加寫入以及/或者抹除電壓的電路有關。此電路藉由 縱供給裝置的能量大小/或者能量極性,將裝置的電子牿 性予以可變異程式化。 付 二、【先前技術】 在電子系統與電腦中經常使用到記憶體裝置來儲存二 進位的資料。這些記憶體裝置可依其特性分為不同的類一 型,每一種類型都有其不同的優缺點。 、 舉例來說,個人電腦中可以看到的隨機存取記憶體 (RAM) —般屬於揮發性半導體記憶體(v〇lati u semiconductor memory)。換句話說,當電源被切斷或是 拔掉的時候,所儲存的資訊就會流失。動態隨機存取記憶 體(Dynamic DRAM)必須每幾個百萬分之一秒 、 (microsecond)就更新(refreshed),也就是重新充電— 次’才能夠留住所儲存的資料,因此具有高度的揮發性。1260629 V. INSTRUCTIONS INSTRUCTIONS (1) '~' -------- RELATED APPLICATIONS: This application is filed on Jan. 3, 2002, and the US Patent No. 60/345, 931, The continuation of the case of programmable metallization cell g = (PROGRAMMABLE CIRCUITRY FOR THE PROGRAMMABLE road METALLIZATION CELL). I. Field of the Invention The present invention relates to programmable microelectronic devices, and more particularly to a circuit for applying write and/or erase voltage. This circuit mutably programs the electronic enthalpy of the device by the energy supply/or energy polarity of the vertical supply device. 2 2. [Prior Art] Memory devices are often used in electronic systems and computers to store binary data. These memory devices can be classified into different types according to their characteristics, and each type has its own advantages and disadvantages. For example, random access memory (RAM) that can be seen in a personal computer is generally a volatile semiconductor memory (v〇lati u semiconductor memory). In other words, when the power is turned off or unplugged, the stored information is lost. Dynamic random access memory (Dynamic DRAM) must be refreshed every few millionths of a second (microsecond), that is, recharge - times to retain the stored data, so it has a high degree of volatilization Sex.

第5頁 1260629 五、發明說明(2) 靜態隨機存取記憶體(Statlc DRAM)可以 留資料,只要電源不切斷就會—直保持原冩入能一次後保 源一切斷,資料也會消失。因此,在這類=。但是電 中,只有在系統沒有斷電的時候才合保有一么性έ己憶體 說,這些RAM裝置佔了相當可觀的晶、'積貝,'W般來 車:昂貴。而為了要儲存資料,也會消耗相當衣會比 由上可知’我們需要更進步的記憶體裝置,用"源。 與類似的裝置上。 在個人電腦 其^存裝置像是磁碟片、硬碟與磁帶等磁性 衣置,還有光碟片、CD-RW和DVD-RW等都算是# #义思;/ 是’這些記憶體裝置的體積大1易受撞擊/震動影塑的 :口動機構貴’ t消耗相當大量的功率。這些負面“ 素使侍此類記憶體裝置不適用於膝上型、掌上型電腦 '個 人數位助理(PDA)等低功率的可攜式應用上。 小巧、低功率、可經常更換儲存資料的可攜式電腦系 、、先與手持型設備的數量迅速成長,是低功率讀/寫半導體 記憶體越來越受重視與普及的部份原因。此外,由於這類 可攜式系統通常需要在關機的時候料, 非 揮發性儲存裝置是較好的選擇。 、 木用非 可程式唯讀記憶體(PROM)係適用於這類系統的一種可Page 5 1260629 V. Invention Description (2) Static random access memory (Statlc DRAM) can retain data, as long as the power supply is not cut off - the original input can be kept off once, the data will disappear . So in this class =. However, in electricity, only when the system is not powered off, there is a nature of the memory. These RAM devices account for a considerable amount of crystal, 'Jiebei, 'W like a car: expensive. In order to store the data, it will consume a considerable amount of clothes. It is known from the above that we need a more advanced memory device, using the source. With similar devices. In the personal computer, the storage device is like a magnetic disk, a hard disk and a magnetic tape, and the optical disk, CD-RW and DVD-RW are all ##义思; / is 'the memory device' Large volume 1 is subject to impact/vibration: the porting mechanism consumes a considerable amount of power. These negative “features make this type of memory device unsuitable for low-power portable applications such as laptops, palmtops, personal digital assistants (PDAs), etc. Small, low-power, frequently changeable storage data The rapid growth of portable computer systems, first-hand and handheld devices is part of the reason why low-power read/write semiconductor memory is gaining more and more attention and popularity. In addition, because such portable systems usually need to be turned off. Non-volatile storage devices are a good choice. Wood non-programmable read-only memory (PROM) is a suitable system for this type of system.

第6頁 1260629 ------- 五、發明說明(3) 非揮發性半導體記憶體裝置。在p_之令 =;ϊ Γ?/(麵)的裝置,使用可燒炫(㈤… =線陣列。卿裝置經過程式化以後,就不能再重複程 二中還包括可抹除(erasabie)的可程式唯讀 體裝置(EEPR0M)。這種穿置妹的可程式唯讀記憶 更。EPROM壯w 種衣置、工過耘式化以後還可以再變 ROM衣置-般需要經過抹除的動作, 外線的照射。因此這類裝置並不適合用在可 -i缺點衣拉1 :EEPR〇M裝置比較容易程式化,但是也有 難了俨籍i寺別疋EEPR〇M裝置都相當複雜、製造上相當困 5 對,比較大。除此之外,包含ΕΕ_的電路必 儲:η 式化的高電壓。所以膽_和其他資料 每個位元的成本非常高。εερ_雖然在斷 然:以保有資料,但是在程式化過程中卻需: μ=a玄率才仃。對於以電池供電的可攜式系統來說,這 樣的功率負擔是相當可觀的。 < 主像是快閃記憶體(FLASH) —類的記憶體也相當昂 二、,:過程也相當複雜。因此,我們需要易於製造,且 乂造成本相對不貴的改良型記憶體裝置。除此之外,我們 也需要可程式化這類裝置的電路。 第7頁Page 6 1260629 ------- V. Description of the invention (3) Non-volatile semiconductor memory device. In the device of p_ (= ϊ / / / / / / / / ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( Program-only read device (EEPR0M). This kind of wearable program has a program-only read-only memory. EPROM is a kind of clothing, and it can be changed to ROM after the work is finished. , the external line of illumination. Therefore, this type of device is not suitable for the use of the -i defect clothing 1: EEPR 〇 M device is relatively easy to stylize, but it is also difficult to 俨 i 寺 寺 寺 疋 疋 疋 疋 疋 疋 疋 疋 疋 疋 疋 疋 疋 疋 疋 疋 疋 疋 疋 疋 疋It is quite sleepy 5 pairs, which is relatively large. In addition, the circuit containing ΕΕ_ must store: η-type high voltage. So the cost of each bit of biliary_ and other data is very high. εερ_ Although it is broken: There is data, but in the process of stylization: μ = a Xuan rate. For a battery-powered portable system, this power burden is considerable. < The main image is flash memory (FLASH) - The memory of the class is also quite high, and the process is quite complicated. Here, we need easy to manufacture, and resulting in improved qe memory device according to the present relatively expensive. In addition, we also need to be programmable circuitry of such devices. Page 7

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【發明内容】 本卷明長:供改良的微電子可程式電路 (microelectronic programmable circuit) ^ , 程式電路之系統及其形成方法。更特別的是,與包含 程式電路(programming Circuit),用以提供 x明提供 ,除的電壓給可程式裝置。❿包含這類電路二及/ =式結構的系統可以取代傳統的非揮發性與揮發性記^ 接下來將詳細探討本發明 一些缺點。整體來說,本發明 可程式裝置相當容易製造,且 容易達到程式化的目的。 如何克服現行可程式裳置的 所揭示的程式電路與相關的 成本相當便宜,同時也相當 省在本發明的各種實施例中,可程式結構包含一個離子 V,(i〇n至少二個電極(electr〇de)。當外 加第一極性偏壓於二電極之間時,會改變結構的一或多個 ,子特性。在此實施例的一個情形中,當外加第一極性偏 壓於一電極之間時,會改變結構的阻抗(resistance)。在 另#個情形下,當外加第一極性偏壓於二電極之間時,會 改、=結構的電容(Capaci tance)或其他的電子特性。根據 本實施例的另一情形,我們可以藉由施加一足量的第二極 ί*生的偏壓,逆轉可程式特性的變化量。而一或多個電子特 性的變化以及改變量可以偵測得到,因此,我們可以從包SUMMARY OF THE INVENTION This is a description of a modified microelectronic programmable circuit, a system of a program circuit, and a method of forming the same. More specifically, and including a programming circuit, the voltage is supplied to the programmable device.系统 Systems containing such circuit two and / = structures can replace traditional non-volatile and volatile notes. Next, some of the disadvantages of the present invention will be discussed in detail. Overall, the programmable device of the present invention is relatively easy to manufacture and is easy to achieve stylized. How to overcome the current programmable circuit of the disclosed programmable circuit is relatively inexpensive, and is also quite advantageous in various embodiments of the present invention. The programmable structure includes an ion V, (i〇n at least two electrodes ( When the first polarity is biased between the two electrodes, one or more, sub-characteristics of the structure are changed. In one embodiment of this embodiment, the first polarity is biased to an electrode. When it is between, it will change the resistance of the structure. In the other case, when the first polarity is applied between the two electrodes, the capacitance of the structure or other electronic characteristics will be changed. According to another aspect of the embodiment, we can reverse the amount of change in the programmable characteristic by applying a sufficient amount of the second bias, and the change in one or more electronic characteristics and the amount of change can be Detected, so we can get from the package

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五、發明說明(5) 含此一結構的電路中取出所儲存的資訊。 的 根據本發明,用以程式化以及/或者抹除可程 電路包含複數個電壓輸入端以及複數個開關,連衣置 電壓源與接地(ground)以及電壓輸入端之間。在 j f ~ 的各種情況下,程式電路使用第一電壓(μ 貫施例 壓)和第二電壓(比如說一個負電壓)來 笔 只❾ / +牲式化以 者抹除可程式裝置。在本實施例的一個特別情況下 \ 電路包含一個連接至電壓輸入端和可程式化^置’程式 氧半導體(CMOS)電路。在本實施例的其他不^情兄^補金 式電路包含被動負載以及/或者主動負載。 月’下’程 根據本發明的另一實施例,用以程式化以及/ :可:呈式裝置的電路包含單一寫入電壓輸入端,複;個J 關’和一個選擇開關(select switch)。複數個開關連1 在電壓源與接地(ground)以及寫入電壓輸入端之間。 開關連接於寫入電壓輸入端與可程式化裝置間。選擇開 可以讓結構陣列内的特殊可程式結構選擇地:二 ¢6. ΛΑ m ^ <〜两八驭抹 根據本發明的另一實施例,可程式裝置可以在一個基 座的表面上形成。在本實施例的一個情況下,基座包含^ 式電路。而在本實施例的另一個情況下,記憶體裝置覆蓋 於程式電路之上,而程式電路與記憶體間的導線則是利用 _ __V. INSTRUCTIONS (5) The stored information is taken out from the circuit containing the structure. In accordance with the present invention, the programmable and/or erased rewritable circuit includes a plurality of voltage inputs and a plurality of switches between the voltage source and the ground and the voltage input. In the various cases of j f ~, the program circuit uses the first voltage (μ) and the second voltage (such as a negative voltage) to pen only / + animalize to erase the programmable device. In a particular case of the present embodiment, the circuit includes a circuit coupled to a voltage input and a programmable logic semiconductor (CMOS) circuit. Other non-sense circuits in this embodiment include passive loads and/or active loads. According to another embodiment of the present invention, a circuit for programming and/or: a presentation device includes a single write voltage input terminal, a plurality of J switches ' and a select switch (select switch) . A plurality of switches are connected between the voltage source and the ground and the write voltage input. The switch is connected between the write voltage input and the programmable device. Selecting the opening allows the special programmable structure within the array of structures to be selected: ¢6. ΛΑ m ^ <~two octaves According to another embodiment of the invention, the programmable device can be formed on the surface of a pedestal . In one case of this embodiment, the pedestal includes a circuit. In another case of the embodiment, the memory device is over the program circuit, and the wire between the program circuit and the memory is _ __

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I 第9頁 1260629 五、發明說明(6) 基座與可程式結構内的導線構造(conductive wiring scheme)形成 〇 四、【實施方式】 在此’本發明可以用各種不同的功能元件加以說明。 要注意的是這裏所指的功能元件可以用任何數目的硬體或 疋可執行特定功能的架構元件(structurai comp0nent)來 實施。舉例來說,本發明可以採用各種積體元件,其中包 含不同電子裝置,比如說電阻、電晶體、電容、二極體及 類似70件等組成,而元件的數值可經過適當調整以達到特 定的目的。除此之外,本發明可以利用各種積體電路應 用,施以一有效的可逆性偏壓來實施。熟悉此技藝者^可 透過本發明的說明而了解此等廣泛應用,故不在此詳^。 另外要注意的是,儘管在圖示的電路中各種元件已經透過 適當的方式與其他70件麵合或連接,此類的連線和轉人方I. Page 9 1260629 V. INSTRUCTIONS (6) The pedestal is formed by a conductive wiring scheme in a programmable structure. [Embodiment] The present invention can be described by various functional elements. It is to be noted that the functional elements referred to herein can be implemented with any number of hardware or structuring elements that perform a particular function. For example, the present invention can employ various integrated components including different electronic devices, such as resistors, transistors, capacitors, diodes, and the like, and the components can be appropriately adjusted to achieve specific values. purpose. In addition, the present invention can be implemented using a variety of integrated circuit applications with an effective reversible bias. Those skilled in the art will be able to understand such broad applications through the description of the present invention and therefore will not be described in detail herein. It should also be noted that although the various components in the circuit shown have been joined or connected to the other 70 pieces in an appropriate manner, such connections and transfer points

式也可以透過元件之間的直接連線或位於其間的其I 或裝置來連接。 T 八^發明-般與用於可程式微電子裝置之程式電路與包 “王式電路之糸統及其形成方法有關。圖i與圖2所示 發明所揭示的程式電路及其系統巾’形成於基座…為本 面的可程式微電子結構1〇〇與20 0,離子導體14 選 擇性包含的緩衝或障壁層或區域155 。二广 100與200包含電極120與130。 〜構The formula can also be connected by a direct connection between the components or its I or device located therebetween. T 八^ invention-like program circuit and package for programmable microelectronic devices are related to the system of the king circuit and its formation method. The program circuit and system towel disclosed in the invention shown in Fig. i and Fig. 2 Formed on the pedestal ... is a programmable microelectronic structure 1 〇〇 and 20 0, the buffer or barrier layer or region 155 selectively included in the ionic conductor 14. The 广广 100 and 200 comprise electrodes 120 and 130.

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一般來說,結構100與200的作用為,當有一個大於臨 界電壓(threshold V〇ltage)VT的偏壓加在電極12〇與13()之 間時,結構1 00的電子特性就會變化。以下將會對臨界電 壓做進一步的說明。舉例來說,根據本發明的一個實施 例,虽有一個電壓V g ντ加在電極1 2 〇與1 3 〇之間,離子導體 14〇ι中的導電離子開始遷移。並且在或靠近電極12〇與1別 中較負的一立而形成一個區域1 6 0,即電沈殿物 (elecyodeposit),其導電性較離子導體其他大部分的區 域要高。當有區域160形成時,電極12()與丨3〇之間的阻抗 會降低,而其他的電子特性也可能會改變。在沒有任何絕 緣障壁的情況下,用來從一個電極到另一電極成長區域 M0的臨界電壓將會大幅降低裝置阻抗。臨界電壓約等於 系統的氧化還原電位(reducti〇n/oxidal:ic)ri potential),一般在幾百mV左右。上述的絕緣障壁在底下 將會詳細說明。如果反轉同樣電壓的極性,區域丨6〇將會 溶回離子導體,而裝置也會回復高阻抗或抹除的狀態。 結構10 0與20 0可用來儲存資訊,因此可用在記憶體電 路上。舉例來說,在本發明中的結構丨〇 〇與其他可程式化 結構可用來取代DRAM、SRAM、PROM、EPROM、EEPR0M以及 flash等記憶體裝置,或者是上述的組合。除此之外,本 發明所揭不的可程式結構可用在需要程式化或改變電路中 某部份電子特性的應用。In general, the structure 100 and 200 function to change the electronic properties of the structure 100 when a bias voltage greater than the threshold voltage VT is applied between the electrodes 12A and 13(). . The critical voltage will be further explained below. For example, in accordance with an embodiment of the present invention, although a voltage V g ντ is applied between the electrodes 1 2 〇 and 1 3 ,, the conductive ions in the ionic conductor 14 开始 start to migrate. And at or near the opposite of the electrodes 12 〇 and 1 to form a region 160, an elecyodeposit, which is more conductive than most other regions of the ionic conductor. When a region 160 is formed, the impedance between the electrodes 12() and 丨3〇 is lowered, and other electronic characteristics may also be changed. In the absence of any insulating barrier, the threshold voltage used to grow the region M0 from one electrode to the other will significantly reduce the device impedance. The critical voltage is approximately equal to the system's redox potential (reducti〇n/oxidal: ic) ri potential, typically around a few hundred mV. The above insulating barriers will be described in detail below. If the polarity of the same voltage is reversed, the region 丨6〇 will dissolve back into the ionic conductor and the device will return to a high impedance or erased state. Structures 10 0 and 20 0 can be used to store information and can therefore be used on a memory circuit. For example, the structures and other programmable structures in the present invention can be used to replace memory devices such as DRAM, SRAM, PROM, EPROM, EEPR0M, and flash, or a combination thereof. In addition, the programmable structure disclosed in the present invention can be used in applications that require programming or changing some of the electronic characteristics of the circuit.

第11頁 五、發明說明(8) 根據本叙明的各種實施丫列,可程式記憶體,比如說細 胞元〗00或20 0的揮發性(v〇latUity)可藉由改變寫入過程 (w r i t e 〇 p e r a t i ο η )中的能源量,如時間、電流、電麼、 熱能或類似的東西來操縱。在這個情況下,區域丨6〇會在 寫入過耘中幵^成。纟寫入過程中的能源量(其電壓超過 入過程所需的臨界電壓)越高,區域16〇長得越多,因此 =意體的揮發性也越低。反之,&果提供細胞元的能量相 导低,就會形成相當容易抹除的揮發記憶體。所以用來形 成揮發性記憶體和非揮發性記憶體的結構可以相同或相y Τ ’而:來形成揮發性/易於抹除的記憶 ^^l^t^^(p〇rtable electrons devrceV^ 用本身儲存的能量’因此耗電越少越好 性記憶體可以在相同的基座上形成,並藉由心非揮發 (pamuoned)或隔離方式來分開,讓每一 ^八 專注於揮發性或非揮發性記憶體的功能。σ 77可以 :元=利用程式化技術做成揮發性或;4發=細 " 讓β己丨思體的特性,如揮發性或非揮發性,—^ 記憶體陣列中個別部份所受能量來控制。 可藉由改變 回到圖1與圖2,基座110可以包含任 舉例來說,基座110可以包含半導體、導體:^ =物質。 (semi insulat i ve)與絕緣物質等物質,或繞緣 合。根據本發明的一個實施例,基座丨丨 ^物貞的組 匕5絕緣物質11 2 1260629Page 11 V. Description of the Invention (8) According to various implementations of the present description, the readable memory, such as the volatility (v〇latUity) of the cell 00 or 20 0, can be changed by changing the writing process ( Write 〇perati ο η ) The amount of energy, such as time, current, electricity, heat or the like, is manipulated. In this case, the area 丨6〇 will be written in the 耘. The higher the amount of energy in the process of writing (the voltage exceeds the threshold voltage required for the incoming process), the more the region 16〇 grows, so the lower the volatility of the intentional body. Conversely, & the fruit provides a low energy phase of the cell, which results in a volatile memory that is relatively easy to erase. Therefore, the structures used to form volatile memory and non-volatile memory can be the same or phase y ': to form a volatile/easily erased memory ^^l^t^^(p〇rtable electrons devrceV^ The energy stored by itself' therefore consumes less power. The better the memory can be formed on the same pedestal and separated by pamuoned or isolated, allowing each to focus on volatility or non-volatility. The function of volatile memory. σ 77 can be: yuan = use of stylized technology to make volatile or; 4 hair = fine " Let β have the characteristics of the body, such as volatile or non-volatile, -^ memory The individual portions of the array are controlled by the energy. By changing back to Figures 1 and 2, the susceptor 110 can comprise, for example, the susceptor 110 can comprise a semiconductor, a conductor: ^ = substance. (semi insulat i Ve) or a substance such as an insulating material, or a rim. According to one embodiment of the present invention, the group 匕5 insulating material of the susceptor is 11 2 1260629

以及包含形成於半導體基座上的微電子裝置的一區域 11 4。微電子裝置1 1 4可包含用以程式化結構1 〇 〇以及/咬 者1 0 2的程式電路,以下將詳加討論。裝置層11 2與1 1 &可 藉由額外的層(layer)區隔’比如說’一般用來形成積體 電路的層。由於這種可程式結構可以在絕緣物質或其他物 質上形成,因此本發明中所揭示的可程式結構特別適用於 注重基座大小的應用上’比如說半導體物質。此外,在微 電子裝置上覆蓋記憶體細胞元的好處是,這樣的配置可以 讓記憶體細胞元陣列以及微電子裝置間達到更高的資料 輸率。這是因為可在112與150兩層間形成導電路徑、’ (conductive plugs)的緣故。 電極120與130也可以用 例來說,電極1 2 0與1 3 0可以 polysilicon)或金屬來形成 各種合適的導電材料形成>舉 用摻雜多晶矽物質(doped 根據本發明的一個實施例 電極120與130的其中之 :=f解在離子導體140中的金屬的物質形成。 :足夠偏壓(V叫加在電極之間時,其中一個是可f 一而另一個是相當惰性、不會在操作可程式裝中 ,也就是惰性電極。舉例來說,電極咖在V 體二:可以是陽極(anode),並且包含可溶解在離子ί 以是Λ的物負,其中包含銀。而電極130在寫入過程中可 *極,亚且包含鎢(tungsten)、鎳(nickel)、鉬And an area 11 4 including a microelectronic device formed on the semiconductor pedestal. Microelectronic device 1 14 may include program circuitry for stylizing structure 1 / / and / bite 1 0 2 , as discussed in more detail below. The device layers 11 2 and 1 1 & can be separated by an additional layer 'say' to form a layer of an integrated circuit. Since such a programmable structure can be formed on an insulating substance or other substance, the programmable structure disclosed in the present invention is particularly suitable for applications that focus on the size of a pedestal such as a semiconductor material. In addition, the benefit of overwriting memory cells on a microelectronic device is that such a configuration allows for a higher data rate between the memory cell array and the microelectronic device. This is because a conductive path, 'conductive plugs' can be formed between the two layers 112 and 150. Electrodes 120 and 130 may also be used, for example, to form polysilicon or metal to form various suitable conductive materials. > Doped polysilicon material (doped electrode 120 according to one embodiment of the present invention) And 130 of which: =f solves the formation of a metal species in the ionic conductor 140. : Sufficiently biased (when V is applied between the electrodes, one of them is f and the other is rather inert and will not The operation is programmable, that is, the inert electrode. For example, the electrode is in the V body 2: it can be an anode, and contains a substance that is soluble in the ion, which is a negative, containing silver, and the electrode 130 In the process of writing, it can be used, including tungsten (tungsten), nickel (nickel), molybdenum.

第13頁 1260629Page 13 1260629

五、發明說明(10) (/llybdenUm)、白金、金屬矽化物(metai sil1Clde)等相 二、:性物,。至少有一個電極包含可溶解在離子導俨 =的金屬的物質可以幫助維持離子導體14。=屬 的程 從而在使用結構100以及/或者结 =,讓區域16G在離子導體14()内快速且穩定的形 ^ ^者促進其他電子特性改變。此外,採用惰性物質製 作另-個電極’也就是在寫入操作中當作陰極的電極,可 以促進任何區域丨60電解(electr〇diss〇luU〇n)。以及 或者讓可程式裝置受到足夠的電壓時,還原至抹除的 (erased state) 〇 〜 、可程式結構可以用在各種用途,並且由各種物質組 成’比方說根據所需求的寫入或抹除特性而定。各種可程 式結構組態和形成結構的物質已經在2 〇 〇 2年丨〇月9日於美 國提出申請的案號1 0/268, 1 0 7「可程式微電子裝置、結構 與系統及其形成方法(PROGRAMMABLE MICROELECTRONIC device, structure, and system AND METHOD of FORMING THE SAME)」中揭示,在此並引用此申請案的内 容作為說明。 ' 根據本發明的一個實施例,電極120與130中至少一個 是以適合作為内部連結(interconnect)的材料製成。舉例 來說’電極130可以在半導體積體電路中作為内部連結架 構的一部分。在本實施例的一個情況下,形成電極丨3 〇的V. Description of invention (10) (/llybdenUm), platinum, metal telluride (metai sil1Clde) and other phases Second:: sex,. At least one of the electrodes containing a substance that is soluble in the ion guide 俨 = can help maintain the ionic conductor 14. The process of genus thus promotes other electronic property changes by using structure 100 and/or junction = to make region 16G fast and stable in ion conductor 14(). In addition, the use of an inert material as the other electrode', that is, the electrode serving as the cathode in the writing operation, can promote the electrolysis of any region 丨60 (electr〇diss〇luU〇n). And when the programmable device is subjected to sufficient voltage, it is restored to the erased state 〇~, the programmable structure can be used for various purposes, and is composed of various substances, for example, according to the required writing or erasing. Depending on the characteristics. Various programmable structures and structured materials have been filed in the United States on 1st of September 2nd, 1st, 1st, 1st, 1st, 1st, 1st, 1st, The contents of this application are hereby incorporated by reference in its entirety in its entirety. According to one embodiment of the invention, at least one of the electrodes 120 and 130 is made of a material suitable as an internal interconnect. For example, the electrode 130 can be part of an internal interconnect structure in a semiconductor integrated circuit. In one case of this embodiment, the electrode 丨3 形成 is formed

1260629 五、發明說明(11) ,質實際上不能溶解在離子導體14〇所包含的物質中。適 &内部連結與作為電極13G的物f比方像嫣(t s 鎳(m:〇lybdenum)、白金以 (metal si 1 icide)等一類物質。 離子導體1 4 0可以用加上屈釣抱茂外人 皙組成。、_人你炎私 上足夠偏£就會傳導離子的物 (二 九 體140的物質包括高分子聚合物 (polymer)、玻璃與半導艚物暂。产 中,離子導ri4n: 在本發明的一個實施例 :成離子¥體14〇疋以硫系化合物(ChalcGgenide)物質所 離子導體140還可以包含已溶解以及/或者擴散的導 ,物質。舉例來說,離子導體14G可包含溶解金屬以 H金Λ離體溶液。根據本發明的—個實施例,導 =sf明内含已溶解金屬的硫系化合物玻璃, 溶液二:約fu、GexS^ 包括銀、、、在o·、1至0·5之間。其他的硫系化合物物質 體140^可勺5Α以及上述的組合,或者類似的物質。此外,導 離子穿透匕導V::1!正器(network modifier),能夠影響 是銀-類=爾動性(moblllty)。舉例來說,像 、’至屬’以及鹵素(halogen)、鹵化物 第15頁 1260629 五、發明說明(12) (hal ide)、或者是氫等物質。可以加在導體140上,用以 加強離子流動性,從而增加結構在抹除/寫入的速度。此 外,離子導體1 4〇可以包含複數個具有不同阻抗數值的區 域。舉例來說,離子導體1 4 0可以包含一個靠近可氧化電 極的第一區域,其具有相當低的阻抗,以及一個靠近惰性 電極的第二區域,其具有相當南的阻抗。 根據本發明的一個實施例’至少有一部分的結構1 〇 0 是在絕緣物質1 5 0的導孔(V i a )中形成。將一部分的結構 1 〇 0形成在絕緣物質1 5 0的導孔(v i a )中有幾個好處,其中 像是這樣的形成方式可以讓結構變得相當小,可以達到 1 0nm的數量級。此外,絕緣物質1 5 0可隔絕多種結構1 〇 0與 其他電子元件。 絕緣物質1 5 0包含可避免結構1 〇 〇發生不必要的電子以 及/或者離子擴散。根據本發明的一個實施例,物質1 50 包含氮化矽(silicon nitride)、氮氧化矽(silicon oxynitride)以及聚合物如聚亞醯胺(polyimide)、聚對笨 二甲基(parylene)或者是以上物質的組合。 接點1 6 5可以通電至一或多個電極1 2 0、1 3 0 ’以促進 在個別的電極上形成電子接點。接點1 6 5可以利用任何導 電物質形成,最好是金屬、合金或者是包含鋁 (aluminum)、鎢(tungs t en)或銅(c 〇PPer)的組合。1260629 V. Inventive Note (11), the substance is practically insoluble in the substance contained in the ionic conductor 14〇. The internal connection and the material f as the electrode 13G are like a square ts (ts: nickel (m: 〇 b b den 、 、 、 、 、 metal metal metal metal metal metal metal metal metal metal metal metal metal metal metal metal metal metal metal ts ts ts ts ts ts ts ts ts ts ts ts ts ts ts ts ts ts ts ts The composition of the outsiders is 。, _ people you are privately enough to conduct ions (the substances of the ninth body 140 include polymer, glass and semi-conductive sputum temporarily. In production, ion conduction ri4n In one embodiment of the present invention, the ion conductor 140 may also contain a substance that has been dissolved and/or diffused. For example, the ion conductor 14G may be used as the ion-conducting material. Containing a dissolved metal in an aqueous solution of H ruthenium. According to an embodiment of the present invention, a sulfur-based compound glass containing a dissolved metal is contained, and solution 2: about fu, GexS^ includes silver, and · Between 1 and 0. 5. Other sulfur-based compound bodies 140 can be scooped with 5 Α and combinations of the above, or similar substances. In addition, the conductive ions penetrate the VV::1! ), can affect the silver-class = moblllty. For example, Like, 'to the genus' and halogen, halide, page 15, 1260629, invention (12) (hal ide), or hydrogen, etc. may be added to the conductor 140 to enhance ion mobility, Thereby increasing the speed at which the structure is erased/written. Furthermore, the ionic conductor 14 〇 may comprise a plurality of regions having different impedance values. For example, the ionic conductor 1 400 may comprise a first region adjacent to the oxidizable electrode. , which has a relatively low impedance, and a second region near the inertial electrode, which has a relatively south impedance. According to one embodiment of the invention 'at least a portion of the structure 1 〇0 is a guide in the insulating material 150 Formed in the hole (V ia ). There are several advantages to forming a part of the structure 1 〇0 in the via of the insulating material 150, wherein such a formation can make the structure quite small, It reaches the order of 10 nm. In addition, the insulating material 150 can isolate a variety of structures 1 〇 0 from other electronic components. The insulating material 1 50 includes the avoidance of structure 1 不必要 unwanted electrons / or ion diffusion. According to an embodiment of the invention, the substance 150 comprises silicon nitride, silicon oxynitride and polymers such as polyimide, poly-p-dimethylene (parylene) or a combination of the above. Contact 165 can be energized to one or more electrodes 1 2 0, 1 3 0 ' to facilitate the formation of electronic contacts on individual electrodes. Contact 165 can be formed using any conductive material, preferably a metal, an alloy, or a combination comprising aluminum, tungsten (tungs t en) or copper (c 〇 PPer).

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操縱可程式 訊。舉例來說,在寫入過程中::符性’可用來儲存資 關閉狀態變成「1」或導通狀態。 k 0」或 程中可以從「1」變成「〇」。此/ 7 土 /、裝置在抹除過 安口 , 如同美國專利宰申士主 木號1 0 / 2 6 8,1 0 7中所述,結構可撼 ’、甲明 口口 ,4. ^ ^ ^ . 擁有多重可程式狀態,右 早一結構中儲存多位元的資訊。 、71〜、在 寫過程 圖3所示為本發明所揭示的—種可程式結構,例如結 構200的電流一電壓特性表。在圖示的結構中,導孔直徑d 大約4微米(micron),導體140大約3511111厚,由Ge3Se7_Ag (接近A G S a )構成。電極1 3 〇為惰性電極,由鎳 (n i c k e 1 )組成’電極1 2 0由銀組成。而障壁層2 5 5是原始的 氧化鎳(native nickel oxide)。如圖3所示,當施加超過 1 V的電壓於關閉狀態下的結構2 0 〇時,電流開始增加。不 過當寫入過程執行後,也就是有電沈積物產生,導體140 的阻抗會大幅降低至2 0 0 Ω,如圖3的曲線3 2 0所示。如上所 述,當電極1 3 0連接到一個電源供應器較負的一端。此為 相較於電極1 2 0而言,接近電極1 3 0的地方會形成導電區域 (conductive region),並且朝電極120成長。有效的臨界 電壓(threshold voltage),也就是能夠成長導電區域, 並且打穿障壁層255讓電極120與130導電的電壓,是相當 高的。尤其是電壓V - VT必須施加在結構2 0 0上,讓電子可Manipulate the programmable message. For example, during the writing process: : " can be used to store the closed state to "1" or the on state. k 0" or Cheng can be changed from "1" to "〇". This / 7 soil /, the device is erased over the mouth, as described in the US patent Zha Shenshi main wood number 1 0 / 2 6 8, 1 0 7, the structure can be 撼 ', Jia Ming mouth, 4. ^ ^ ^ Have multiple programmable states, and store information about multiple bits in a structure in the right. 71. In the writing process, FIG. 3 shows a programmable current structure, such as a current-voltage characteristic table of the structure 200. In the illustrated construction, the via diameter d is approximately 4 microns (micron) and the conductor 140 is approximately 3511111 thick and is comprised of Ge3Se7_Ag (close to A G Sa ). The electrode 13 3 is an inert electrode composed of nickel (n i c k e 1 ). The electrode 1 2 0 is composed of silver. The barrier layer 255 is the original nickel oxide. As shown in Fig. 3, when a voltage of more than 1 V is applied to the structure 20 〇 in the off state, the current starts to increase. However, when the writing process is performed, that is, when electrodeposits are generated, the impedance of the conductor 140 is greatly reduced to 200 Ω, as shown by the curve 3 2 0 of FIG. As described above, when the electrode 1 30 is connected to the negative end of a power supply. This is a conductive region formed near the electrode 1 30 as compared with the electrode 120, and grows toward the electrode 120. An effective threshold voltage, i.e., a voltage capable of growing a conductive region, and penetrating the barrier layer 255 to conduct the electrodes 120 and 130, is relatively high. In particular, the voltage V - VT must be applied to the structure 200 to make the electrons

第17頁 1260629Page 17 1260629

以穿透由絕緣層組成的障壁層255以形成導電區域。 由穿透或漏電的方式通過障壁層,導通導體丨 二 部分的障壁層255。 ’、王v 节,月的另一個實施例,如果沒有絕緣層存在的 诂要啟動寫入過程所需的電壓就會相當低。i言县么. ::導體140與電極120或13〇任一個之間,沒有絕緣層.、、 關係。 如上所述,要改變本發明中記憶體結構的相對揮發 性’可利用在寫入過程中,施加不同的能量在結構上來達 成。舉例來說,以數百mA的高電流脈衝施加於圖1和圖2的 、’、《構上約數百n s的時間,可以形成相當非揮發性的記憶體 細胞元。另外,同樣的電流也可以加在同樣或相似的結構 上。若時間較短,如數個n s,可以形成具有相當揮發性的 記憶體結構。在任一種情況下,本發明的記憶體可以高速 程式化,即使是揮發性的記憶體還比傳統的DRAM更具非揮 發性。舉例來說,揮發性記憶體的操作速度與DRAM相仿, 但是只需要數個小時更新一次。 讀取過程 要讀取記憶體細胞元的狀態,如「〇」或「1」而不會 明顯的干擾到原來的狀態,可以施加正向或反向的偏壓, 大小比形成電沈積物的臨界電壓要低,比如說圖3中的結The barrier layer 255 composed of an insulating layer is penetrated to form a conductive region. The barrier layer 255 of the two portions of the conductor 导 is conducted through the barrier layer by penetration or leakage. Another embodiment of the month, the month of the month, if there is no insulating layer, the voltage required to initiate the writing process will be quite low. i 言县么. :: Between conductor 140 and electrode 120 or 13 ,, there is no insulation layer, ,, relationship. As described above, changing the relative volatility of the memory structure in the present invention can be utilized in the writing process by applying different energies to the structure. For example, a high current pulse of several hundred mA is applied to the time of construction of Figures 1 and 2, and the configuration is about a few hundred n s to form a relatively non-volatile memory cell. Alternatively, the same current can be applied to the same or similar structure. If the time is short, such as a few n s, a relatively volatile memory structure can be formed. In either case, the memory of the present invention can be programmed at a high speed, and even volatile memory is more non-volatile than conventional DRAM. For example, volatile memory operates at the same speed as DRAM, but only takes a few hours to update. The reading process reads the state of the memory cell, such as "〇" or "1" without significantly interfering with the original state, and can apply a forward or reverse bias, which is larger than the size of the electrodeposited material. The threshold voltage is low, such as the knot in Figure 3.

第18頁 1260629 五、發明說明(15) 構約需1 · 4V。或者是通過低於或等於程式化電流最低限度 的電流’電流會產生最高的導通阻抗值。具有約丨電流 限制的讀取操作過程示於圖3。在這個情況下,電壓會從0 升到2 V ’而電流會在電壓從0至0 · 2 V時,上升到電流限 制’代表達到了一個低阻抗(歐姆/線性電壓一電流)的 導通狀態。另一個不會干擾記憶體狀態的讀取方法是施加 脈衝^時間要相當短。而電壓會比電化學沈積法所需的臨 界電壓要高’以免產生可感知的法拉第電流(Faradaic cuTreni fl〇w),也就是說幾乎所有的電流都會跑去極化 /充電(polarizing/charging)裝置而不會形成電沈積 物0 根 含溫度 用以抵 補償電 態。在 程式結 力口的電 結構會 處於抹 外,溫 過程中 較0 補償裝 銷溫度 路的例 本例中 構和具 壓。如 在已知 除的狀 度補償 和未知 據本發明的不同實施例 S: (temperature 變化對可程式裝 子包含一個可程 ’於讀取過程中 有已知的抹除狀 果未知結構是處 抹除裝置導通前 態,兩個裝置將 電路可用來製造 狀態的可程式結 ,具有可程式結構的 compensation devi 置的效能的影響。一 式結構,具有已知的 ’同時對具有未知狀 態的可程式結構施以 於寫入的狀態,那麼 先行導通。若此未知 會在差不多的時間導 一比較電壓或電流, 構所產生的電壓或電 ce), 個溫度 抹除狀 態的可 逐漸增 此未知 結構係 通。另 在讀取 流相比Page 18 1260629 V. Description of invention (15) The conformation requires 1 · 4V. Or, by a current below or equal to the minimum of the programmed current, the current will produce the highest on-resistance value. The read operation process with a current limit of 丨 is shown in Figure 3. In this case, the voltage will rise from 0 to 2 V ' and the current will rise from 0 to 0 · 2 V, and the current limit ' represents a low impedance (ohmic / linear voltage - current) conduction state. . Another method of reading that does not interfere with the state of the memory is to apply the pulse ^ time is quite short. The voltage will be higher than the threshold voltage required for electrochemical deposition to avoid the generation of a detectable Faraday current (Faradaic cuTreni fl〇w), which means that almost all current will run away from polarization/charging. The device does not form an electrodeposited material. The root temperature is used to compensate for the electrical state. The electrical structure at the end of the program will be outside the wiper, and the temperature will be less than 0 in the case of the compensated pinned temperature path. As is known in the case of the addition of the degree of compensation and unknown embodiments of the invention according to the invention S: (temperature changes to the programmable package contains a processable process in the reading process has a known erased state unknown structure is The erase device turns on the front state, and the two devices use the circuit to make the state of the programmable node, with the performance of the compensating devi setting of the programmable structure. The structure has a known 'simultaneous pair of programs with unknown state The structure is applied to the state of writing, then it is turned on first. If it is unknown, the voltage or current will be compared at a similar time, and the voltage generated by the structure or the electric ce) may gradually increase the unknown structure. System through. Another compared to the read stream

1260629 五、發明說明(16) 抹除過 可 偏壓來 壓大小 貫施例 20 0 上。 Kims, (Ω )。 之間的 寫入所 壁層或 程 =1結構如結構200可藉由在寫入過程中施以反向 未=:而所施加偏壓的量和用來形成電沈積物的電 目二1更大,只不過極性相反。根據本發明的一個 。’足^的抹除電屡(v^vt)在一段時間内施加於結構 二二二紐與寫入過程中施加的能量有關,一般少 ;ί…構20 0回到關閉狀態,阻抗值超過100萬歐姆 Ρ辟可式結構並不包含一層位於導體140與電極12〇 二2二=φ用來抹除結構狀態的臨界電麼會遠小於 . σ , “壓,因為抹除過程不需要讓電子穿透障 讓障壁層崩潰。 喊电卞穿远Ρ早 控制操作 在離 式結構加 導電物質 銀一類的 之一力口入 即可。因 應用需求 壓可以從 加反向偏 電極上的 參數 子導體 以控制 的還原 金屬從 離子導 此,舉 ’就可 可氧化 壓的時 過量金 中的導電物質濃 。舉例來說,在 電位(reduct ion 溶液中取出。反 體’只要施加的 例來說,如果導 以施加反向偏壓 電極提供更多的 間或者是增加抹 屬。我們可利用 度可藉由施加 溶液中施加的 potential) 之,導電物質 電壓超過物質 電物質濃度高 促成還原。而 金屬離子。此 除偏壓可有效 適當的微處理 偏壓於可程 負電壓超過 ’就可以將 可以從電極 的氧化電壓 於裝置特殊 施加正向偏 外’延長施 去除在惰性 為來自動控 第20頁 1260629 細· ' — 五、發明說明(17) 制導電物質。 在本發明的各種實施例中,可程式裝置的臨界電壓可 以利用比如"兒,上述的寫入和抹除程序來加以控制。控 制臨界電壓可以調整可程式裝置,使其符合使用者想要的 讀取或寫入電壓。一般來說,如上所述,臨界電壓與導電 物質在離子導體以及//或者任何障壁層内的量,以及其他 的因素都有關係。 圖4所不為一部分的積體電路4〇2,其中包含可程式結 構40 0二用來提供額外的電子元件隔絕作用。根據本發明 的一個貫施例,結構4〇〇包含電極42〇與43〇,離子導體 4 4 0接點4 6 0以及介於接點4 6 〇與電極4 2 〇間的非結晶石夕二 n接面二極體。可程式化結構 所兩7丁搞、士列可做Λ高密度的組態’用以提供記憶體電路 宓;〜;於儲,:量。一般來說,記憶體裝置的最大儲存 ^:度又限於仃列解碼器電路(r〇w/C〇lumn dec〇der cir^u+itry)大小與複雜性。不過,可程式結構儲 可 ;;覆蓋在積體電路之上,這樣結構4G0不會佔去/座二 0,可將整個半導體晶片面積用在行/列解碼、V列放工大 器以及資料管理電路Γ去祐—、认人处 ^感測放大 Μ祕植- (未顯不)的功旎。如此,使用本發 明所揭不之可程式結構 使用本, 現有的半導體積於電構實際上可視為附加的技術,在 積體東路技術上添增功能與容量。 第21頁 1260629 五、發明說明(18) 圖5繪示出記憶體裝置的一部分,其中結構4〇〇擁 立的Ρ-η接面二極體470,位於記憶體電路的位元線(b^獨 line)510與字元線(word line)52〇的交叉處。圖6所示 另一隔絕方式,係採用介於電極與可程式結構的接點’、、、 (contact)之間的電晶體61〇,可程式結構在記憶體 位元線610與字元線6 20的交又處。 直的1260629 V. INSTRUCTIONS (16) Erasing can be biased to compress the size of the application 20 0 . Kims, (Ω). The writing between the wall layer or the step = 1 structure such as the structure 200 can be performed by applying a reverse bias in the writing process to the amount of bias applied and the electrode used to form the electrodeposit. Bigger, but the opposite polarity. According to one of the inventions. The eraser of the foot ^ (v^vt) is applied to the structure 222 in a period of time and is related to the energy applied during the writing process, generally less; ί...the structure 20 returns to the closed state, and the impedance value exceeds 100. The 10,000 ohm Ρ 可 结构 并不 并不 并不 并不 并不 并不 并不 并不 并不 导体 导体 导体 导体 导体 导体 导体 导体 导体 导体 导体 导体 导体 导体 导体 导体 φ φ φ φ φ φ φ φ φ φ φ φ φ φ φ φ φ The penetrating barrier causes the barrier layer to collapse. The shouting is too long to control the operation in one of the separation structure plus the conductive material silver. The application pressure can be added from the parameters of the reverse bias electrode. The conductor is controlled by the reduced metal from the ion, and the amount of the conductive material in the excess gold is concentrated when the oxidative pressure is applied. For example, the potential is taken in the reduct ion solution. If the electrode is applied with a reverse bias to provide more space or to increase the genus, the usability can be achieved by applying a potential applied in the solution, and the voltage of the conductive substance exceeds the concentration of the substance. Originally, the metal ion. This bias can be effectively and appropriately micro-processed to bias the negative voltage over the 'can be used to remove the oxidation voltage from the electrode to the device. Automatic Control Page 20 1260629 细·' - 5, Invention Description (17) Conductive Substance. In various embodiments of the present invention, the threshold voltage of the programmable device can be utilized, for example, ", writing and erasing as described above The program controls it. The control threshold voltage adjusts the programmable device to match the read or write voltage desired by the user. In general, as described above, the threshold voltage and conductive material are in the ionic conductor and/or any The amount in the barrier layer, as well as other factors, is related. Figure 4 is not a part of the integrated circuit 4〇2, which contains a programmable structure 40 0 for providing additional electronic component isolation. According to the present invention In one embodiment, the structure 4〇〇 includes electrodes 42〇 and 43〇, the ion conductor 4 4 0 contacts 4 6 0, and the amorphous stone between the junction 4 6 〇 and the electrode 4 2 〇 Two n-junction diodes. Two-segmented structure can be programmed, and the high-density configuration can be used to provide memory circuit 宓; ~; storage, amount: in general, memory The maximum storage of the device is limited to the size and complexity of the decoder circuit (r〇w/C〇lumn dec〇der cir^u+itry). However, the programmable structure can be stored; Above the circuit, the structure 4G0 will not occupy/seat 2, and the entire semiconductor wafer area can be used in row/column decoding, V-column processing, and data management circuits. Μ Secret plant - (not shown) merits. Thus, using the programmable structure disclosed in the present invention, the existing semiconductor product can be regarded as an additional technology in the actual structure, and the function and capacity are added to the integrated East Road technology. Page 21 1260629 V. Description of the Invention (18) FIG. 5 illustrates a portion of a memory device in which a structure 〇〇 η η 接 junction diode 470 is located in a bit line of a memory circuit (b^ The line 510 is at the intersection of the word line and the word line 52〇. Another isolation mode shown in FIG. 6 is to use a transistor 61 between the electrodes and the contacts of the programmable structure, and the programmable structure is in the memory bit line 610 and the word line 6. 20 is handed over again. straight

圖7所示為一示範電路700,用以改變如圖i、2及4 示之可程式裝置等微電子裝置之電子特性。一般來說, 路700可用來提供充足、可逆的壓降於可程式結構上,以 執行上述之寫入和抹除功能。 電路70 0包含第一輸入7〇2耦合至可程式裝置7〇6之第 一區域704,第二輸入710耦合至第一開關712與第二開關 714,電壓源716耦合至開關714,而接地718耦合至開關 712。在本實施例中,裝置7〇6的第二區域7〇8耦合至第一 開關與第二開關。根據本實施例的一個示範情況,開關 Ή2和開關714形成一個互補金氧半導體(CM〇s)裝置。其中 開關714為p通道(p-channel)電晶體,而開關712為11通道 (n-channel)半導體。CM0S裝置的輪出72〇耦合至可程式裝 置706的第二區域708。在本例中,輸入71〇係耦合至卩通道 電晶體和η通迢電晶體的閘級(gate) ^開關712和714組成 一部份的CMOS裝置,可以讓讀取和寫入操作所消耗的功率Figure 7 shows an exemplary circuit 700 for varying the electronic characteristics of a microelectronic device such as the programmable device shown in Figures i, 2 and 4. In general, the path 700 can be used to provide a sufficient, reversible voltage drop across the programmable structure to perform the write and erase functions described above. The circuit 70 0 includes a first input 7〇2 coupled to the first region 704 of the programmable device 7〇6, a second input 710 coupled to the first switch 712 and the second switch 714, the voltage source 716 coupled to the switch 714, and grounded 718 is coupled to switch 712. In the present embodiment, the second region 7〇8 of the device 7〇6 is coupled to the first switch and the second switch. According to an exemplary case of the embodiment, the switch Ή2 and the switch 714 form a complementary MOS device. Wherein switch 714 is a p-channel transistor and switch 712 is an 11-channel (n-channel) semiconductor. The turn 72 of the CMOS device is coupled to the second region 708 of the programmable device 706. In this example, the input 71 is coupled to the gate of the channel transistor and the gate of the η transistor. The switches 712 and 714 form part of the CMOS device, which can be consumed by the read and write operations. Power

1260629 五、發明說明(19) 相當低,同時讓電路70 0易於製造。在本實施例的另一情 況下。P通道電晶體7 1 4可以換成一個被動負載,比如說電 阻(多晶矽電阻)或一個主動負載(比如空乏模式 (depletion mode)的MOS電晶體)。同樣地,如上所述, 此CMOS裝置可以形成在基座,比如說基座1丨〇内,而可程 式裝置706可覆蓋於基座之上。 在操作中,當可程式裝置706係處於非寫入或抹除狀 態,且有一低電壓,比如說〇V的電壓施加在輸入7〇2與71〇 上’ 1置7 0 6的惰性電極(區域7 〇 8 )相較於可溶解電極 (區域704 )係處於正偏壓。在這個狀態下,將不會發生 寫入的動作。當有正電壓,大約接近Μ的正電壓一一 near +V)施於輸入702與710上,區域7〇8的電壓將會降至 大約0V。只要輸入端7〇2的正電壓夠大,讓壓降超^寫入 臨界電壓,差不多20 0至30 0mV,電路70 0將會對裝置7〇6執 行上述的寫入功能。如果要抹除裝置7〇6,可以施加約〇v 的低電壓於輸入702與710上,讓裝置7〇6的區域7〇8相 裝置70 6的區域704為正偏壓。另外,相反極性的電壓也可 施加在輸入702與710上,以達到上述的寫入和抹除功能。 圖8所示為本發明另一實施例中的電路8〇〇,係用 式化可程式結構。電路8〇〇與電路7〇〇相似,除了電路_ 僅包含一個單一輸入802,並額外地包含一選擇輸入和 開關8 0 6,用以啟動讀取或寫入功 巧月£* °1260629 V. Description of the invention (19) is quite low, while making the circuit 70 0 easy to manufacture. In another case of this embodiment. The P-channel transistor 7 1 4 can be replaced by a passive load such as a resistor (polysilicon resistor) or an active load (such as a depletion mode MOS transistor). Similarly, as described above, the CMOS device can be formed in a pedestal, such as a pedestal, and the configurable device 706 can overlie the pedestal. In operation, when the programmable device 706 is in a non-write or erase state and has a low voltage, for example, a voltage of 〇V is applied to the input electrodes 7〇2 and 71〇' Region 7 〇 8 ) is positively biased compared to the soluble electrode (region 704 ). In this state, the write action will not occur. When there is a positive voltage, approximately a positive voltage close to Μ, near +V) is applied to inputs 702 and 710, the voltage in region 7〇8 will drop to approximately 0V. As long as the positive voltage at the input terminal 7〇2 is large enough to allow the voltage drop to exceed the threshold voltage, which is approximately 20 to 30 mV, the circuit 70 0 will perform the above-described write function to the device 7〇6. If device 7〇6 is to be erased, a low voltage of about 〇v can be applied to inputs 702 and 710 such that region 7〇8 of device 7〇6 phase 704 of device 70 6 is positively biased. Alternatively, voltages of opposite polarity can be applied to inputs 702 and 710 to achieve the write and erase functions described above. Figure 8 is a diagram showing a circuit 8 in another embodiment of the present invention, which is a programmable program. Circuit 8 is similar to circuit 7 except that circuit _ contains only a single input 802 and additionally includes a select input and switch 8 0 6 to initiate a read or write function of £*°

第23頁 1260629 五、發明說明(20) 在電路800操作中,施加一適當的偏壓,比如說1至… 的正電壓(1 t0 5V - near +V)於輸入8〇4以導通開關 6可執行寫入或抹除的功能。開關8 〇 β在本發明的圖示 =施例中為MOS電晶體。一旦啟動後,施加高電壓,比如 :兒1至5V的正電壓(1 to — near +ν)於輸入,可執 行寫入的功能。而施加低電壓,大約〇ν的電壓於輸入8〇2 可執行抹除的功能。在寫入過程中,裝置7〇6的阻抗會降 ,。這個現象可用來限制程式化效應,因為隨著程式化過 私的進行,輸入8〇2處的電壓會被拉低。 圖9所示為本發明的另一電路9〇〇。電路9〇〇與電路 j似,除了可程式結構706相對於輸入8〇2的方向相反。在 這個例子中,施加一低電壓於輸入8〇2會產生寫入的動 作’而施加高電壓於輸入80 2會產生抹除的動作。 圖10所示為包含複數個可程式裝置1 0 02至1 0 06之 1 00 0。電路1 00 0可形成記憶體陣列的一部分,比如說陣 的某一行的一部分。電路丨00 0與電路80 0相似,除了°電1 1 0 0 0包含複數個選擇輸入丨0 08至1012,複數個可程式' 路 置,以及複數個選擇開關,比如說MOS電晶體丨〇丨4至"t 1 〇 18。根據本發明的一個實施例,單一可程式裝置可〜 導通相關的選擇開關,進行讀取或寫入的操作=σ藉由Page 23 1260629 V. INSTRUCTIONS (20) In operation of circuit 800, an appropriate bias voltage, such as a positive voltage of 1 to 0 (1 t0 5V - near +V) is applied to input 8〇4 to turn on switch 6 The function of writing or erasing can be performed. The switch 8 〇 β is in the illustration of the invention = MOS transistor in the embodiment. Once started, apply a high voltage, such as a positive voltage of 1 to 5V (1 to – near +ν) to the input to perform the write function. When a low voltage is applied, the voltage of 〇ν can be erased by inputting 8〇2. During the writing process, the impedance of the device 7〇6 will drop. This phenomenon can be used to limit the stylization effect, because the voltage at input 8〇2 will be pulled down as the stylization proceeds. Figure 9 shows another circuit 9 of the present invention. Circuit 9 is similar to circuit j except that the programmable structure 706 is opposite in direction to the input 8〇2. In this example, applying a low voltage to the input 8〇2 will cause a write operation' and applying a high voltage to the input 80 2 will cause an erase action. Figure 10 shows a 00 0 comprising a plurality of programmable devices 1 0 02 to 1 0 06. Circuit 1000 may form part of a memory array, such as a portion of a row of arrays. The circuit 丨00 0 is similar to the circuit 80 0 except that the power 1 1 0 0 0 includes a plurality of select inputs 丨0 08 to 1012, a plurality of programmable 'channels, and a plurality of select switches, such as MOS transistors 丨〇丨4 to "t 1 〇18. According to an embodiment of the present invention, a single programmable device can turn on a related selection switch to perform a read or write operation = σ by

第24頁 1260629Page 24 1260629

五、發明說明(21) 的是2 = 圖示加以說明,”要注意 雖然在程式電路中以Μ(^φ日妒特疋i心舉例來說, 吩甲以M0S電日日體作為開關,但是本 不在此限。本發明所用的電路可以附加或以雙載子電晶體 (bipolar t irans is tor)或是類似的元件來形成圖示中的開 關。熟悉此技藝者可根據此處所載之說明,在不違背本發 明所載的專利申請範圍之精神與範疇的情況下,針對設計 以及方法與衣置的女排,做各種其他修正、變化或加強。5. The description of the invention (21) is 2 = the illustration is given, "note that although in the program circuit, the ^ ^ ^ 举例 举例 举例 举例 举例 举例 举例 举例 举例 举例 举例 举例 举例 举例 举例 举例 举例 举例 举例 举例 举例 举例 举例 以 以 以 以 以 , , , , , However, the circuit used in the present invention may be additionally or in the form of a bipolar t irans is tor or similar element to form the switch in the figure. Those skilled in the art may It is to be understood that various modifications, changes, or enhancements may be made to the design and method of dressing and dressing for women's volleyball without departing from the spirit and scope of the patent application scope of the present invention.

第25頁 1260629 圖式簡單說明 五、【圖式簡單說明】 有關本發明的進一步說明將在接下來的詳細說明與申 請專利範圍中逐次闡述,並搭配相關的圖示加以說明,其 中類似的參考數字圖示中類似的元件,其中: 圖1、2與4係本發明中形成於一基座表面的可程式結構的 截面圖示; 圖3係電流一電壓圖,係用來繪示本發明所揭示的裝置的 電流與電壓特性; 圖5與6係本發明的一個實施例中的記憶體裝置的一部份; 以及 圖7至1 0係本發明所揭示之程式電路。 熟悉本技藝者可以了解圖中元件係以簡單清楚為目 的,並不一定依照實際的尺寸比例繪示。舉例來說,圖中 某些元件的尺寸可以會較為誇大,以協助了解本發明的各 種實施例。 I 10基座 II 4區域 1 3 0、4 3 0 電極 1 5 0絕緣物質 1 6 0區域 元件符號說明 1 0 0、2 0 0、4 0 0 結構 1 1 2絕緣物質 1 2 0、4 2 0 電極 140、440離子導體 155、25 5 區域 1 6 5接點 402積體電路Page 25 1260629 Brief Description of the Drawings [Flat Description] A further description of the present invention will be explained in the following detailed description and the scope of the patent application, and will be described with reference to the accompanying drawings Similar elements in the figures, wherein: Figures 1, 2 and 4 are cross-sectional illustrations of a programmable structure formed on a surface of a substrate in the present invention; Figure 3 is a current-voltage diagram used to illustrate the invention The current and voltage characteristics of the disclosed device; Figures 5 and 6 are part of a memory device in one embodiment of the present invention; and Figures 7 through 10 are circuit circuits disclosed herein. Those skilled in the art will appreciate that the elements of the figures are for the purpose of simplicity and clarity and are not necessarily shown in the actual scale. For example, the dimensions of some of the elements in the figures may be exaggerated to assist in understanding various embodiments of the invention. I 10 pedestal II 4 area 1 3 0, 4 3 0 electrode 1 5 0 insulating material 1 6 0 area element symbol description 1 0 0, 2 0 0, 4 0 0 structure 1 1 2 insulating material 1 2 0, 4 2 0 electrode 140, 440 ion conductor 155, 25 5 area 1 6 5 contact 402 integrated circuit

第26頁 1260629 圖式簡單說明 4 6 0接點 5 1 0位元線 6 1 0電晶體 6 2 0字元線 70 2第一輸入 706可程式裝置 710第二輸入 7 1 4第二開關 7 1 8接地 80 0電路 804選擇輸入 90 0電路Page 26 1260629 Schematic description 4 6 0 contact 5 1 0 bit line 6 1 0 transistor 6 2 0 word line 70 2 first input 706 programmable device 710 second input 7 1 4 second switch 7 1 8 ground 80 0 circuit 804 select input 90 0 circuit

1 0 02、1 0 04、1 0 06 可程 1 008、1010、1012 選擇 1014 、 1016 、 1018 MOS 4 7 0二極體 5 2 0字元線 6 1 5位元線 7 0 0示範電路 704第一區域 708第二區域 7 1 2第一開關 7 1 6電壓源 720輸出 802單一輸入 806開關 1 00 0電路 式裝置 輸入 電晶體1 0 02, 1 0 04, 1 0 06 Reachable 1 008, 1010, 1012 Select 1014, 1016, 1018 MOS 4 7 0 Dipole 5 2 0 Word Line 6 1 5 Bit Line 7 0 0 Demonstration Circuit 704 First region 708 second region 7 1 2 first switch 7 16 voltage source 720 output 802 single input 806 switch 1 00 0 circuit device input transistor

第27頁Page 27

Claims (1)

1260629 4.2〇 案號 92100098_[η—— 六、申請專利範圍 丨月(更)正:f丨 1 · 一種用以程式化一微電子記ti、籍裒ΐ ( m i c r 〇 e 1 e c t r ο n i c memory device)之電路,該電路包含: 一第一輸入耦合至該記憶體裝置之一第一區域;以及 一第二輸入耦合至一第一開關與一第二開關,該第一 開關I禺合至一電壓源(v ο 1 t a g e s 〇 u r c e ),而該第二開關親 合至接地(ground); 其中該電路係用以提供一第一偏壓(b i a s )與一第二偏 壓給該記憶體裝置,其中該第一偏壓的極性與該第二偏壓 的極性相反。 2. 如申請專利範圍第1項所述之電路,其中該第一開關與 第二開關形成一CMOS裝置。 3. 如申請專利範圍第2項所述之電路,其中該CMOS裝置之 一輸出係耦合至該記憶體裝置之一第二區域。1260629 4.2〇案号92100098_[η——6. The scope of application for patents is (月(more) 正: f丨1 · A program used to program a microelectronic record ti, 裒ΐ (micr 〇e 1 ectr ο nic memory device a circuit comprising: a first input coupled to a first region of the memory device; and a second input coupled to a first switch and a second switch, the first switch I coupled to a a voltage source (v ο 1 tages 〇urce ), and the second switch is in contact with a ground; wherein the circuit is configured to provide a first bias and a second bias to the memory device Wherein the polarity of the first bias is opposite to the polarity of the second bias. 2. The circuit of claim 1, wherein the first switch and the second switch form a CMOS device. 3. The circuit of claim 2, wherein an output of the CMOS device is coupled to a second region of the memory device. 4S&W0301TW-ΑΧΟΝ-替換頁-042] 06.pt c 第28頁 1260629 95. 4, 25 ____ 案號 92100098 _年月日 修正 六、申請專利範圍 子特性之電路,該電路包含: 一寫入輸入(w r i t e i n p u t ) _合至該微電子裝置之一 第一區域; 一選擇開關(select switch)搞合於該寫入輸入與該 微電子裝置之第一區域之間; 一第一開關耦合至該寫入輸入與一電壓源;以及 一第二開關搞合至該寫入輸入與接地(g r 〇 u n d ), 其中該第一開關與該第二開關耦合至該微電子裝置之 一第二區域,以及 其中該電路係用以提供一第一偏壓(b i a s )與一第二偏 壓給該微電子裝置,其中該第一偏壓的極性與該第二偏壓 的極性相反。 7. 如申請專利範圍第6項所述之電路,其中該第一開關與 第二開關形成一CMOS裝置。 8. 如申請專利範圍第7項所述之電路,其中該選擇開關包 含一M0S 電晶體(transistor)。 9. 如申請專利範圍第6項所述之電路,其中該微電子裝置 包含一離子導體物質,係選自以下的族群:玻璃 (glass)、半導體物質(semiconductor material)、石荒系 化合物(chalcogenide)物質以及高分子聚合物(polymer) 物質。4S&W0301TW-ΑΧΟΝ-Replacement page-042] 06.pt c Page 28 1260629 95. 4, 25 ____ Case No. 92100098 _ 月月日日 Revision 6. Circuit for applying patent range sub-characteristics, the circuit contains: Input (writeinput) is coupled to a first region of the microelectronic device; a select switch is coupled between the write input and the first region of the microelectronic device; a first switch coupled to the Writing a input to a voltage source; and a second switch engaging the write input and ground (gr 〇und ), wherein the first switch and the second switch are coupled to a second region of the microelectronic device, And wherein the circuit is configured to provide a first bias and a second bias to the microelectronic device, wherein the polarity of the first bias is opposite to the polarity of the second bias. 7. The circuit of claim 6 wherein the first switch and the second switch form a CMOS device. 8. The circuit of claim 7, wherein the selection switch comprises a MOS transistor. 9. The circuit of claim 6, wherein the microelectronic device comprises an ion conductor material selected from the group consisting of glass, semiconductor material, and chalcogenide. ) substances and polymers. 4S&W0301TW - ΑΧΟΝ -替換頁-04 2106. p t c 第29頁 1260629 95. 4.2;> 案號92100098_年月日 修正 六、申請專利範圍 1 0 .如申請專利範圍第6項所述之電路,其中該第一區域包 含可溶性電極物質。 1 1 .如申請專利範圍第6項所述之電路,其中該第二區域包 含惰性電極物質。 1 2 .如申請專利範圍第6項所述之電路,其中該第一區域包 含惰性電極物質。 1 3 .如申請專利範圍第6項所述之電路,其中該第二區域包 含可溶性電極物質。 1 4.如申請專利範圍第6項所述之電路,進一步包含複數個 微電子裝置耦合至該第一開關與該第二開關。 1 5 .如申請專利範圍第1 4項所述之電路,進一步包含複數 個選擇開關耦合至該寫入輸入。 1 6 . —種用以程式化一可程式結構之電路,該電路包含: 一寫入輸入(write input) |禺合至該結構之一第一區 域; 一CMOS電晶體,該CMOS電晶體之一輸出耦合至該結構 之一第二區域與該寫入輸入;以及4S&W0301TW - ΑΧΟΝ - Replacement page -04 2106. ptc Page 29 1260629 95. 4.2;> Case No. 92100098_ Year Month Day Amendment VI, Patent Application Range 10. The circuit described in claim 6 Wherein the first region comprises a soluble electrode species. The circuit of claim 6, wherein the second region comprises an inert electrode material. The circuit of claim 6, wherein the first region comprises an inert electrode material. The circuit of claim 6, wherein the second region comprises a soluble electrode material. The circuit of claim 6, further comprising a plurality of microelectronic devices coupled to the first switch and the second switch. The circuit of claim 14 further comprising a plurality of select switches coupled to the write input. A circuit for programming a programmable structure, the circuit comprising: a write input | coupled to a first region of the structure; a CMOS transistor, the CMOS transistor An output coupled to the second region of the structure and the write input; 4S&W0301TW- ΑΧΟΝ -替換頁-042106. p t c 第30頁 1260629 95乂 25 案號92100098_ 年 月 日 修正 六、申請專利範圍 一選擇電晶體(select transistor)搞合於該寫入輸 入與該可程式結構之間,其中該可程式結構包含一離子導 體與分佈於該離子導體内之傳導物質(conductive material ) 〇 1 7.如申請專利範圍第1 6項所述之電路,進一步包含複數 個可程式結構耦合至該CMOS電晶體之輸出。 1 8.如申請專利範圍第1 6項所述之電路,進一步包含複數 個選擇電晶體耦合至該寫入輸入。 1 9 .如申請專利範圍第1 6項所述之電路,其中該選擇電晶 體係一M0S電晶體。4S&W0301TW- ΑΧΟΝ-Replacement page-042106. ptc Page 30 1260629 95乂25 Case No. 92100098_ Year Month Day Amendment VI, Patent Application Scope Select transistor selects the write input and the programmable Between the structures, wherein the programmable structure comprises an ionic conductor and a conductive material distributed in the ionic conductor 7.1. 7. The circuit of claim 16 further comprising a plurality of programmable The structure is coupled to the output of the CMOS transistor. 1 8. The circuit of claim 16 further comprising a plurality of select transistors coupled to the write input. The circuit of claim 16 wherein the electro-optic system is a MOS transistor. 4S&W0 3 01TW - ΑΧΟΝ -替換頁-04 2 丨 06 p t c 第31頁4S&W0 3 01TW - ΑΧΟΝ - Replacement page -04 2 丨 06 p t c Page 31
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