JP2003272376A - Ferroelectric memory - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a ferroelectric memory in which disturbance resistance in a memory cell of non-selection can be improved. <P>SOLUTION: This ferroelectric memory is provided with bit lines, word lines arranged so as to intersect to the bit lines, and a memory cell 1 arranged between the bit lines and the word lines and comprising a ferroelectric capacitor 2 and one diode 3 connected to the ferroelectric capacitor 2 in series. <P>COPYRIGHT: (C)2003,JPO

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a ferroelectric memory, and more particularly to a ferroelectric memory having a ferroelectric capacitor.

[0002]

2. Description of the Related Art In recent years, a ferroelectric memory has been attracting attention as a high speed and low power consumption non-volatile memory. For this reason, research and development on ferroelectric memories are being actively conducted. FIG. 15 is a typical circuit diagram of a conventional and most commonly used ferroelectric memory, and FIG. 16 is a sectional structure diagram corresponding to FIG. 15 and 16
In this conventional structure, element isolation region 102 is formed in a predetermined region on the surface of semiconductor substrate 101. A source region 103 and a drain region 104 are formed in the element formation region surrounded by the element isolation region 102 with a predetermined interval. Source region 103
Over the channel region located between the drain region 104 and the drain region 104, the word line (WL) via the gate insulating film 105.
Forming the gate electrode 106. A bit line (BL) 113 is electrically connected to the drain region 104.

A lower electrode 109 is formed in the source region 103 via a plug electrode 108. An upper electrode 111 that forms a plate line (PL) is formed on the lower electrode 109 via a ferroelectric layer 110. The lower electrode 109, the ferroelectric layer 110, and the upper electrode 111 form a ferroelectric capacitor 112. In addition, the source region 103 and the drain region 104, the gate insulating film 105, and the gate electrode 10
The transistor 107 is composed of 6 and 6.
The transistor 107 functions as a switch that selects a memory cell. Also, as shown in FIG.
One memory cell 100 has one transistor 107
And one ferroelectric capacitor 112.

However, in the structure of the conventional ferroelectric memory shown in FIGS. 15 and 16, one memory cell 100 is composed of one transistor 107 and one ferroelectric capacitor 112. There is a disadvantage that the area of the memory cell is relatively large.

Therefore, conventionally, a ferroelectric memory having a simple matrix type ferroelectric capacitor in which one memory cell is composed of only one ferroelectric capacitor has been developed.

FIG. 17 is a circuit diagram of a conventional simple matrix type ferroelectric memory, and FIG. 18 is a sectional structural view corresponding to FIG. Referring to FIGS. 17 and 18, in the conventional simple matrix ferroelectric memory,
A ferroelectric layer 202 is formed on the bit line (BL) 201. Then, the word line (WL) 203 is formed on the ferroelectric layer 202 in a direction intersecting with the bit line 201.
Are formed. The bit line 201 and the ferroelectric layer 2
02 and the word line 203 form a ferroelectric capacitor 210. In this simple matrix type ferroelectric memory, as shown in FIG. 17, one memory cell 200 is composed of only one ferroelectric capacitor 210.

FIG. 19 is a circuit diagram for explaining a voltage application method during a write operation by the 1/2 Vcc method of a conventional simple matrix type ferroelectric memory, and FIG.
Is 1 / th of the conventional simple matrix ferroelectric memory
FIG. 7 is a circuit diagram for explaining a voltage application method during a write operation by the 3Vcc method.

Referring to FIG. 19, in the case of the conventional 1/2 Vcc method, in order to drive a selected memory cell (selected cell), a bit line BL ₁ and a word line W connected to the selected cell are connected.
A voltage of Vcc is applied between it and L ₁ . That is, the power supply voltage Vcc is applied to the word line WL ₁ and 0 V is applied to the bit line BL ₁ . Then, ₀ V is applied to the word lines WL ₀ and WL ₂ connected to the non-selected memory cells (non-selected cells), and _1/2 Vcc is applied to the bit lines BL ₀ and BL ₂ connected to the non-selected cells. .
As a result, a voltage of Vcc is applied to the selected cell and 1/2 Vcc is applied to the non-selected cell.

Further, referring to FIG. 20, the conventional 1 / 3V
In the case of the cc method, the power supply voltage Vcc is applied to the word line WL ₁ and 0 V is applied to the bit line BL ₁ . Then, 1/3 Vcc is applied to the word lines WL ₀ and WL ₂ connected to the unselected memory cells (non-selected cells), and 2/3 Vcc is applied to the bit lines BL ₀ and BL ₂ connected to the unselected cells. Apply. As a result, the voltage of Vcc is applied to the selected cell and 1/3 Vcc is applied to the non-selected cell.

In the above case, the ferroelectric layer 202 of the selected cell
(See FIG. 18), it is necessary that the polarization inversion be sufficiently saturated and that the polarization state of the ferroelectric layer of the non-selected cell hardly changes.

[0011]

However, at present, since the square shape of the ferroelectric hysteresis is not sufficient, as shown in FIG. 21, 1/2 Vcc is applied to the non-selected cells.
Alternatively, if 1/3 Vcc is continuously applied in the same direction, so-called disturb occurs in which the information (charge amount) is lost. When such a disturbance occurs, the information written in the non-selected cells is lost, so that it is difficult to use it as a ferroelectric memory.
Therefore, at present, it is considered difficult to put the ferroelectric memory having the simple matrix structure shown in FIGS. 17 and 18 into practical use.

The present invention has been made to solve the above problems, and one object of the present invention is to:
It is an object of the present invention to provide a ferroelectric memory capable of improving the resistance to disturbance in unselected memory cells.

Another object of the present invention is to put a simple matrix type ferroelectric memory into practical use by improving the disturbance resistance in unselected memory cells.

[0014]

In order to achieve the above object, a ferroelectric memory according to a first aspect of the present invention comprises a bit line, a word line arranged to intersect the bit line, a bit line and a word line. And a memory cell including a ferroelectric capacitor and a diode connected in series to the ferroelectric capacitor.

According to the first aspect of the present invention, by providing the memory cell including the ferroelectric capacitor and the diode connected in series to the ferroelectric capacitor as described above, in the voltage range where almost no current flows through the diode. Since the resistance of the diode becomes almost infinite, most of the voltage is applied to the diode, and almost no voltage is applied to the ferroelectric capacitor. Therefore, when writing or reading data, if a voltage in the range in which almost no current flows through the diode is applied to the non-selected cell, almost no voltage is applied to the ferroelectric capacitor, so that in the simple matrix ferroelectric memory, Disturbance of the selected cell can be avoided. As a result, it is possible to improve the disturbance resistance of the non-selected cells in the simple matrix ferroelectric memory. As a result, a simple matrix type ferroelectric memory can be put to practical use.

According to a second aspect of the present invention, in the ferroelectric memory according to the first aspect, when the ON voltage and the breakdown voltage of the diode are Vt and Vb, respectively,
The standby voltage of the bit line and the word line is (Vt + V
b) <Standby voltage <0. With this configuration, compared to the case where the standby voltage is 0V,
Since the standby voltage is close to the center of the hysteresis characteristic of the memory cell composed of the ferroelectric capacitor and the diode, compared with the case where the standby voltage is 0V,
It is possible to increase resistance to noise when writing or reading is not performed. In this case, it is preferable to set the standby voltage to (Vt + Vb) / 2. With this configuration, it is possible to further enhance resistance to noise when writing or reading is not performed.

According to a third aspect of the present invention, in the ferroelectric memory according to the first or second aspect, at least one of data writing and reading is performed by applying an asymmetric voltage pulse to the bit line and the word line. To do.
According to this structure, it is possible to easily write or read data by using the ferroelectric memory according to the first aspect.

According to a fourth aspect of the present invention, in the ferroelectric memory according to any one of the first to third aspects, when a high voltage is applied to the ferroelectric capacitor, polarization inversion occurs and the ferroelectric capacitor has a low voltage. A pulse applying unit for applying a pulse having a predetermined pulse width that does not substantially cause polarization inversion when a voltage is applied, is further provided, and at least one of data writing and reading is provided. At one time, a high voltage pulse having a predetermined pulse width is applied to the selected memory cell, and a low voltage pulse having a predetermined pulse width is applied to the non-selected memory cells. According to this structure, writing or reading can be performed with respect to the selected memory cell, and almost no polarization inversion can occur with respect to the non-selected memory cell. As a result, it is possible to further improve the disturbance resistance in the non-selected memory cells.

According to a fifth aspect of the present invention, in the ferroelectric memory according to any one of the first to fourth aspects, the diode is a p-type formed by joining a p-type semiconductor layer and an n-type semiconductor layer.
Includes n-junction diode. According to this structure, it is possible to form a diode whose characteristics are not deteriorated even by annealing (heat treatment) for crystallizing the ferroelectric layer.

According to a sixth aspect of the present invention, in the ferroelectric memory according to any one of the first to fourth aspects, the diode is formed by a junction of a p-type region and an n-type region formed on a semiconductor substrate. Includes junction diode. With this structure, the cell size can be reduced and annealing (heat treatment) for crystallization of the ferroelectric layer is performed.
It is possible to form a diode whose characteristics are not deteriorated by the above.

According to a seventh aspect of the present invention, in the ferroelectric memory according to any one of the first to fourth aspects, the diode includes a Schottky diode formed by joining a conductive layer and a semiconductor layer. According to this structure, it is possible to form a diode whose characteristics are not deteriorated even by annealing (heat treatment) for crystallizing the ferroelectric layer.

In the above ferroelectric memory, the conductive layer forming the Schottky diode contains metal and silicon, and the metal is Ir, Pt, Ru, Re,
At least one selected from the group consisting of Ni, Co, and Mo may be included. The conductive layer forming the Schottky diode contains a metal, nitrogen and silicon, and the metal is Ir, Pt, Ru or R.
At least one selected from the group consisting of e, Ni, Co, and Mo may be included. According to this structure, a thermally stable Schottky junction can be formed.

In the structure of claim 4, the p-type semiconductor layer and the n-type semiconductor layer may include an amorphous layer. According to this structure, fine pn junction diodes can be uniformly manufactured.

Further, in the structure of claim 7, the semiconductor layer forming the Schottky diode may include an amorphous layer. According to this structure, fine Schottky diodes can be uniformly manufactured.

In the structure according to any one of claims 1 to 4, the diode includes a p-type region or an n-type region formed on the semiconductor substrate, and a conductive layer formed on the p-type region or the n-type region. The Schottky diode formed by the junction of may be included. According to this structure, the cell size can be reduced, and a diode whose characteristics do not deteriorate even by annealing (heat treatment) for crystallizing the ferroelectric layer can be formed.

An invention directed to the following method of operating a ferroelectric memory is also conceivable. That is, the operation method of the ferroelectric memory is as follows: a bit line, a word line arranged so as to intersect with the bit line, a bit line and a word line, and a ferroelectric capacitor and a ferroelectric capacitor. A method of operating a ferroelectric memory, comprising: a memory cell including a diode connected in series to a bit line, and writing or reading binary data by applying an asymmetric voltage pulse to a bit line and a word line. I do. According to this structure, the resistance of the diode becomes almost infinite in the voltage range in which almost no current flows through the diode, so that most of the voltage is applied to the diode and almost no voltage is applied to the ferroelectric capacitor. Therefore,
When writing or reading data, if a voltage in the range where almost no current flows in the diode is applied to the non-selected cell, almost no voltage will be applied to the ferroelectric capacitor, so in the simple matrix ferroelectric memory, the non-selected cell is selected. The disturbance of can be avoided.

In the method of operating the above ferroelectric memory,
Preferably, when the ON voltage and the breakdown voltage of the diode are Vt and Vb, respectively, the standby voltage of the bit line and the word line is (Vt + Vb) <
Standby voltage <0. According to this structure, the standby voltage is closer to the center of the hysteresis characteristic of the memory cell composed of the ferroelectric capacitor and the diode, as compared with the case where the standby voltage is 0V, so that the standby voltage is set to 0V. Compared with the case, it is possible to increase the resistance to noise when writing or reading is not performed. In this case, set the standby voltage to (V
It is preferably set to t + Vb) / 2. With this configuration, it is possible to further enhance resistance to noise when writing or reading is not performed.

In the method of operating the above ferroelectric memory,
Preferably, a predetermined pulse width that causes polarization reversal when a high voltage is applied to the ferroelectric capacitor and substantially does not occur when a low voltage is applied to the ferroelectric capacitor. A pulse applying unit for applying the pulse having the pulse to the memory cell, wherein a high voltage pulse having a predetermined pulse width is applied to the selected memory cell during at least one of data writing and reading. And a low voltage pulse having a predetermined pulse width is applied to the non-selected memory cells. According to this structure, writing or reading can be performed with respect to the selected memory cell, and almost no polarization inversion can occur with respect to the non-selected memory cell. As a result, it is possible to further improve the disturbance resistance in the non-selected memory cells.

[0029]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of the present invention will be described below with reference to the drawings.

(First Embodiment) FIG. 1 is a circuit diagram showing the entire structure of a simple matrix type ferroelectric memory according to the first embodiment of the present invention. FIG. 2 is a schematic diagram for explaining the configuration of the memory cell of the ferroelectric memory according to the first embodiment shown in FIG.

First, with reference to FIGS. 1 and 2, the overall structure of the simple matrix ferroelectric memory of the first embodiment will be described. In the ferroelectric memory according to the first embodiment, the memory cell array 50 is configured by arranging a plurality of memory cells 1 in a matrix shape (in FIG. 1, only 9 memory cells are shown for convenience of description. ing). One terminal of the ferroelectric capacitor 2 forming each memory cell 1 is connected to the bit lines BL _{0 to} BL ₂ ,
The other terminal of the ferroelectric capacitor 2 is connected to one terminal of the diode 3. The other terminal of the diode 3 is connected to the word lines WL _{0 to} WL ₂ . That is, in the first embodiment, the memory cell 1 is composed of the ferroelectric capacitor 2 and one diode 3 connected in series to the ferroelectric capacitor 2. In addition,
Details of the diode 3 will be described later.

The word lines WL _{0 to} WL ₂ are connected to the row decoder 31. In addition, each bit line BL _{0 to} BL ₂
Are connected to the column decoder 32.

The row address and the column address designated from the outside are input to the address pin 33. The row address and the column address are the address pin 3
3 to the address latch 34. Of the addresses latched by the address latch 34, the row address is transferred to the row decoder 31 via the address buffer 35, and the column address is transferred to the column decoder 32 via the address buffer 35.

The row decoder 31 includes word lines WL ₀ to WL ₀ .
A word line corresponding to the row address latched by the address latch 34 is selected from WL ₂ , and the potential of each word line is controlled in accordance with the operation mode.

The column decoder 32 has each bit line BL _0.
Of to BL _2, selects a bit line corresponding to the latched column address in the address latch 34, corresponding to control of the operation mode the potential of each bit line.

Further, the row decoder 31 and the column decoder 32 respectively apply a pulse application circuit 41 and a pulse application circuit 42 for applying voltage pulses to the word lines WL _{0 to} WL ₂ and the bit lines BL _{0 to} BL ₂ , respectively. Is included.

Data designated externally is input to the data pin 36. The data is transferred from the data pin 36 to the column decoder 32 via the input buffer 37. The column decoder 32 includes bit lines BL _{0 to} BL ₂
The potential of is controlled to the potential corresponding to the data.

The data read from an arbitrary memory cell 1 is transferred from each bit line BL _{0 to} BL ₂ to the column decoder 32.
Is transferred to the sense amplifier 38 via. The sense amplifier 38 is a voltage sense amplifier. The data determined by the sense amplifier 38 is transferred from the output buffer 39 to the data pin 3
It is output to the outside via 6.

The above-mentioned circuits (31-39, 4)
The operations 1, 42) are controlled by the control core circuit 40.

Here, the memory cell 1 of the first embodiment
As shown in FIG. 2, the diode 3 constituting the device has a positive ON voltage Vt and a negative breakdown voltage Vb whose absolute value is larger than the ON voltage Vt. This memory cell 1
The amount Q of electric charge with respect to the applied voltage V at both ends of is as shown in FIG. In this case, most of the applied voltage is applied to the diode at the voltage V satisfying Vb ≦ V ≦ Vt centering on the voltage (Vt + Vb) / 2. That is, at the voltage V in the above range, almost no current flows through the diode 3, so that the resistance of the diode 3 becomes almost infinite. Therefore, most of the applied voltage is applied to the diode 3 and almost no voltage is applied to the ferroelectric capacitor 2.

Referring to FIG. 3, in the first embodiment, (V
t−Vb) / 2 ≧ 1/2 Vcc is satisfied, and when the standby voltage during standby is (Vt + Vb) / 2, the power supply voltage Vcc is set to (Vt + Vb) / 2 + Vcc, which is a voltage sufficient for polarization reversal. To set. in this case,
(Vt-Vb) / 2 ≧ 1 / 2Vcc is the memory cell 1
Shows the condition of the power supply voltage Vcc at which almost no current flows through the diode 3 when (Vt + Vb) / 2 ± 1 / 2Vcc is applied.

FIG. 4 is a circuit diagram for explaining the voltage application method of the ferroelectric memory according to the first embodiment of the present invention. Referring to FIG. 4, in the first embodiment, in the selected cell,
(Vt + Vb) / 2 + Vcc or (Vt + Vb) / 2
A voltage pulse of −Vcc is applied and a voltage pulse of (Vt + Vb) / 2 ± 1 / 2Vcc is applied to the non-selected cells. (Vt + Vb) / applied to this selected cell
2 + Vcc and (Vt + Vb) / 2-Vcc are 0V
Centered at is an asymmetric voltage pulse. In addition, (Vt + Vb) / 2 + 1 / 2Vc applied to the non-selected cells
c and (Vt + Vb) / 2-1 / 2Vcc are also asymmetric voltage pulses centered at 0V. By applying such an asymmetric voltage pulse, data writing or reading can be performed by polarization inversion in the selected cell, and almost no voltage is applied to the ferroelectric capacitor 2 of the non-selected cell. As a result, it is possible to avoid the disturb in the non-selected cells.

In the first embodiment described above, the standby voltage, which is the voltage applied to each cell during standby, is (V
t + Vb) / 2, a voltage obtained by adding ± Vcc to the standby voltage is applied to the selected cell, and a voltage obtained by adding ± 1/2 Vcc to the standby voltage is applied to the non-selected cells. As a result, when reading or writing is not performed, (Vt-V
Even if the voltage fluctuates up to b) / 2, almost no current flows through the diode 3, so that almost no voltage is applied to the ferroelectric capacitor 2. As a result, noise immunity can be improved as compared with the case where the standby voltage is set to 0V.

In the first embodiment, as described above, by providing the memory cell 1 including the ferroelectric capacitor 2 and one diode 3 connected in series with the ferroelectric capacitor 2, the diode 3 is provided in the memory cell 1. In the voltage range in which almost no current flows, the resistance of the diode 3 becomes almost infinite, so most of the voltage is applied to the diode 3 and almost no voltage is applied to the ferroelectric capacitor 2. Therefore, when writing or reading data, if the above voltage in the range in which almost no current flows through the diode 3 is applied to the non-selected cell, almost no voltage is applied to the ferroelectric capacitor 2, so that the simple matrix ferroelectric It is possible to avoid disturbance of unselected cells in the body memory. As a result, it is possible to put a simple matrix type ferroelectric memory into practical use.

FIG. 5 is a circuit diagram for explaining the voltage application method of the ferroelectric memory according to the modification of the first embodiment of the present invention. Referring to FIG. 5, in the modified example of the first embodiment, (Vt−Vb) / 2 ≧ 1 / 3Vcc is satisfied,
Further, the power supply voltage Vcc is set so that the polarization voltage is sufficiently inverted at (Vt + Vb) / 2 + Vcc when the standby voltage during standby is (Vt + Vb) / 2. In this case, (Vt-Vb) / 2 ≧ 1 / 3Vcc is the power supply voltage Vcc at which almost no current flows through the diode 3 when (Vt + Vb) / 2 ± 1 / 3Vcc is applied to the memory cell 1. The conditions are shown.

In the modification of the first embodiment, as shown in FIG.
As shown in, the selected cell has (Vt + Vb) / 2 + Vc
A voltage pulse of c or (Vt + Vb) / 2-Vcc is applied and (Vt + Vb) / 2 ± is applied to the non-selected cells.
A voltage pulse of 1/3 Vcc is applied. (Vt + Vb) / 2 + Vcc and (Vt +) applied to this selected cell
Vb) / 2-Vcc is an asymmetric voltage pulse centered at 0V. In addition, it is applied to the non-selected cells (V
t + Vb) / 2 + 1 / 3Vcc and (Vt + Vb) /
2-1 / 3 Vcc is also an asymmetric voltage pulse centered at 0V. By applying such an asymmetric voltage pulse, data writing or reading can be performed by polarization inversion in the selected cell, and almost no voltage is applied to the ferroelectric capacitor 2 of the non-selected cell. As a result, it is possible to avoid the disturb in the non-selected cells.

In the modification of the first embodiment described above, as in the first embodiment, the standby voltage during standby is set to (Vt + Vb) / 2, and the selected cell has a standby voltage of ± Vcc and a non-selected value. It is sufficient to apply ± 1/3 Vcc as the standby voltage to the selected cell.

(Second Embodiment) In the second embodiment,
A method of suppressing the disturbance of the non-selected cell even when a voltage such that a current flows through the diode 3 is applied to the non-selected cell will be described.

That is, in the first embodiment, the voltage V which satisfies Vb ≦ V ≦ Vt is applied to the non-selected cell with the standby voltage (Vt + Vb) / 2 as the center, whereby the diode 3 of the non-selected cell is applied. Since almost no current flows through the diode 3, most of the applied voltage is applied to the diode 3. On the other hand, in the second embodiment, (Vt-V
b) / 2 <1/2 Vcc is satisfied, and (Vt + V
b) A method of suppressing the disturb even when the power supply voltage Vcc is set so that the polarization is sufficiently inverted at / 2 + Vcc will be described. In this case (V
t-Vb) / 2 <1 / 2Vcc is stored in the memory cell 1
When (Vt + Vb) / 2 ± 1 / 2Vcc is applied,
The condition of the power supply voltage Vcc at which a current flows through the diode 3 is shown.

With the power supply voltage Vcc of the second embodiment set as described above, as shown in FIG. 4, (Vt + Vb) / 2 ± Vcc is applied to the selected cell and (V is applied to the non-selected cell).
A voltage pulse of t + Vb) / 2 ± 1/2 Vcc is applied. In this case, in the ferroelectric capacitor 2 of the selected cell,
(Vb-Vt) / 2 + Vcc or (Vt-Vb) / 2
A voltage of −Vcc is applied. Also, in non-selected cells,
Unlike the first embodiment, since a current flows through the diode 3, the ferroelectric capacitor 2 of the non-selected cell has (Vb−
Vt) / 2 + 1 / 2Vcc or (Vt-Vb) / 2-
A voltage of 1/2 Vcc is applied.

FIG. 6 shows SrBi ₂ Ta ₂ as a ferroelectric layer.
FIG. 7 is a diagram showing a relationship between a pulse width and a polarization inversion charge amount when a pulse is applied to a ferroelectric capacitor using an O ₉ (SBT) film. As is apparent from FIG. 6, when the pulse width is 70 nsec or less, when the applied voltage is high (for example, 1.6 V or more), the polarization inversion charge amount is almost saturated and becomes 1 or less.
The charge amount is ⁴ μC / cm ^{2 to} 15 μC / cm ² . On the other hand, when the pulse width is 70 nsec or less and the applied voltage is low (for example, 0.6 V or less), polarization inversion hardly occurs. As described above, when the pulse width is relatively short, polarization inversion occurs in the ferroelectric layer at high voltage, whereas polarization inversion hardly occurs at low voltage.

In the second embodiment, the ferroelectric capacitor 2 of the memory cell 1 is provided with (Vb-
Vt) / 2 + Vcc or (Vt-Vb) / 2-Vcc
When a high voltage is applied, a sufficient polarization reversal occurs and (Vb-Vt) / 2 + 1 / 2Vcc or (Vt-
When a voltage as low as Vb) / 2-1 / 2 Vcc is applied, a pulse having a pulse width that hardly causes polarization inversion is applied to the memory cell 1. This allows
Even when a voltage such that a current flows through the diode 3 is applied to the non-selected cell, the disturbance of the non-selected cell can be suppressed.

The above pulse may be applied by using the pulse applying circuits 41 and 42 shown in FIG. The pulse applying circuits 41 and 42 in this case are examples of the “pulse applying means” in the present invention.

Further, the power supply voltage V of the second embodiment described above.
In cc, as a modified example of the second embodiment, as shown in FIG. 5, the selected cell has (Vt + Vb) / 2 ± Vc.
c, (Vt + Vb) / 2 ± 1 / 3Vcc in non-selected cells
May be applied. In this case, the ferroelectric capacitor 2 of the selected cell has (Vb-Vt) / 2 + Vc
A voltage of c or (Vt-Vb) / 2-Vcc is applied. Further, in the ferroelectric capacitor 2 of the non-selected cell,
(Vb-Vt) / 2 + 1 / 3Vcc or (Vt-V
b) A voltage of / 2-1 / 3 Vcc is applied. This second
Also in the modification of the embodiment, the ferroelectric capacitor 2 of the memory cell 1 has (Vb−Vt) / 2 + Vcc or (Vb−Vt) / 2 + Vcc.
When a high voltage of about t-Vb) / 2-Vcc is applied, sufficient polarization inversion occurs and (Vb-Vt) / 2 + 1 /
When a voltage as low as 3 Vcc or (Vt-Vb) / 2-1 / 3 Vcc is applied, a pulse having a pulse width that hardly causes polarization inversion is applied to the memory cell 1. As a result, even when a voltage that causes a current to flow through the diode 3 is applied to the non-selected cell, the disturb of the non-selected cell can be suppressed.

(Third Embodiment) FIG. 7 is a sectional view showing the structure of a memory cell of a ferroelectric memory according to a third embodiment of the present invention, and FIG. 8 is a third embodiment shown in FIG. FIG. 6 is a cross-sectional view of the structure of the memory cell according to the embodiment as viewed from the direction rotated by 90 °.

Referring to FIGS. 7 and 8, in the third embodiment, p formed on the silicon substrate is used as diode 3 connected to ferroelectric capacitor 2 forming memory cell 1 (see FIG. 1). -Use an n-junction diode. Specifically, as shown in FIG. 7, an STI (Shallow Trench) is formed in a predetermined region on the surface of the silicon substrate 61.
The element isolation film 62 is formed by the isolation method. An n-type region 63 is formed on the surface of the silicon substrate 61 located between the element isolation films 62. n
A p-type region 64 is formed in the mold region 63. The p-type region 64 and the n-type region 63 form a pn junction diode according to the third embodiment.

Further, the interlayer insulating film 65 is formed so as to cover the entire surface.
Are formed. A plug electrode 66 is formed in the contact hole 65 a of the interlayer insulating film 65 so as to be electrically connected to the p-type region 64. A lower electrode 67 is formed on the plug electrode 66. In addition, the lower electrode 6
An upper electrode 69 is formed on the substrate 7 via a ferroelectric layer 68 made of an SBT film or the like. This lower electrode 67
The ferroelectric layer 68 and the upper electrode 69 constitute the ferroelectric capacitor according to the third embodiment.

In the third embodiment, the cell size can be reduced by forming the pn junction diode on the silicon substrate 61 as described above, and at the same time,
It is possible to form a diode whose characteristics are not deteriorated even by annealing (heat treatment) at 600 ° C. or more for crystallization of the ferroelectric layer 68.

FIG. 9 is a sectional view showing the structure of the diode portion of the memory cell according to the modification of the third embodiment shown in FIGS. 7 and 8. In the modification of the third embodiment, as shown in FIG. 9, two electrodes 71 and 72,
P-type semiconductor thin film 73 disposed between electrodes 71 and 72
And the n-type semiconductor thin film 74 form a pn junction diode. In this case, the p-type semiconductor thin film 73
The n-type semiconductor thin film 74 is formed using an amorphous semiconductor layer or a polycrystalline semiconductor layer. In particular, since the amorphous semiconductor layer has no crystal grain boundary, the diode characteristics can be made uniform even if a fine structure is manufactured. As the amorphous semiconductor layer, for example, amorphous silicon is used.

(Fourth Embodiment) FIG. 10 shows a fourth embodiment of the present invention.
FIG. 11 is a sectional view showing a structure of a memory cell of the ferroelectric memory according to the embodiment, and FIG. 11 is a sectional view of the structure of the memory cell according to the fourth embodiment shown in FIG. .

Referring to FIGS. 10 and 11, this fourth
In the embodiment, a Schottky diode formed on the silicon substrate 81 is used as the diode 3 connected to the ferroelectric capacitor 2 that constitutes the memory cell 1 (see FIG. 1). Specifically, as shown in FIG. 10, the element isolation film 82 formed by the STI method is formed in a predetermined region on the silicon substrate 81.
Are formed. An n ⁺ type region 83 is formed on the surface of the silicon substrate 81 located between the element isolation films 82. An n-type region 84 is formed in the n ⁺ -type region 83. A conductive layer 86 is formed on the n-type region 84. A Schottky barrier is formed at the interface between n-type region 84 and conductive layer 86. As a result, the n-type region 84 and the conductive layer 86 form the Schottky diode according to the fourth embodiment. The n ⁺ type region 83 and the n type region 84 shown in FIGS.
A Schottky diode may be formed by changing to the p ⁺ type region and the p type region.

An interlayer insulating film 85 is formed so as to cover the conductive layer 86 and the element isolation film 82. A plug electrode 87 is formed in the contact hole 85 a of the interlayer insulating film 85 so as to be connected to the conductive layer 86. A lower electrode 88 is formed on the plug electrode 87.
An upper electrode 90 is formed on the lower electrode 88 via a ferroelectric layer 89 made of an SBT film or the like. The lower electrode 88, the ferroelectric layer 89, and the upper electrode 90 form the ferroelectric capacitor according to the fourth embodiment.

In the fourth embodiment, as shown in FIGS. 10 and 11, the cell size can be reduced by forming the Schottky diode on the silicon substrate 81.

FIG. 12 is a sectional view showing a diode portion of a memory cell according to a modification of the fourth embodiment shown in FIGS. 10 and 11. In the modification of the fourth embodiment, as shown in FIG. 12, an n-type or p-type semiconductor layer 93 is formed.
And a conductive layer 92 are used to form a Schottky diode. Conductive layer 9 of n-type or p-type semiconductor layer 93
An electrode 94 is formed on the surface opposite to 2.
In this case, the n-type or p-type semiconductor layer 93 is formed using a polycrystalline semiconductor layer or an amorphous semiconductor layer. In particular,
Since the amorphous semiconductor layer has no crystal grain boundary, the diode characteristics can be made uniform even if a fine structure is manufactured. As the amorphous semiconductor layer, amorphous S
i or the like is used.

Further, the Schottky diode is required to have thermal stability so as not to exhibit ohmic characteristics due to mutual diffusion at the interface between the conductive layer and the semiconductor layer in the semiconductor element manufacturing process. 13 and 14
Are IrSi / polySi samples and Ir, respectively.
It is the figure which showed the profile in the depth direction of each composition after heat-processing at 800 degreeC with respect to a SiN / poly Si sample.

As is clear from FIGS. 13 and 14,
IrSi / polySi even after high-temperature treatment at 800 ° C.
No significant interdiffusion was observed at the interface and the IrSiN / polySi interface, and the conductive layer was IrSi or Ir.
It can be seen that the bond between SiN and poly-Si, which is the semiconductor layer, is thermally stable. It should be noted that such a thermally stable bond is formed by Ir, Pt, Ru, Re, Ni, Co and M.
Conductive material containing at least one of o and silicon, or Ir, Pt, Ru, Re, Ni, Co
And at least one of Mo and silicon,
It can also be obtained by a conductive material containing nitrogen.

It should be understood that the embodiments disclosed this time are illustrative and non-restrictive in all respects. The scope of the present invention is shown not by the above description of the embodiments but by the scope of claims for patent, and further includes meanings equivalent to the scope of claims for patent and all modifications within the scope.

For example, in the second to fourth embodiments described above,
The case where the SBT film is used as the ferroelectric layer will be described.
However, the present invention is not limited to this, and SrBi₂(Nb, T
a)₂O ₉(SBNT), Pb (Zr, Ti) O₃(PZ
T), (Pb, La) (Zr, Ti) O₃(PLZ
T), (Bi, La)_FourTi₃O₁₂(BLT), Bi_FourT
i₃O₁₂(BIT) or equivalent ferroelectric layer is used
Can be In particular, as shown in FIG.
When a high voltage is applied to the body layer, it produces sufficient polarization reversal.
And when a low voltage is applied, almost all
A polarization inversion feature with a pulse width that does not cause pole inversion.
Any ferroelectric layer having properties can be used.

In the above embodiment, the standby voltage, which is the voltage applied to each cell during standby, is (Vt + V
However, the present invention is not limited to this, and the standby voltage may be in the range of (Vt + Vb) <standby voltage <0. According to this structure, the standby voltage is closer to the center of the hysteresis characteristic of the ferroelectric capacitor as compared with the case where the standby voltage is set to 0V, so that writing or reading is performed compared to the case where the standby voltage is set to 0V. The resistance to noise when not in use can be increased. However, the standby voltage is (Vt
Most preferably, it is set to + Vb) / 2.

[0070]

As described above, according to the present invention, it is possible to provide a ferroelectric memory capable of improving the disturbance resistance in unselected memory cells.

[Brief description of drawings]

FIG. 1 is a circuit diagram showing an overall configuration of a ferroelectric memory according to a first embodiment of the present invention.

FIG. 2 is a schematic diagram for explaining a configuration of a memory cell of the ferroelectric memory according to the first embodiment shown in FIG.

FIG. 3 is a diagram for explaining the effect of the ferroelectric memory according to the first embodiment of the present invention.

FIG. 4 is a circuit diagram illustrating a voltage application method of the ferroelectric memory according to the first embodiment of the present invention.

FIG. 5 is a circuit diagram for explaining a voltage application method of a ferroelectric memory according to a modified example of the first embodiment of the present invention.

FIG. 6 is a diagram showing pulse response characteristics relating to the amount of polarization reversal of a ferroelectric layer.

FIG. 7 is a sectional view showing a structure of a memory cell of a ferroelectric memory according to a third embodiment of the present invention.

FIG. 8 is a cross-sectional view of the structure of the memory cell according to the third embodiment shown in FIG. 7, as seen from the direction rotated by 90 °.

9 is a sectional view showing a structure of a diode portion of a memory cell according to a modification of the third embodiment shown in FIGS. 7 and 8. FIG.

FIG. 10 is a sectional view showing the structure of a memory cell of a ferroelectric memory according to a fourth embodiment of the present invention.

FIG. 11 is a cross-sectional view of the structure of the memory cell according to the fourth embodiment shown in FIG. 10, as seen from the direction rotated by 90 °.

FIG. 12 is a cross-sectional view showing a diode portion of a memory cell according to a modification of the fourth embodiment shown in FIGS. 10 and 11.

FIG. 13 is a correlation diagram for explaining thermal stability of the Schottky diode according to the fourth embodiment of the present invention.

FIG. 14 is a correlation diagram for explaining thermal stability of the Schottky diode according to the fourth embodiment of the present invention.

FIG. 15 is a typical circuit diagram of a conventional and most commonly used ferroelectric memory.

16 is a sectional structural view corresponding to the circuit diagram shown in FIG.

FIG. 17 is a circuit diagram showing a circuit configuration of a memory cell array of a conventional simple matrix ferroelectric memory.

FIG. 18 is a sectional structural view of the conventional simple matrix type ferroelectric memory shown in FIG.

FIG. 19 is a circuit diagram for explaining a voltage application state at the time of a write operation by the 1/2 Vcc method of the conventional simple matrix type ferroelectric memory shown in FIGS. 17 and 18.

20 is a circuit diagram for explaining a voltage application state during a write operation by the 1/3 Vcc method of the conventional simple matrix type ferroelectric memory shown in FIGS. 17 and 18. FIG.

FIG. 21 is a diagram showing ferroelectric hysteresis characteristics for explaining the problems of the conventional simple matrix type ferroelectric memory.

[Explanation of symbols]

1 memory cell 2 Ferroelectric capacitor 3 diode 41, 42 pulse applying circuit (pulse applying means) 50 memory cell array

Claims (7)

[Claims] 1. A bit line, a word line arranged to intersect the bit line, a word line arranged between the bit line and the word line, and connected in series to the ferroelectric capacitor and the ferroelectric capacitor. A ferroelectric memory having a memory cell including a diode connected to the. 2. When the ON voltage and the breakdown voltage of the diode are Vt and Vb, respectively, the standby voltage of the bit line and the word line is (V
The ferroelectric memory according to claim 1, wherein t + Vb) <standby voltage <0. 3. The ferroelectric memory according to claim 1, wherein at least one of writing and reading of data is performed by applying an asymmetric voltage pulse to the bit line and the word line. 4. A predetermined value which causes polarization reversal when a high voltage is applied to the ferroelectric capacitor and substantially does not occur when a low voltage is applied to the ferroelectric capacitor. Pulse applying means for applying a pulse having a pulse width of 1 to the memory cell, and the predetermined pulse width is applied to the selected memory cell during at least one of data writing and reading. 4. The ferroelectric substance according to claim 1, wherein a high voltage pulse having a low voltage pulse having a predetermined pulse width is applied to a non-selected memory cell. memory. 5. The ferroelectric memory according to claim 1, wherein the diode includes a pn junction diode formed by joining a p-type semiconductor layer and an n-type semiconductor layer. . 6. The p-type diode is formed by a junction of a p-type region and an n-type region formed in a semiconductor substrate.
5. A n-junction diode is included in any one of Claims 1-4.
2. A ferroelectric memory according to item. 7. The ferroelectric memory according to claim 1, wherein the diode includes a Schottky diode formed by joining a conductive layer and a semiconductor layer.