TWI256554B - Control chip with multi-function bus and control chip set thereof - Google Patents

Control chip with multi-function bus and control chip set thereof

Info

Publication number
TWI256554B
TWI256554B TW092117231A TW92117231A TWI256554B TW I256554 B TWI256554 B TW I256554B TW 092117231 A TW092117231 A TW 092117231A TW 92117231 A TW92117231 A TW 92117231A TW I256554 B TWI256554 B TW I256554B
Authority
TW
Taiwan
Prior art keywords
control chip
bus
function bus
function
pins
Prior art date
Application number
TW092117231A
Other languages
English (en)
Other versions
TW200500867A (en
Inventor
Chia-Hsing Yu
Chi-Hsin Lin
Original Assignee
Via Tech Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Via Tech Inc filed Critical Via Tech Inc
Priority to TW092117231A priority Critical patent/TWI256554B/zh
Priority to US10/710,041 priority patent/US7032060B2/en
Publication of TW200500867A publication Critical patent/TW200500867A/zh
Application granted granted Critical
Publication of TWI256554B publication Critical patent/TWI256554B/zh

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/40—Bus structure
    • G06F13/4004—Coupling between buses
    • G06F13/4009—Coupling between buses with data restructuring
    • G06F13/4018—Coupling between buses with data restructuring with data-width conversion

Landscapes

  • Engineering & Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Microcomputers (AREA)
  • Bus Control (AREA)
TW092117231A 2003-06-25 2003-06-25 Control chip with multi-function bus and control chip set thereof TWI256554B (en)

Priority Applications (2)

Application Number Priority Date Filing Date Title
TW092117231A TWI256554B (en) 2003-06-25 2003-06-25 Control chip with multi-function bus and control chip set thereof
US10/710,041 US7032060B2 (en) 2003-06-25 2004-06-15 Control chip supporting plurality of buses and control chip set thereof

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
TW092117231A TWI256554B (en) 2003-06-25 2003-06-25 Control chip with multi-function bus and control chip set thereof

Publications (2)

Publication Number Publication Date
TW200500867A TW200500867A (en) 2005-01-01
TWI256554B true TWI256554B (en) 2006-06-11

Family

ID=33538485

Family Applications (1)

Application Number Title Priority Date Filing Date
TW092117231A TWI256554B (en) 2003-06-25 2003-06-25 Control chip with multi-function bus and control chip set thereof

Country Status (2)

Country Link
US (1) US7032060B2 (zh)
TW (1) TWI256554B (zh)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7805560B2 (en) * 2005-08-31 2010-09-28 Ati Technologies Inc. Methods and apparatus for translating messages in a computing system
US7698493B2 (en) * 2005-08-31 2010-04-13 Ati Technologies, Inc. Methods and apparatus for translating write request messages in a computing system
US20070233930A1 (en) * 2006-03-14 2007-10-04 International Business Machines Corporation System and method of resizing PCI Express bus widths on-demand

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5781746A (en) * 1990-07-20 1998-07-14 Siemens Aktiengesellschaft Microprocessor with multiple bus configurations
US6148357A (en) * 1998-06-17 2000-11-14 Advanced Micro Devices, Inc. Integrated CPU and memory controller utilizing a communication link having isochronous and asynchronous priority modes
US6775282B1 (en) * 1999-12-27 2004-08-10 Intel Corporation Bus communication
US6658520B1 (en) * 2000-09-26 2003-12-02 Intel Corporation Method and system for keeping two independent busses coherent following a direct memory access
US6886066B2 (en) * 2001-10-11 2005-04-26 International Business Machines Corporation Method and apparatus for sharing signal pins on an interface between a system controller and peripheral integrated circuits

Also Published As

Publication number Publication date
US20040268014A1 (en) 2004-12-30
TW200500867A (en) 2005-01-01
US7032060B2 (en) 2006-04-18

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Legal Events

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MK4A Expiration of patent term of an invention patent