、1253649 玖、發明說明 (發明說明應敘明：發明所屬之技術領域、先前技術、內容、實施方式及圖式簡單說明） 【發明所屬之技術領域】 本發明係關於一種平面記憶體單元(FLAT CELL)，尤其 是關於一種讀取平面記憶體單元(FLAT CELL)的電路。 【先前技術】 在記憶體選擇電路中，如何利用簡易的製程及快速的讀 取資料及降低選擇電路讀取資料時的電阻一直扮演一個很 重要的角色，然而在目前的環境下，讀取電路時的所造成的 電阻及電容效應是無法避免的，因此如何更有效率的降低電 阻及電容效應並進而提升系統的效能是所有硏發人員一直 努力的目標。 呂定洲(Ding-Jou Lu)等人之美國專利第6084794號之文 獻：HIGy SPEED FLAT-CELL MASK ROM STRUCTURE WITH SELECT LINES，係藉由同時短路欲選取讀取資料旁兩側之電 晶體’而達到讀取資料效果，如圖一所示，外界系統如欲讀 取電晶體11資料，必須先將兩側之電晶體10與電晶體12 先短路後方才能讀出電晶體U的資料，此種讀取記憶體內 資料的方式控制電路複雜，並由於讀取資料時需將兩側的電 晶體短路’因且易產生寄生電容效應造成雜訊的干擾及其他 因素等導致系統不正常運作。 π進一步解決以上問題，另一昔知技術如圖二所示，當 U、/人頁（發明說明頁不敷使用時，請註記並使用續頁） 7 1253649 讀取該技術之電晶體20,藉由設定第一模擬接地端(VG(0))35 爲邏輯”1”、位元選擇線(BL(0))34爲邏輯”1”、第一選擇線 (SL(0))31爲邏輯”1”、第二選擇線(SL(1))32爲邏輯”0”、第二 模擬接地端(VG(1))36爲邏輯”0”，使電晶體20構成一讀取迴 路，使外部可以正確的讀取電晶體20內的資料，改善了美 國專利第6084794號短路的做法，並且減少電容效應，但卻 無法解決在讀取電晶體記憶體內的資料爲邏輯，，〇，，時由於位 元選擇線（BL(0))所產生之電流造成電路元件間彼此之干 擾，使得讀取速度無法提升，但隨著科技的進步，人們對於 記憶體的要求快速及正確的讀取資料的要求越來越高，因此 光解決選擇電路選取記憶體時的短路所造成之電容效應是 不夠的，如何有效的降低讀取資料的電阻及電容效應以提升 記憶體模組效能亦是所有硏發人員長期努力的目標。 因此本發明提供一關於降低讀取記憶體單元資料的電 阻及降低干擾的選擇電路，提供較多的讀取迴路，來降低系 統電阻及電容效應，並進而提升效能。 【發明內容】 本發明之主要目的係提供一種二進二出讀取路徑之高 速平面記憶體單元結構，藉由兩條路徑選擇所需之電晶體記 憶體單元及兩條路徑由輸出電晶體記憶體，以達到讀取記憶 體內容的目的。 本發明之另一目的係提供一種選擇記憶體電路’藉以降 ϋ續次頁（發明說明頁不敷使用時，請註記並使用續頁） 8 ,1253649 低讀取記憶體內容時的電容及電阻效應。 本發明提供一種具二進二出讀取路徑之高速平面記憶 體單元之選擇電路，本發明至少包括：一第一選擇線 (SL(0))31、一第二選擇線(SL⑴)32、一記憶體陣列33、一位 元選擇線(BL(0))34、一第一模擬接地端(VG(0))35、一第二模 擬接地端(VG(1))36、一字元選擇線37、一第一開關電晶體 301、一第二開關電晶體302、一第三開關電晶體303、一第 四開關電晶體304、一第五開關電晶體305、一第六開關電晶 體306、一第七開關電晶體307、一第八開關電晶體308、一 第九開關電晶體309 —第十開關電晶體310、第十一開關電 晶體311第十二開關電晶體312、第十三開關電晶體313及 第十四開關電晶體314 ;藉由控制各個開關電晶體以達成讀 取記憶體陣列33內之資料的目的，另，本發明亦可達成兩 條路徑選擇電晶體記憶體單元及兩條路徑由電晶體記憶體 單元輸出的效果’降低外界讀取本發明之電阻値。 【實施方式】 有關本發明爲達成上述之目的，所採用之技術、手段及 具體結構特徵’兹舉一較佳可行之實施例，並藉由圖示說明 而更進一步揭示明瞭，詳如下述。 請參考圖三之架構示意圖，本發明提供一種二進二出讀 取路徑之高速平面記憶體單元結構，可藉由兩條輸入路徑及 二條輸出路徑選擇所對應之電晶體記憶體單元，以達到讀取 □續次頁（發日月說日月胃+敷’言靑|£言己) 9 1253649 記億體資料的目的，該結構至少包括:一第一選擇線31、一 第二選擇線32、一記憶體陣列33、一位元選擇線34、一第 一模擬接地端35、一第二模擬接地端36、一字元選擇線37、 一第一開關電晶體301、一第二開關電晶體302、一第三開關 電晶體303、一第四開關電晶體304、一第五開關電晶體305、 一第六開關電晶體306、一第七開關電晶體307、一第八開關 電晶體308、一第九開關電晶體309、一第十開關電晶體310、 第十一開關電晶體311第十二開關電晶體312、第十三開關 電晶體313及第十四開關電晶體314 ;其中該字元選擇線37 係用以連接該記憶體陣列33內電晶體之閘極；其中該第一 選擇線31係連接至該第三開關電晶體303、第四開關電晶體 304、第五開關電晶體305、第六開關電晶體306、第八開關 電晶體308、第九開關電晶體309、第十三開關電晶體313及 第十四開關電晶體314之閘極；其中該第二選擇線32係連接 至該第一開關電晶體301、第二開關電晶體302、第七開關電 晶體307、第十開關電晶體310、第十一開關電晶體311及第 十二開關電晶體312之閘極；該第一開關電晶體301及第三 開關電晶體303、第八開關電晶體308及第十開關電晶體310 係控制該第一模擬接地端35與記憶體陣列33之導通；該第 四開關電晶體304、第五開關電晶體305、第七開關電晶體 307、第十一開關電晶體311、第十三開關電晶體313及第十 四開關電晶體314係控制該位元選擇線34與記憶體陣列33 之導通；該第二開關電晶體302、第六開關電晶體306、第九 □續次頁（發明說明頁不敷使用時，請註記並使用續頁） 1253649 開關電晶體309及第十二開關電晶體312係控制該第二模擬 接地端36與記憶體陣列33之導通；其經由控制該第一選擇 線31、第二選擇線32、位元選擇線34、第一模擬接地端35 及第二模擬接地端36係使外界讀取該記憶陣內資料產生二 進二出讀取電流路徑，藉以形成讀取迴路。 換句話說，以讀取電晶體記憶體單元331爲例，當第一 選擇線31爲邏輯”1”、第二選擇線32爲邏輯”0”、位元選擇 線34爲邏輯”1”、第一模擬接地端35爲邏輯”1”及第二模擬 接地端36爲邏輯”0”使得第一開關電晶體301爲截止狀態、 第二開關電晶體302爲截止狀態、第三開關電晶體303爲導 通狀態、第四開關電晶體304爲導通狀態、第五開關電晶體 305爲導通狀態、第六開關電晶體306爲導通截止狀態、第 七開關電晶體307爲截止狀態、第八開關電晶體308爲導通 狀態、第九開關電晶體309爲導通狀態第十開關電晶體310 爲截止狀態、第十一開關電晶體311爲截止狀態、第十二開 關電晶體312爲截止狀態、第十三開關電晶體313爲導通狀 態及第十四開關電晶體314爲導通狀態；其中第四開關電晶 體304爲導通狀態，使得位元選擇線34與電晶體331構成一 輸入路徑，且由於第三開關電晶體303爲導通狀態，使得電 晶體331內可藉由第三開關電晶體303及第一模擬接地端35 所形成一輸出路徑，另藉由第十三開關303的導通係使位元 選擇線34與電晶體331產生第二條的輸入入徑，並且由於第 八開關電晶體308爲導通狀悲係使第一*模擬接地端35與電晶 [□續次頁（發明說明頁不敷使用時，請註記並使用續頁） 11 1253649 體331產生第二條的輸出入徑，藉此達到兩條路徑選擇電晶 體記憶體單元，兩條路徑由電晶體記憶體單元輸出的效果， 並於gfi憶單兀被選取時構成迴路，由於輸入路徑有兩條與輸 出路徑有兩條係使輸入與輸出同時構成並聯效果，進一步降 低本發明於被讀取時之電阻値，使得外界電路本發明時的電 阻及電容效應降低，所造成的效果不只是達到降低雜訊、減 少耗能、提高頻率響應更能降低外界運用本發明時整體系統 運作時之溫度。 由以上得之，本發明之選擇記憶體電路可產生兩條路徑 選擇電晶體記憶體單元及兩條路徑由電晶體記憶體單元輸 出的效果，其中本發明之電晶體係可藉由互補金屬氧化半導 體（Complementary Metal-Oxide Semiconductor，CM〇S)製程技 術或砂覆絕緣（Silicon On Insulator，SOI)製程技術所完成， 且該第一開關電晶體301、第二開關電晶體302、第三開關電 晶體303、第四開關電晶體304、第五開關電晶體305、第六 開關電晶體306、第七開關電晶體307、第八開關電晶體308、 第九開關電晶體309、第十開關電晶體310、第十一開關電晶 體311、第十二開關電晶體312、第十三開關電晶體313、第 十四開關電晶體314可進一步串接或並接電容、電阻、二極 體或電晶體等電路基本元件以提升於實際應用時之特殊要. 求，如匹配等，雖本發明實施例揭露如上，然其並非用以限， 定本發明，因本發明記憶選擇電路可能因爲外界電路匹配需 求串接或並聯一電路元件。 □續次頁（發明說明頁不敷使用時，請註記並使用續頁） 12 ,1253649 因此，本發明提供一種二進二出讀取路徑之高速平面記 憶體單元結構，藉由控制選擇電路的開關，以達到兩條路徑 選擇電晶體記憶體單元，兩條路徑由電晶體記憶體單元輸出 的目的，更進一步來說，本發明所提供之多路徑輸入，其使 輸入路徑所構成之電阻得以並聯以達到降低阻抗的效果。因 此本發明可以依據所選擇的資料位置不同而產生不同之迴 路，並減少了電路複雜度。除此之外，由於本發明有低耗能、 低電阻及可快速讀取特性，因此非常適合應用於各類需記憶 體讀取裝置中。所以在數位系統的設計中，其可利用的範圍 將非常的廣闊。綜上所述，本發明「二進二出讀取路徑之高 速平面記憶體單元結構」爲一合理完善之發明，不僅具備優 良之實用性，而且在設計上屬前所未有的創新，具新穎性， 且可以完全由選擇電路的控制進而達到兩條路徑選擇電晶 體言己憶體單元，兩條路徑由電晶體記憶體單元輸出的讀取功 能，亦屬突破習知技術窠臼的高度發明，並非易於思及之單 純應用，具進步性，因此，本案業已符合發明專利之各項申 請要件，懇請鈞局於以詳查，並賜予應得之發明專利，實 爲感禱。 雖然本發明已以較佳實施例揭露如上，然其並非用以限 定本發明，任何熟悉本技藝之人士，在不脫離本發明之精神 和範圍內，當可做些許之更動與潤飾，因此本發明之保護範. 圍當視後附之申請專利範圍所界定者爲準。 續次頁（發明說明頁不敷使用時，請註記並使用續頁） 13 1253649 【圖式簡單說明】 圖式說明= 圖一係爲傳統選擇電路架構示意圖； 圖二係爲傳統另一選擇電路架構示意圖；以及 圖三係爲本發明之一較佳實施例選擇電路架構示意圖 【圖號說明】 電晶體——10、11、12 電晶體記憶體單元-…· 節點.................341、 、20 -331 342 第一選擇線——……-31 第二選擇線...............32 記億體陣列............-33 位元選擇線-..............34 字元選擇線...............37 第一模擬接地端.........35 第二模擬接地端………36 第一開關#電晶體——…301 第二開關電晶體---------302 第三開關電晶體——-303 第四開關電晶體…--…-304 第五開關電晶體……-305 第六開關電晶體---------306 第七開關電晶體---------307 第八開關電晶體---------308 第九開關電晶體-........309 [□續次頁（發明說明頁不敷使用時，請註記並使用續頁） 14 ,1253649 第十開關電晶體---------310 第十一開關電晶體——311 第十二開關電晶體——312 第十三開關電晶體——313 第十四開關電晶體——314 續次頁（發明說明頁不敷使用時，請註記並使用續頁）1,125,649, 发明, the description of the invention (the description of the invention should be described: the technical field, prior art, content, embodiment and schematic description of the invention) TECHNICAL FIELD OF THE INVENTION The present invention relates to a planar memory unit (FLAT) CELL), especially regarding a circuit for reading a planar memory cell (FLAT CELL). [Prior Art] In the memory selection circuit, how to use a simple process and fast reading of data and reduce the resistance of the selection circuit when reading data has always played a very important role, but in the current environment, the reading circuit The resulting resistance and capacitance effects are unavoidable, so how to more effectively reduce the resistance and capacitance effects and thus the performance of the system is the goal of all the people who have been working hard. U.S. Patent No. 6,084,794 to Ding-Jou Lu et al.: HIGy SPEED FLAT-CELL MASK ROM STRUCTURE WITH SELECT LINES, which is read by simultaneous short circuit to select the transistor on both sides of the read data. Take the data effect, as shown in Figure 1, if the external system wants to read the data of the transistor 11, it must first short-circuit the transistor 10 on both sides and the transistor 12 before reading the data of the transistor U. The method of controlling the data in the memory is complicated, and the short circuit of the two sides is required when reading the data. The noise is disturbed due to the parasitic capacitance effect and other factors are caused, and the system does not operate normally. π further solve the above problem, another known technology as shown in Figure 2, when the U, / person page (the description of the page is not enough, please note and use the continuation page) 7 1253649 Read the technology of the transistor 20, borrow By setting the first analog ground (VG(0)) 35 to logic "1", the bit select line (BL(0)) 34 to logic "1", and the first select line (SL(0)) 31 to logic "1", the second selection line (SL(1)) 32 is logic "0", and the second analog ground (VG(1)) 36 is logic "0", so that the transistor 20 constitutes a read loop, so that The external can correctly read the data in the transistor 20, improve the short circuit of the US Patent No. 60847794, and reduce the capacitance effect, but can not solve the problem of reading the data in the transistor memory as logic, 〇, 时Since the current generated by the bit selection line (BL(0)) causes interference between circuit elements, the reading speed cannot be improved, but with the advancement of technology, people demand fast and correct reading of memory. The requirements are getting higher and higher, so the light effect caused by the short circuit caused by the light selection selection circuit when selecting the memory It is not enough, how to effectively reduce the read data of resistance and capacitance effects to enhance the performance of memory modules is also the goal of all WH developers long-term effort. Accordingly, the present invention provides a selection circuit for reducing the resistance of reading memory cell data and reducing interference, providing more read loops to reduce system resistance and capacitance effects, and thereby improve performance. SUMMARY OF THE INVENTION The main object of the present invention is to provide a high-speed planar memory cell structure for two-input and two-out read paths, and to select a desired transistor memory cell by two paths and two paths to be memorized by an output transistor. Body, in order to achieve the purpose of reading the contents of the memory. Another object of the present invention is to provide a method for selecting a memory circuit to reduce the number of pages (when the description of the page is insufficient, please note and use the continuation page) 8 , 1253649 Capacitance and resistance when reading low memory contents effect. The present invention provides a selection circuit for a high speed planar memory cell having a binary input and output read path. The present invention includes at least a first select line (SL(0)) 31 and a second select line (SL(1)) 32. A memory array 33, a bit selection line (BL(0)) 34, a first analog ground (VG(0)) 35, a second analog ground (VG(1)) 36, a character The selection line 37, a first switching transistor 301, a second switching transistor 302, a third switching transistor 303, a fourth switching transistor 304, a fifth switching transistor 305, and a sixth switching transistor 306, a seventh switching transistor 307, an eighth switching transistor 308, a ninth switching transistor 309 - a tenth switching transistor 310, an eleventh switching transistor 311 a twelfth switching transistor 312, a tenth The three-switch transistor 313 and the fourteenth switch transistor 314 can achieve the purpose of reading the data in the memory array 33 by controlling the respective switch transistors. In addition, the present invention can also achieve two path selection transistor memories. The effect of the unit and the two paths output by the transistor memory unit 'reduced external reading the present invention The resistance is 値. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention has been described in detail with reference to the preferred embodiments thereof Referring to the schematic diagram of the architecture of FIG. 3, the present invention provides a high-speed planar memory cell structure with two input and two output read paths, which can be selected by using two input paths and two output paths to select corresponding transistor memory cells. Read the continuation of the next page (send the date of the month and the sun and the stomach + apply '言靑|£言己) 9 1253649 For the purpose of the billion-body data, the structure at least includes: a first selection line 31, a second selection line 32. A memory array 33, a bit selection line 34, a first analog ground terminal 35, a second analog ground terminal 36, a word selection line 37, a first switching transistor 301, and a second switch The transistor 302, a third switching transistor 303, a fourth switching transistor 304, a fifth switching transistor 305, a sixth switching transistor 306, a seventh switching transistor 307, and an eighth switching transistor 308, a ninth switching transistor 309, a tenth switching transistor 310, an eleventh switching transistor 311 twelfth switching transistor 312, a thirteenth switching transistor 313 and a fourteenth switching transistor 314; The character selection line 37 is used to connect the memory The gate of the transistor in the array 33; wherein the first selection line 31 is connected to the third switching transistor 303, the fourth switching transistor 304, the fifth switching transistor 305, the sixth switching transistor 306, and the eighth a gate of the switching transistor 308, the ninth switching transistor 309, the thirteenth switching transistor 313, and the fourteenth switching transistor 314; wherein the second selection line 32 is connected to the first switching transistor 301, a gate of the second switching transistor 302, the seventh switching transistor 307, the tenth switching transistor 310, the eleventh switching transistor 311 and the twelfth switching transistor 312; the first switching transistor 301 and the third switch The transistor 303, the eighth switching transistor 308 and the tenth switching transistor 310 control the conduction between the first analog ground 35 and the memory array 33; the fourth switching transistor 304, the fifth switching transistor 305, The seven-switch transistor 307, the eleventh switch transistor 311, the thirteenth switch transistor 313, and the fourteenth switch transistor 314 control the conduction between the bit select line 34 and the memory array 33; Crystal 302, sixth switching transistor 306, The ninth □ continuation page (when the invention page is not enough, please note and use the continuation page) 1253649 The switch transistor 309 and the twelfth switch transistor 312 control the second analog ground terminal 36 and the memory array 33 Turning on; controlling the first selection line 31, the second selection line 32, the bit selection line 34, the first analog ground terminal 35, and the second analog ground terminal 36 to cause the outside world to read the data in the memory array to generate a second The second read current path is formed to form a read loop. In other words, taking the read transistor memory unit 331 as an example, when the first select line 31 is logic "1", the second select line 32 is logic "0", and the bit select line 34 is logic "1", The first analog ground terminal 35 is logic "1" and the second analog ground terminal 36 is logic "0" such that the first switching transistor 301 is in an off state, the second switching transistor 302 is in an off state, and the third switching transistor 303 is in a cut-off state. In the on state, the fourth switching transistor 304 is in an on state, the fifth switching transistor 305 is in an on state, the sixth switching transistor 306 is in an on state, the seventh switching transistor 307 is in an off state, and an eighth switching transistor. 308 is in an on state, the ninth switching transistor 309 is in an on state, the tenth switching transistor 310 is in an off state, the eleventh switching transistor 311 is in an off state, the twelfth switching transistor 312 is in an off state, and the thirteenth switch The transistor 313 is in an on state and the fourteenth switching transistor 314 is in an on state; wherein the fourth switching transistor 304 is in an on state, such that the bit selection line 34 and the transistor 331 form an input path, and The turn-off transistor 303 is in an on state, so that an output path can be formed in the transistor 331 by the third switch transistor 303 and the first analog ground terminal 35, and the bit line is selected by the conduction system of the thirteenth switch 303. The line 34 and the transistor 331 generate the input and output diameter of the second strip, and the first * analog ground terminal 35 and the electromorphic crystal are caused by the eighth switching transistor 308 being conductive ([Continuation] When using, please note and use the continuation page) 11 1253649 The body 331 generates the output path of the second strip, thereby achieving the effect of the two paths selecting the transistor memory unit, the two paths being output by the transistor memory unit, and When the gfi memory cell is selected, the loop is formed. Since there are two input paths and two output systems, the input and output simultaneously form a parallel effect, thereby further reducing the resistance 本 of the present invention when being read, so that the external circuit is The resistance and capacitance effects of the invention are reduced, and the effect is not only to reduce noise, reduce energy consumption, and improve frequency response, but also to reduce the temperature of the overall system when the present invention is used. . As a result of the above, the selective memory circuit of the present invention can produce two path selection transistor memory cells and the effect of two paths outputted by the transistor memory cells, wherein the electromorphic system of the present invention can be oxidized by complementary metals. The semiconductor technology (Complementary Metal-Oxide Semiconductor, CM〇S) process technology or the silicon-on-insulator (SOI) process technology is completed, and the first switching transistor 301, the second switching transistor 302, and the third switching device The crystal 303, the fourth switching transistor 304, the fifth switching transistor 305, the sixth switching transistor 306, the seventh switching transistor 307, the eighth switching transistor 308, the ninth switching transistor 309, and the tenth switching transistor 310, the eleventh switching transistor 311, the twelfth switching transistor 312, the thirteenth switching transistor 313, and the fourteenth switching transistor 314 can further be connected in series or in parallel with a capacitor, a resistor, a diode or a transistor. The basic elements of the circuit are used to improve the special requirements of the actual application, such as matching, etc., although the embodiments of the present invention are disclosed above, the present invention is not limited thereto, and the present invention is Since the external memory selection circuit may matching circuit needs a circuit element connected in series or in parallel. □Continued page (when the invention page is not enough, please note and use the continuation page) 12,1253649 Therefore, the present invention provides a high-speed planar memory cell structure for the binary input and output read paths, by controlling the selection circuit Switching to achieve two paths to select a transistor memory cell, the two paths are output by the transistor memory cell, and further, the multipath input provided by the present invention allows the resistance formed by the input path to be Parallel to achieve the effect of reducing impedance. Therefore, the present invention can generate different circuits depending on the position of the selected data, and the circuit complexity is reduced. In addition, since the present invention has low power consumption, low resistance, and fast reading characteristics, it is well suited for use in various types of memory reading devices. Therefore, in the design of digital systems, the range that can be utilized will be very broad. In summary, the "high-speed planar memory cell structure of the two-input and two-out read paths" of the present invention is a reasonably perfect invention, which not only has excellent practicability, but also has unprecedented innovation in design and novelty. And it can be completely controlled by the selection circuit to achieve two paths to select the transistor, and the reading function of the two paths outputted by the transistor memory unit is also a high-invention that breaks through the conventional technique, and is not easy. The simple application of thinking is progressive. Therefore, the case has already met the requirements of various patents for invention patents, and it is prayed that the bureau has carefully examined and granted the invention patents due. While the present invention has been described above in terms of the preferred embodiments thereof, it is not intended to limit the invention, and those skilled in the art can make some modifications and refinements without departing from the spirit and scope of the invention. The scope of protection of the invention is subject to the definition of the scope of the patent application. Continued page (When the invention page is not enough, please note and use the continuation page) 13 1253649 [Simple description of the diagram] Schematic description = Figure 1 is a schematic diagram of the traditional selection circuit architecture; Figure 2 is a traditional alternative circuit Schematic diagram of the architecture; and Figure 3 is a schematic diagram of the selection circuit architecture of a preferred embodiment of the present invention. [Description of the figure] The transistor - 10, 11, 12 transistor memory unit - ... · node .... ..........341, 20-331 342 First choice line——...-31 Second choice line...............32 Billion body Array............-33 bit selection line-..............34 character selection line........... ....37 first analog ground terminal.........35 second analog ground terminal.........36 first switch#transistor-...301 second switch transistor ------ ---302 The third switch transistor——-303 The fourth switch transistor...--...-304 The fifth switch transistor...-305 The sixth switch transistor---------306 Switching transistor---------307 eighth switching transistor---------308 ninth switching transistor-........309 [□ continued page (invention Description page is not enough Please note and use the continuation page) 14 ,1253649 Tenth Switching Transistor ---------310 Eleventh Switching Transistor - 311 Twelfth Switching Transistor - 312 Thirteenth Switching Transistor ——313 The fourteenth switch transistor——314 Continued page (Please note and use the continuation page when the invention page is not enough)