1253605 九、發明說明： 【發明所屬之技術領域】 本發明係有關一種具單面板功能測試之靜電放電 防4整合電路’係、於ESD防護單元電路中包括-具 二面板功％測《之功能，而不量測時為—靜電防護電路。 【先前技術】 、f膜電晶體液晶顯示器（TFT_LCD)是目前相當成熟 的’但因為TFT元件製作在玻璃絕緣面版上，在面板 成=製作過程中，經常發生靜電放電（ESD)相關的問題， 、旦面板中有電晶體元件遭受ESD破壞，在面板顯示區形 成點缺陷或線缺陷，如此該面板即歸為瑕疵品，其良率損 失會相當嚴重。 在TFT製作量產產品過程中（矩陣陣列製程、基板組 合製程（Cell process)與模組化製程），ESD的產生是非常顯 而易見的現象，靜電造成矩陣陣列之TFT元件閘極絕緣層 被打穿與非常大的漏電流，因此靜電的發生對產品良率影 響極大。靜電防護設計可預防外來因素產生靜電如：人 為、機台設備，提升元件電晶體靜電防護效果，達到較妥 善的靜電防護，且單面板功能測試(Cell test function)功能 需額外設計。 習用靜電防護設計上，該靜電防護方式是以二顆電晶 體以二極體(Diode)方式逆向連接形成一 ESD防護單元 10，在每一訊號線丨2(掃描線或資料線）皆接該防護單元 10，用以該訊號線12受靜電防護（如『第1圖』所示）。 1253605 其中電晶體Til 一端接IC墊11與訊號線12,同時與電晶 體丁21的源極連接，電晶體τιι另一端接共用電極13與 電晶體T21的汲極連接。其靜電排放路徑，電晶體T11為 排正靜電元件、電晶體T21為排放負靜電元件，該防護單 元1〇電路雖可達到靜電防護效果，但效能上較不盡理想， 因為在單一條訊號線12只有單一個ESD防護單元1〇提供 靜電排放路徑。 對TFT製程而言，單面板功能測試（Cell test functi〇n) 過程是一道彳艮重要的檢測步驟，此測試過程可節省後段不 必要模組組裝成本，目前單面板功能測試主要分為二個方 法。方法一’短接線（Shorting bar)法：先將所有掃描線（Scan 1^1^8)與負料線（Data Lines)分別以短接線（Shorting bar)方 式連接’再通電壓做顯不晝面的測試。但一旦完成該測 試’還必須以雷射切割（Lasercut)機台將短接線(sh〇rting bar)與掃描線(scan Lines)與資料線(Data Lines)之連接線燒 斷，使每一條掃描線(Scan Line)與掃描線(Scan Line)間將 各自獨立；且每一條資料線(DataLines)與資料線(Data Line)間將各自獨立。 方法二’ TFT開關（TFT Switch)法：係在設置顯示畫 素之矩陣區20外，在每一掃描線與資料線上做一 TFT開 關元件22連接至顯示矩陣區2〇(請參閱「第2圖」所示）， 將欲輸入電壓訊號所有的TFT開關元件22的閘極連接到 測試開關墊PDSA，另也將所有的TFT開關元件汲極連接 在所屬測試墊PSE、PS0、PDR、PDG、PDB (分為奇偶與 1253605 R G、b) ’ TFT開關元件22的源極則連接掃描線與資料 線輸入至顯示矩陣區。只要在測試墊PSE、PSO、PDR、 PDf、PDB與共用電極（vcom)加上顯示晝面電壓，與加上 電壓在測試開關墊PDSA上使TFT開關元件22為，，〇N，，， 即可達到測试功能，此方法雖不像方法一需以雷射切割機 再進行切除動作，但其靜電防護電路需額外製作，才可達 到靜電防護效果。 【發明内容】 爰是，為解決上述之缺失，本發明主要目的在於所提 供之靜電放電(ESD)防護整合電路，利肖励防護單元防 護電路之其中-顆電晶體當作—TFT開關，且單面板功 能測試(cell test function)建構於原本ESD防護單元電路之 中’不需再額外製作靜電防護電路或TFT開關，使本發 明之ESD防護單元電路包括具單面板功能_之功能，而 不量測時為一靜電防護電路。 本發明另—目的在於’每—E S D防護單元皆盘所有掃 描線或資料線上之ESD防護單元減接，此咖防護單 70的並聯樣祕會形成-較佳靜電防護絲，透過此設計 每- ESD防護單元將可提升其對應訊號線之靜電防制保 護耐受能力。 本發明再-目的在於，因為單面板功能測試之FT開 關已包含於每-ESD防護單元，所以可增加非破壞性之單 面板功能賴’但料像短躲，於完成單面板測 試後尚需添加雷射切㈣製程’將可有效節省講買機台成 1253605 〇 本發明係一種具單面板功能測試之靜電放電（esd 防護整合電路，係用於薄膜電晶體液晶顯示面板之esd防 護單元電路，係於顯示面板之顯示晝素之矩陣區外，且^ 一掃描線與資料線之訊號線上設有一 ESD防護單元，其中 每一該ESD防護單元電路包括·· ” 電 一第一薄膜電日曰體興一弟二薄膜電晶體的閘極盥及 極短路，且與-訊號線相n三—電日日日體之間極與 該第-薄膜電晶體之源極相接，並與相鄰訊號線(掃描線/或 =料線)上之ESD防護單元之第-薄臈電晶體之源極 三薄膜電晶體之閘極相接；且該第三薄膜電晶體之㈣I 第二薄膜電晶體之雜相接，並與所有掃織或線、 之ESD防護單元之第二薄膜電晶體之源極與第三、·' 晶體之汲極相接。 一第四薄膜電晶體與一第五薄骐電晶體 極短路’織與該第三薄膜電晶體之源極相接於^共^及 極。-第六薄膜電晶體之汲極與該第四薄膜電晶體=電 相接’並與相鄰訊號線(掃描線或資料線)上的E j 7L之第六薄膜電晶體之汲極與第四薄膜電曰 4早 接。且該第六薄膜電晶體之沒極與1 :之源極相 =::=置:訊號線(掃描線 線相接。^極，又該第六薄膜電晶體之源極與該t、 該第五薄膜電晶體之源極與該第六薄膜電晶體之閑 1253605 極相接，並與相鄰訊號線(掃描線或資料線)上的ESD防護 單元之第五薄膜電晶體之源極與該弟六薄膜電晶體之閘 極相接。且該第六薄膜電晶體之閘極與一測試開關墊連 接，該測試開關墊連接於該顯示面板中所有訊號線上該第 六薄膜電晶體之閘極。 【實施方式】 茲有關本發明之詳細内容及技術説明，現配合圖式說 明如下： 請同時參閱『第3、4、5圖』所示，係本發明之ESD 防護單元、相鄰ESD防護單元之電路及ESD防護單元於 單一顯示面板之配置示意圖。本發明係一種具單面板功 能測試之靜電（ESD)防護整合電路，係用於薄膜電晶體液 晶顯示面板之ESD防護單元30電路，係於顯示面板之 顯示晝素之矩陣區100外，且每一掃描線與資料線之訊 號線32上設有一 ESD防護單元30，其中每一該ESD防 護單元30電路包括： 一第一薄膜電晶體T1與一第二薄膜電晶體T2的閘 極與汲極短路，且與一訊號線32及1C塾31 (該1C墊 31 即第 5 圖中的 Scan N、Scan N+1、Scan N+2、Data N、1253605 IX. Description of the Invention: [Technical Field] The present invention relates to an electrostatic discharge anti-4 integrated circuit with a single panel function test, and includes a function of a second panel function in an ESD protection unit circuit. When not measuring, it is an electrostatic protection circuit. [Prior Art], f-film transistor liquid crystal display (TFT_LCD) is quite mature at present. But because TFT components are fabricated on glass-insulated panels, electrostatic discharge (ESD)-related problems often occur during panel formation. In the panel, the TFT component is damaged by ESD, and a dot defect or a line defect is formed in the panel display area, so that the panel is classified as a defective product, and the yield loss thereof is quite serious. In the process of manufacturing mass production products for TFTs (matrix array process, cell process, and modular process), the generation of ESD is very obvious. Static electricity causes the TFT element gate insulating layer of the matrix array to be broken. With very large leakage currents, the occurrence of static electricity has a great impact on product yield. The ESD protection design prevents external factors from generating static electricity such as: artificial, machine equipment, lifting device crystal electrostatic protection effect, achieving better static protection, and the additional test function of the single panel function test (Cell test function). In the conventional electrostatic protection design, the electrostatic protection method is to reversely connect two ECDs in a diode to form an ESD protection unit 10, and each signal line 2 (scanning line or data line) is connected. The protection unit 10 is configured to protect the signal line 12 by static electricity (as shown in FIG. 1). 1253605 One end of the transistor Til is connected to the IC pad 11 and the signal line 12, and is connected to the source of the electric crystal body 21, and the other end of the transistor τι is connected to the drain electrode of the transistor T21. The electrostatic discharge path, the transistor T11 is a positive electrostatic component, and the transistor T21 is a negative electrostatic component. The protection unit 1〇 circuit can achieve electrostatic protection effect, but the performance is less than ideal, because in a single signal line 12 Only a single ESD protection unit 1 provides an electrostatic discharge path. For the TFT process, the single test function test (Cell test functi〇n) process is an important test step. This test process can save unnecessary module assembly cost in the latter stage. Currently, the single-panel function test is mainly divided into two. method. Method 1 'Shorting bar method: first connect all the scanning lines (Scan 1^1^8) and negative lines (Data Lines) with short-circuit (Shorting bar) respectively. Face test. But once the test is completed, you must also burn the connection between the short wire (sh〇rting bar) and the scan line (scan Line) and the data line (Data Lines) with a laser cutting machine. The Scan Line and the Scan Line will be independent of each other; and each DataLines and Data Line will be independent. Method 2 'TFT Switch Method: In addition to the matrix area 20 for setting the display pixels, a TFT switching element 22 is connected to the display matrix area 2 on each scan line and data line (see "2nd" As shown in the figure, the gates of all the TFT switching elements 22 to which the voltage signals are to be input are connected to the test switch pad PDSA, and all the TFT switching elements are also connected to the test pads PSE, PS0, PDR, PDG, PDB (divided into parity and 1253605 RG, b) 'The source of the TFT switching element 22 is connected to the scanning line and the data line input to the display matrix area. As long as the test pads PSE, PSO, PDR, PDf, PDB and the common electrode (vcom) are added with the display surface voltage, and the applied voltage is applied to the test switch pad PDSA, the TFT switching element 22 is, 〇N,, The test function can be achieved. Although this method does not require a laser cutting machine to perform the resection action, the electrostatic protection circuit needs to be additionally fabricated to achieve the electrostatic protection effect. SUMMARY OF THE INVENTION In order to solve the above-mentioned shortcomings, the main object of the present invention is to provide an electrostatic discharge (ESD) protection integrated circuit, in which a transistor of the protective unit protection circuit is regarded as a TFT switch, and The single-cell function test function is built in the original ESD protection unit circuit. No additional electrostatic protection circuit or TFT switch is required, so that the ESD protection unit circuit of the present invention includes a single-panel function, and When measuring, it is an electrostatic protection circuit. Another object of the present invention is to reduce the ESD protection unit of all scan lines or data lines for each ESD protection unit. The parallel type of the coffee protection sheet 70 will form a better electrostatic protection wire. The ESD protection unit will increase the electrostatic protection against the corresponding signal lines. The present invention again aims to increase the non-destructive single-panel function because the FT switch for the single-panel function test is included in each-ESD protection unit, but it is still necessary to complete the single-panel test. Adding the laser cutting (four) process 'will save the platform to become 1235605. 〇This invention is a kind of electrostatic discharge with single panel function test (esd protection integrated circuit, used for esd protection unit circuit of thin film transistor liquid crystal display panel) , is disposed outside the matrix area of the display panel of the display panel, and has an ESD protection unit on the signal line of the scan line and the data line, wherein each of the ESD protection unit circuits includes a first thin film electric day The gate and the short circuit of the thin film transistor of the body, and the phase of the signal line, and the source of the first and second thin film transistors, and the phase The gate of the third thin film transistor of the first thin-thin transistor of the ESD protection unit on the adjacent signal line (scanning line/or = the material line); and the fourth thin film of the third thin film transistor The crystals are intertwined and The source of the second thin film transistor having the ESD protection unit of the woven or wire, is connected to the third, and the bottom of the crystal. The fourth thin film transistor is short-circuited with a fifth thin germanium transistor. The source of the third thin film transistor is connected to the common electrode. The drain of the sixth thin film transistor is electrically connected to the fourth thin film transistor and is adjacent to the signal line (scan line or The drain of the sixth thin film transistor of E j 7L on the data line is early connected to the fourth thin film electric cymbal 4. And the immersion of the sixth thin film transistor is the source phase of 1:=:= a signal line (the scanning line is connected to the cathode), and the source of the sixth thin film transistor is connected to the source of the fifth thin film transistor and the idle 122655 of the sixth thin film transistor, and The source of the fifth thin film transistor of the ESD protection unit on the adjacent signal line (scanning line or data line) is connected to the gate of the sixth thin film transistor, and the gate of the sixth thin film transistor is A test switch pad is connected, and the test switch pad is connected to the gate of the sixth thin film transistor on all signal lines in the display panel. The details and technical description of the present invention are as follows: Please also refer to the "Figures 3, 4, and 5", which are the ESD protection unit of the present invention, the circuit of the adjacent ESD protection unit, and the ESD. The utility model relates to a configuration diagram of a single display panel. The invention relates to an electrostatic (ESD) protection integrated circuit with single panel function test, which is used for the circuit of the ESD protection unit 30 of the thin film transistor liquid crystal display panel, which is displayed on the display panel. An ESD protection unit 30 is disposed on the signal line 32 of each scan line and data line. Each ESD protection unit 30 circuit includes: a first thin film transistor T1 and a second The gate of the thin film transistor T2 is short-circuited with the drain, and is connected to a signal line 32 and 1C塾31 (the 1C pad 31 is Scan N, Scan N+1, Scan N+2, Data N in FIG. 5,
DataN+1、DataN+2)相接；一第三薄膜電晶體π之閘 極與該第一薄膜電晶體Τ1之源極相接，而該第三薄膜電 晶體Τ3之閘極除與該第一薄膜電晶體T1之源極相接 外，並與所有掃描線或資料線上的ESD防護單元30之 第一薄膜電晶體T1之源極與第三薄膜電晶體T3之閘極 1253605 相接。且該第三薄膜電晶體T3之汲極與第二薄膜電晶體 Τ2之源極相接，而該第二薄膜電晶體Τ2之源極除與該 第三薄膜電晶體Τ3之汲極相接外，並與相鄰訊號線32(掃 描線或資料線)上的ESD防護單元30之第二薄膜電晶體 Τ2之源極與第三薄膜電晶體Τ3之汲極相接，形成所有 訊號線32(掃描線或資料線）上的ESD防護單元30的第二 薄膜電晶體Τ2之源極與第三薄膜電晶體Τ3之汲極相連 一第四薄膜電晶體Τ4與一第五薄膜電晶體Τ5的閘 極與汲極短路，然後與該第三薄膜電晶體Τ3之源極相接 於一共用電極33,透過該共用電極33與顯示畫素之矩陣 區100之TFT晝素電極的壓差即可顯示圖面。一第六薄 膜電晶體T6之汲極與該第四薄膜電晶體T4之源極相 接，而該第六薄膜電晶體T6之汲極除與該第四薄膜電晶 體T4之源極相接外，並與相鄰訊號線32(掃描線或資料 線）上的ESD防護單元30之第六薄膜電晶體T6之汲極與 第四薄膜電晶體T4之源極相接，形成所有訊號線32(掃 描線或資料線)上的ESD防護單元30内第六薄膜電晶體 T6之汲極與第四薄膜電晶體T4之源極相連接。 又該第六薄膜電晶體T6之汲極與一測試墊35連 接，而該測試墊35進一步可分為一掃描測試墊35S與一 資料測試墊35D，分別連接所有屬於掃描線或資料線之 訊號線32上該第六薄膜電晶體T6之汲極。而每一 ESD 防護單元30内之第六薄膜電晶體T6之源極與該對應之 1253605 H線32(掃描線或資料 進一步可根據掃描線分奇、偶二種塾说 線分奇、偶二種 "弟五薄膜電晶體丁5之 T6之閘極相接，該第 4，、賴電曰曰體 六薄膜電曰驊、冤日日體Τ5之源極除與該第 、日日體Τ6之閘極相接外，並與 描線或資料線)上^ w枝線3聊 Τ5之源極^ 4早兀30之第五薄膜電晶體 Τ5之源極與第六薄膜電晶體Τ6之 訊號線32(掃描線或資料線)上的Ε % 源極與第六_晶體 接。且该苐六薄膜電晶體Τ6 、心甘丄 之閘極與-測試開關墊34 連接，其中該測試開關墊34連接於該顯示面板中所㈣ 號線32上該第六薄膜電晶體T6之閘極。 本發明之ESD防護單元3G整合電路在鮮面板功 能測試時或靜電防護之作動方式分別如下·· -、本發日狀ESD防護單元％整合電路在做單面 板功能測試時，在測試開關墊3 4加一打開第六薄膜電晶 體T6電壓準位，該掃描測試塾35S加—掃描電壓準位， 該資料測试墊35D加一資料電壓準位，共用電極％接一 直流(DC)或交流(AC)準位。例如，我們可於測試開關墊 34加- 25V、測試塾35加-應該之電塵準位(婦描測試 墊35S加一 15V、資料測試墊35D加_ 4V)、共用電極 33加一 〇V，此時第四薄膜電晶體T4、乃為”〇即”，第 六薄膜電晶體Τ6為’’on”（此時薄臈電晶體、Τ3 1253605 j 〇N”），而由前述已知”六薄膜電晶體T6之汲極 =該第四薄膜電晶體Τ4之源極相接外，並與所有相對 ，線或資料線的㈣防護單元30之第六薄膜電晶 ，T6之沒極與第四薄膜電晶體了4之源極相接，則該測 ，墊35(掃描測試塾35S，資料测試整35d)之電壓將透過 ^級ESD防護單元3G内之第六薄膜電晶體τ6傳到該 訊破線32(掃描線、㈣線），使㈣面板之訊號線”輸 入該矩陣區100内之顯示晝素所需之工作電壓。DataN+1, DataN+2) are connected; a gate of a third thin film transistor π is connected to a source of the first thin film transistor Τ1, and a gate of the third thin film transistor Τ3 is divided by the first The source of a thin film transistor T1 is connected to the source, and the source of the first thin film transistor T1 of the ESD protection unit 30 on all scan lines or data lines is connected to the gate 1235605 of the third thin film transistor T3. The drain of the third thin film transistor T3 is in contact with the source of the second thin film transistor ,2, and the source of the second thin film transistor Τ2 is connected to the drain of the third thin film transistor Τ3. And connecting the source of the second thin film transistor Τ2 of the ESD protection unit 30 on the adjacent signal line 32 (scanning line or data line) to the drain of the third thin film transistor Τ3 to form all the signal lines 32 ( The source of the second thin film transistor Τ2 of the ESD protection unit 30 on the scan line or the data line is connected to the drain of the third thin film transistor Τ3, and the gate of the fourth thin film transistor Τ4 and a fifth thin film transistor Τ5 The pole and the drain are short-circuited, and then connected to the source of the third thin film transistor Τ3 to a common electrode 33, and the voltage difference between the common electrode 33 and the TFT pixel electrode of the matrix region 100 of the pixel is displayed. Drawing. a drain of a sixth thin film transistor T6 is in contact with a source of the fourth thin film transistor T4, and a drain of the sixth thin film transistor T6 is connected to a source of the fourth thin film transistor T4. And connecting the drain of the sixth thin film transistor T6 of the ESD protection unit 30 on the adjacent signal line 32 (scanning line or data line) to the source of the fourth thin film transistor T4 to form all the signal lines 32 ( The drain of the sixth thin film transistor T6 in the ESD protection unit 30 on the scan line or the data line is connected to the source of the fourth thin film transistor T4. The drain of the sixth thin film transistor T6 is connected to a test pad 35, and the test pad 35 can be further divided into a scan test pad 35S and a data test pad 35D, respectively connecting all the signals belonging to the scan line or the data line. The drain of the sixth thin film transistor T6 on line 32. The source of the sixth thin film transistor T6 in each ESD protection unit 30 and the corresponding 1223625 H line 32 (scanning lines or data can further be divided according to the scanning line, even two kinds of lines, odd and even two "The fifth of the thin film transistor D5's T6 gate, the fourth, the Lai electric body six thin film electric 曰骅, the day of the Japanese body Τ 5 source and the first, the Japanese body闸6 of the gate is connected to the outside, and with the line or data line) ^ w branch line 3 chat Τ 5 source ^ 4 early 兀 30 of the fifth thin film transistor Τ 5 source and the sixth thin film transistor Τ 6 signal The Ε% source on line 32 (scan or line) is connected to the sixth _ crystal. And the gate of the sixth thin film transistor Τ6 and the cardigan is connected to the test switch pad 34, wherein the test switch pad 34 is connected to the gate of the sixth thin film transistor T6 on the (4) line 32 of the display panel. . The ESD protection unit 3G integrated circuit of the present invention is used in the function test of the fresh panel or the static electricity protection as follows: - The present day ESD protection unit % integrated circuit is used in the single panel function test, in the test switch pad 3 4 plus one to open the sixth film transistor T6 voltage level, the scan test 塾 35S plus - scan voltage level, the data test pad 35D plus a data voltage level, the common electrode % connected to the current (DC) or AC (AC) level. For example, we can test the switch pad 34 plus - 25V, test 塾 35 plus - should be the electric dust level (the test pad 35S plus a 15V, the data test pad 35D plus _ 4V), the common electrode 33 plus a 〇V At this time, the fourth thin film transistor T4 is "〇", and the sixth thin film transistor Τ6 is ''on' (at this time, thin germanium transistor, Τ3 1253605 j 〇N"), and is known from the foregoing" The drain of the six thin film transistor T6 = the source of the fourth thin film transistor Τ4 is connected, and the sixth thin film of the (4) protection unit 30 of the opposite line or data line, the T6 of the pole and the When the four thin film transistors are connected to each other, the voltage of the pad 35 (scanning test 塾35S, data test 35d) will be transmitted to the sixth thin film transistor τ6 in the ESD protection unit 3G. The signal breaks the line 32 (scanning line, (four) line), and the signal line of the (four) panel is input into the operating voltage required for displaying the pixels in the matrix area 100.
二、本發明之ESD防護單元3〇在做靜電防護時，假 如在訊號、線32(掃描、線、資料線)產生正壓靜電，，第一 、一、二電晶體ΤΙ、Τ2、Τ3同時為，，0Ν，，，正壓靜電會 :訊號線32所屬單一 ESD防護單元3〇做一排放，此路 仁僅為其中之一。此時掃描線或資料線處於高準位狀態 所以可導通(ON)第一、二薄膜電晶體τι、Τ2，這時第2. When the ESD protection unit 3 of the present invention is performing electrostatic protection, if the positive voltage static electricity is generated in the signal and line 32 (scanning, line, data line), the first, first and second transistors ΤΙ, Τ2, Τ3 simultaneously For, 0Ν,,, positive pressure static electricity: the signal line 32 belongs to a single ESD protection unit 3 to make a discharge, this way is only one of them. At this time, the scanning line or the data line is in a high level state, so the first and second thin film transistors τι, Τ2 can be turned on (ON).
一、第二薄膜電晶體ΊΠ、T2之源極處於高準位狀態，因 此可導通(ON)相對應之第三薄膜電晶體T3，正壓靜電排 放路徑將經由該訊號線32 (掃描線、資料線)所屬之第三 薄膜電晶體Τ3排放。又，此時所有訊號線32 (掃描線、 資料線）上之ESD防護單元30，根據前述可得知正壓靜 電排放路梭不只經由該訊號線32所屬之第三薄膜電晶體 Τ3排放，同時可藉由其它訊號線32 (掃描線、資料線) 上的ESD防護單元3〇之第三薄膜電晶體Τ3導通做一多 工路徑排放靜電，透過此設計將可卓實提升靜電防護效 能’進而提升面板生產良率，排放負壓靜電原理亦然。 12 1253605 同時此靜電防護設計並不會影響單面板功能測試（Cell test function)或產品模組段之驅動（Module Driving)正 常顯示晝面。 綜上所述’本發明之具單面板功能測試之靜電放電 (ESD)防護整合電路之優點在於，本發明係利用esd防 護單元30電路之其中一顆電晶體當作TFT開關元件， 此TFT開關元件具備單面板功能測試，使本發明之eSd 防護單兀30電路包括具備單面板功能測試之功能，而不 測試時為一靜電防護電路。且該esd防護單元30的並 聯樣態將會達到較佳的靜電防護電路，藉此每一 ESD防 4單το 30將可提升其對應訊號線之靜電防制保護耐受能 力。 同時因為該TFT開關已包含於每一 ESD防護單元 3〇 ’所以可增加非破縣之單面板功能測試 ，但卻不像 而$知&接線’於完成單面板測試後尚需添加雷射切割 的製程，將可有效節省購買機台成本。 — 迷僅為本發明之較佳實施例而已，並非用來限 ^^實&之範圍。即凡依本發明中請專利範圍所做 …t化與修飾’皆為本發明專利範圍所涵蓋。 【圖式簡單說明】 第1圖，係習知 ^ 9 ^总 之ESD防護單元之電路示意圖。 第2圖，係習知1 丁 楚 ” 開關之顯示面板示意圖。 第3圖’係本發明 ESD防護單元之電路示意圖 1253605 第4圖，係本發明之相鄰ESD防護單元之電路示意圖。 第5圖，係本發明於單一顯示面板之配置示意圖。 【主要元件符號說明】 10、30 : ESD P方護單元 11 、 31 : 1C 墊 12、 32 • 訊號線 13、 33 • 共用電極 T11 、T21 :電晶體 T1 第 一 薄膜電晶 體 T2 第 二 薄膜電晶 體 T3 第 三 薄膜電晶 體 T4 第 四 薄膜電晶 體 T5 第 五 薄膜電晶 體 T6 第 六 薄膜電晶 體 20、100 :矩陣區 21 : ESD元件 參 22 : TFT開關元件 PDSA、34 :測試開關墊 PSE、PSO、PDR、PDG、PDB、35 ··測試墊 35S :掃描測試墊 35D :資料測試墊 141. The source of the second thin film transistor ΊΠ and T2 is in a high level state, so that the corresponding third thin film transistor T3 can be turned on (ON), and the positive pressure electrostatic discharge path will pass through the signal line 32 (scanning line, The data line) belongs to the third thin film transistor Τ3 discharge. Moreover, at this time, the ESD protection unit 30 on all the signal lines 32 (scanning lines, data lines) can know that the positive pressure electrostatic discharge road shuttle is discharged not only through the third thin film transistor 所属3 to which the signal line 32 belongs, but also The third thin film transistor Τ3 of the ESD protection unit 3 on the other signal line 32 (scanning line, data line) can be used to discharge static electricity through a multiplex path, and the design can improve the electrostatic protection performance. Improve the production yield of the panel and the principle of discharging the negative pressure static electricity. 12 1253605 At the same time, this ESD protection design does not affect the single panel function test (Cell test function) or the product module segment (Module Driving). In summary, the present invention has an advantage of an electrostatic discharge (ESD) protection integrated circuit with a single-panel function test. The present invention utilizes one of the transistors of the esd protection unit 30 circuit as a TFT switching element, and the TFT switch The component has a single panel function test, so that the eSd protection unit 30 circuit of the present invention includes a function of single panel function test, and is not an electrostatic protection circuit when tested. Moreover, the parallel state of the esd protection unit 30 will achieve a better static protection circuit, whereby each ESD protection 4 το 30 will improve the electrostatic protection protection tolerance of its corresponding signal line. At the same time, because the TFT switch is included in each ESD protection unit 3〇', it can increase the non-broken single-panel function test, but it does not seem like the “Knowledge & Wiring” needs to add laser after completing the single-panel test. The cutting process will effectively save the cost of purchasing the machine. The present invention is only a preferred embodiment of the present invention and is not intended to limit the scope of the & That is, all of the patents and the modifications made in the scope of the invention are covered by the scope of the invention. [Simple description of the diagram] Figure 1 is a schematic diagram of the circuit of the ESD protection unit. Fig. 2 is a schematic view of a display panel of a switch of the prior art. Fig. 3 is a schematic diagram of a circuit of the ESD protection unit of the present invention 1256305. Fig. 4 is a circuit diagram of an adjacent ESD protection unit of the present invention. The figure is a schematic diagram of the configuration of the present invention on a single display panel. [Description of main component symbols] 10, 30: ESD P square protection unit 11, 31: 1C pad 12, 32 • Signal line 13, 33 • Common electrode T11, T21: Transistor T1 First thin film transistor T2 Second thin film transistor T3 Third thin film transistor T4 Fourth thin film transistor T5 Fifth thin film transistor T6 Sixth thin film transistor 20, 100: Matrix region 21: ESD component reference 22 : TFT switching element PDSA, 34: Test switch pad PSE, PSO, PDR, PDG, PDB, 35 · Test pad 35S: Scan test pad 35D: Data test pad 14