12524881252488
五、發明說明α) 發明所屬之技術領域 本發明係關於一插9 w 性記憶胞，係由-電？=月包’特別是有關於-種非揮發 操續範圍之内兩個平板電容所構成，且在一 先前技術 上述平板電容之電容值係為固定值。 非揮發性記憶，缺 所儲存資料的能力。電技：喪失電力|’仍可以記住 性記憶體中之—種，=除式記憶體(EEP_)係為非發 中或由記憶胞中將資=一電子信號將資料寫入記憶胞 :極的結•’並且由-層多晶賴成之浮1 =用 據ό己憶胞之寫入而儲存電荷。 ’、' 美國專利編號第6, 191，980號專利，係揭露一種 EEPR〇M記憶胞，如第1圖中所示。纟中記憶胞100包括-PMOS電晶體MCI、-NMQS電晶體M2，以及—抹除|置^， 並係共用一層多晶矽閘極2〇6。並且為了增加控制閘極 與浮置閘極的耦合，更可包括一電容器c丨。然而，該 EEPR〇M 5己憶胞之寫入（program)及抹除（erase)係使用電晶 體結構來操作，舉例來說，一個記憶胞中同時會具有p井 區及N井區’故記憶胞的尺寸較大且增加了面積的需求。 發明内容 ' 有鑑於此，本發明之首要目的，係在於縮小記憶胞所 需的面積大小，以降低記憶體裝置之製造成本。 根據上述目的，本發明係提供一非揮發性記憶體。該 非揮發性記憶胞包括一開關裝置以及一第一、第二平板電V. INSTRUCTION STATEMENT α) TECHNICAL FIELD OF THE INVENTION The present invention relates to a plug-in memory cell, which is powered by The <month package' is composed of two plate capacitors within a non-volatile operating range, and the capacitance value of the above-mentioned plate capacitor is a fixed value in the prior art. Non-volatile memory, lacking the ability to store data. Electrical Technology: Loss of Power | 'You can still remember the kind of memory in the memory, = The type of memory (EEP_) is non-issued or written by the memory cell = an electronic signal to write data into the memory cell: The pole's knot' and the float of the layer-by-layer polycrystal 1 = store the charge with the write of the memory. U.S. Patent No. 6,191,980 discloses an EEPR(R) M memory cell as shown in Figure 1. The memory cell 100 includes a PMOS transistor MCI, a -NMQS transistor M2, and a wiper layer, and shares a layer of polysilicon gates 2〇6. And in order to increase the coupling between the control gate and the floating gate, a capacitor c丨 may be further included. However, the program and erase of the EEPR〇M 5 memory cell are operated using a crystal structure. For example, a memory cell will have both a p well region and an N well region. The size of the memory cells is large and increases the need for area. SUMMARY OF THE INVENTION In view of the above, the primary object of the present invention is to reduce the size of the area required for memory cells to reduce the manufacturing cost of the memory device. In accordance with the above objects, the present invention provides a non-volatile memory. The non-volatile memory cell includes a switching device and a first and second tablet
0516-A40024twf(nl);denni s.ptd 第6頁 五、發明說叼（2) ΐ具：闕J置係設置於-基板上，第―、第 電容係共用乃二；雜區。開闕裝置與ί:平；電；f 性記憶皰< _ ^日日石夕夺置間極，以儲存電# # A I接^ 接面崩=寫心並且在不導致該子：：作為该非揮發 〶之下，藉由 揮I性記憶胞内任何 ?unne“w，來抹挣:/;/雜區與該浮置閘極間之随通 第-摻雜區係在多 二_揮發性記憶胞。此外，第一、 中’使得在-操作=洋置閉極形成之前，形成於該基板 容值係為固定值。&之下，该第一、第二平板電容之電 根據上述目的，太 方法，首先，於一其4 I明提供一非揮發性記憶體之製造 第二元件區。接菩上疋義出一第一主動區與一第一及 -第-、第二重摻雜摻：該第-及第二元件區’以成形 -、第二重摻雜區2第然=形成-浮置閑極於該第 與該第'重摻# F 動區之上，其中該浮置閘極 與該第二重捧第第：：板電，，並且該浮置間極 閘極為罩幕，對，2 弟一平板電容。最後，以該浮置 及-源極區，二：一主動區進行摻雜’以形成，汲極區 -垂仏 化成—開關電晶體，直中拟士呤笫一、第 電容之電容值係為固^電堡範圍内，該第一、第二平板 為讓本發明之p # n ^ 下文特舉一較佳每的、特徵及優點能更明顯易懂， 下： 只也例，並配合所附圖式，作詳細說明如 貫施方式0516-A40024twf(nl);denni s.ptd Page 6 5. Inventive 叼(2) Cookware: 阙J is placed on the substrate, the first and the first capacitors are shared; Open the device with ί: flat; electricity; f sex memory blister < _ ^ day and night stone eve with the pole, to store electricity # # AI connect ^ junction surface collapse = write heart and does not lead to the child ::: as Under the non-volatile enthalpy, by using any ?unne "w in the memory of the memory, it is smeared: /; / the inter-doped region between the miscellaneous region and the floating gate is more than two Volatile memory cells. In addition, the first, middle, and the substrate are formed at a fixed value before the operation of the ocean is closed. Under the device, the first and second plate capacitors are electrically charged. According to the above object, the method is first, in the first step, to provide a non-volatile memory for the manufacture of the second component region, and to connect the first active region with a first and - the first and the first Double-doping doping: the first and second element regions 'formed-, the second heavily doped region 2 is first = formed - floating idler above the first and the 're-doped regions Wherein the floating gate is electrically connected to the second repetitive:::, and the floating pole gate is extremely shielded, right, 2 brothers, a plate capacitor. Finally, the floating and - source District, two: one master The region is doped to form, the drain region is formed into a switching transistor, and the capacitance value of the straight capacitor is the range of the solid capacitor, and the first and second plates are Let p #n ^ of the present invention be more specifically described, features, and advantages will be more apparent, and the following:
0516-A40024twf(nl)；dennis.ptd 第7頁 1252488 一1丨丨丨" 1 _ 五、發明說明（3) /第2圖係為本發明之非揮發性記憶胞的示意圖，而 圖係為本發明之非揮發性記憶胞之結構圖。如圖中所示， 本發明之非揮發性記憶胞包括一開關裝置们丨及一第」、， 第二平板電容CU、C12。於本例巾，開關裝置MU係 一_s電晶體’設置於一基板丨丨之上。開關裝置m界 極！9與汲極21係藉由接點P3、P4電性連到接地和位原 BL。第一、第二平板電容C11、C12，係分別具有一、—、 第二摻雜區12、14。第二平板電容之第二摻雜區14(下 極）係藉由接點P2耦接至字元線WL。 開關裝置Mil與第一、第二平板電容⑺心係共用_0516-A40024twf(nl);dennis.ptd Page 7 1252488 一一丨丨丨" 1 _ 5, invention description (3) / 2 is a schematic diagram of the non-volatile memory cell of the present invention, and the diagram It is a structural diagram of the non-volatile memory cell of the present invention. As shown in the figure, the non-volatile memory cell of the present invention includes a switching device and a second panel capacitor CU, C12. In the case of the present invention, the switching device MU is disposed on a substrate 一. Switching device m boundary! 9 and the bungee 21 are electrically connected to the ground and the original BL by the contacts P3 and P4. The first and second panel capacitors C11 and C12 respectively have one, — and second doping regions 12 and 14. The second doped region 14 (lower) of the second plate capacitor is coupled to the word line WL by a contact P2. The switching device Mil is shared with the first and second plate capacitors (7) _
:㊁：洋二閘J16，以儲存電荷作為該非揮發性記憶_ f寫入，並且在不導致該非揮發性記憶胞1〇内任何接面 :貝之下’藉由第一摻雜區12與多晶石夕浮置問極i6 J (tUrmeling)，來抹狳該非揮發性記憶胞ι〇。此外， :成12、14係在多晶矽浮置閘極16形成之前， 形成於基板11中，使得在一操作電壓範圍之内， 、 二平板電容Cll 'C12之電容值係為固定值。於本發明中， ΪΓ:電壓範圍内之電壓係用以執行記憶胞之寫：、讀取 謝卩'憶胞Γ中係藉由熱載子注入來寫入資料，並藉由 作rh广)随通(tunnellng)來抹除資料。在記 的刼作上，係施加一大約4〜1〇伏特的 =，至=請U…和第二平板電容C12:第：摻 雜£14，並同日寸將開關裝置M11之源極和第—平板電容⑴ 第8頁 0516-A40024twf(nl);dennis.ptd 1252488 五、發明說明（4) 之第一摻雜區12保持在接地電 入。此時，會產生埶載子、、主，末進仃s己憶胞10之寫 另外，#鋅W 到輕接的浮置閘極中。 係猎由施加一大約丨〇伏 斤 容Cl 1之第一摻雜區12，同 、壯一 i至弟一平板電 和第二平板電容Π 2之第—#雜;J衣置M1 1之汲極與源極 進行記憶胞Η之抹除二二气2第， 生隨通(tunneHng)，使得電子…閘4 ⑽s ^圖^之習知__記憶胞係使用電晶體結構 容广、來操作。第4a圖係表示第1圖中_電 情Λ 由細st容器具有通道，所以在記 作中，M0S電容器MC1、M3的電容值會根據跨在： -上ϋ所變化，並不會保持固定。當M〇s電容、 :上之電£Vc接近於其臨界電壓時，其通道中會產生 層，故MOS電容器之等效電容值會下降，如第则中所轉 :壓^二在^胞不論是要用以寫入、抹除或讀取的操作 電黡祀圍Vop内，M0S電容器之等效電容值是變動的。 另外，第4c圖係表示第i圖中電容器C1的結構’由 電f器C1係由一覆晶石夕層pc、其下方之p井區及其間的氧 |b層1構成。但是當電容_上之電壓以超過於一臨 壓Vt時，其在P井區中會產生—空乏區，故電容抑之電 2容值會下降，如第㈣中所示。由於一般來抑井區 通吊不是重摻雜，故造成空乏區之臨界電壓η仍會位於 憶胞之刼作電壓範圍内。因&，同樣地在記憶胞的操作電: 2: Yang Erzhan J16, writes the charge as the non-volatile memory _ f, and does not cause any junction in the non-volatile memory cell 1:: under the first doping region 12 and more The spar is floating on the i6 J (tUrmeling) to wipe out the non-volatile memory cell. Further, the steps 12 and 14 are formed in the substrate 11 before the polysilicon floating gate 16 is formed, so that the capacitance value of the two plate capacitors C11 'C12 is a fixed value within an operating voltage range. In the present invention, ΪΓ: the voltage within the voltage range is used to perform the writing of the memory cell: reading Xie Yu's memory cell is written by hot carrier injection, and is made by rh. With the help of (tunnellng) to erase the data. In the note, a voltage of about 4~1 volts is applied, to = please U... and the second plate capacitor C12: the first: doped with £14, and the same day will be the source of the switch device M11 and the first —Slab Capacitor (1) Page 8 0516-A40024twf (nl); dennis.ptd 1252488 5. The first doping region 12 of the invention description (4) is maintained at grounding. At this time, the 埶 carrier, the main, and the last 仃 己 忆 忆 10 另外 另外 另外 另外 另外 另外 另外 另外 另外 另外 另外 另外 另外 另外 另外 另外 另外 另外 另外 另外 另外 另外 另外 另外The first doping area 12 is applied by applying a 丨〇 斤 容 Cl Cl , , , , , , , , , , , , , — — ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; The bungee and the source perform the memory cell annihilation of the second and second gas 2, and the tongneHng, so that the electronic ... gate 4 (10) s ^ map ^ _ _ _ memory cell system using a wide crystal structure, operating. Figure 4a shows the _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ . When the M〇s capacitor, the voltage on the VV is close to its threshold voltage, a layer will be formed in the channel, so the equivalent capacitance value of the MOS capacitor will decrease, as in the second step: The equivalent capacitance of the M0S capacitor is variable whether it is used to write, erase or read the operating capacitor Vop. Further, Fig. 4c shows that the structure 'of the capacitor C1 in Fig. i' is composed of a ferrite C1, a p-well layer below it, and an oxygen|b layer 1 therebetween. However, when the voltage on the capacitor_ exceeds a voltage Vt, it will generate a depletion region in the P-well region, so the capacitance of the capacitor will decrease, as shown in the fourth panel. Since the general suppression zone is not heavily doped, the threshold voltage η of the depletion zone will still be within the voltage range of the cell. Because &, the same in the operation of the memory cell
1252488 五、發明說明（5) 壓範圍Vop内，m〇S電容器之等效電容值也是會變動的。 然而’於本發明中記憶胞係使用平板電容C11、C1 2來 細作’並且平板電容C1 1、c 1 2之下電極（1 2、1 4 )係由重摻 雜區（N+)所構成，如第4e圖中所示。由於重摻雜區（11 + )作 為平板電谷Cll、C12之下電極，故要在重摻雜區（n+)中產 生空之區而造成電容值的變化，需要施加很大的負電壓在 $板電容的兩端，此負電壓Vc將會超出記憶胞的操作電壓 fe圍Vop之外。因此，平板電容在記憶胞之操作電壓範圍 \〇P内，本發明之平板電容cn、Π2的電容值並不會有所 變化，而會保持固定值，如第4f圖中所示。所以，如第i 圖中所不之兄憶胞中的電容$C1以及M〇s電容器mci、们並 不符合本發明中所定義之平板電容cn、Π2。 ，外，若第i圖中之電容器C1以及_電容器·、 的電=之操作電壓範圍内’達到與本發明同樣 , 』、丄 只j 乂 y貝要加大其尺寸，故其面積會辦 “作而：力:。☆本發明中記憶胞係由平板電容： =小：：：用體：rr之記憶胞僅需 5a〜5c圖中所示。首先非於揮ϋ記憶胞之製造方法，如第 18與一第一及第二元件、。土反/上定義出一第一主動區 件區，以成形一第_、η: ’重摻雜該第-及第二元 所示。 弟一重摻雜區12、14，如第5a圖中 然後，於第一、篦-舌协〜 一 払雜區12、14與第一主動區181252488 V. INSTRUCTIONS (5) Within the voltage range Vop, the equivalent capacitance of the m〇S capacitor also varies. However, in the present invention, the memory cell system is made fine by using the plate capacitors C11 and C1 2 and the electrodes (1 2, 14) under the plate capacitors C1 1 and c 1 2 are composed of a heavily doped region (N+). As shown in Figure 4e. Since the heavily doped region (11 + ) is used as the electrode under the plate electric valleys C11 and C12, an empty region is generated in the heavily doped region (n+) to cause a change in the capacitance value, and a large negative voltage needs to be applied. At both ends of the board capacitor, this negative voltage Vc will exceed the operating voltage of the memory cell outside the Vop. Therefore, in the operating voltage range \〇P of the memory cell, the capacitance values of the panel capacitors cn and Π2 of the present invention do not change, but maintain a fixed value, as shown in Fig. 4f. Therefore, the capacitance $C1 and the M〇s capacitor mci in the brother cell of the figure i are not in accordance with the plate capacitances cn and Π2 defined in the present invention. In addition, if the voltages of the capacitors C1 and _capacitors in the figure i are within the operating voltage range of the present invention, the size of the capacitors is the same as that of the present invention, and the size of the capacitors is increased. "Working: Force: ☆ In the present invention, the memory cell is made up of a plate capacitor: = small::: user: rr memory cell only needs to be shown in the figure 5a~5c. First of all, the method of manufacturing the memory cell For example, the first active component region is defined by the first and second components, and the first active component region is formed to form a first _, η: 'heavially doped first and second elements. a heavily doped region 12, 14, as in Figure 5a, then, in the first, 篦-tongue association ~ a doping region 12, 14 and the first active region 18
0516-A40024twf(nl);denni s.ptd i^· 第ίο頁 1252488 五、發明說明（6) 之上，形成一多晶矽浮 一重摻雜區12及其間 6。多晶矽浮置閘極16與第 板電容CU，並且多晶/浮乳化層（未顯示）構成一第一平 間之閘極氧化層（未1"到6與第二重摻雜區1 4其 5b圖中所示。其中形成7^亥f 了 =二平板電容C12，如第 在操作電壓範圍（例如、弟二重摻雜區12、14使得 谷之，容值係不會改變而為固定之值内。，弟一、第二平板電 進行摻雜，以形為罩幕，對第一主動區18 關電晶體MU，如第5(；圖;^9_及。—源極區2卜以形成一開 雖然本發明已以較佳容 限制本發日月，任何熟習此；技“I:露：上，、然其並非用以 神和範圍内，當可做更動盥潤二 不脫離本發明之精 當事後附之申請專利範圍;斤界定者=^本發明之保護範圍 $ 11頁 °516-A4〇〇24twf(nl);dennis.ptd 1252488 圖式簡單說明 第1圖係為一習知EEPROM記憶胞之示意圖。 第2圖係為本發明之非揮發性記憶胞的示意圖。 第3圖係為本發明之非揮發性記憶胞之結構圖。 第4a圖係表示第1圖中MOS電容器MCI 、M3的結構。 第4b圖係顯示第4a圖中MOS電容器之CV曲線。 第4c圖係表示第1圖中電容器C 1的結構。 第4d圖係顯示第4c圖中電容器C1之CV曲線。 第4 e圖係表示本發明中平板電容的結構。 第4 f圖係顯示本發明中平板電容器之CV曲線。 第5 a〜5 c圖係為本發明之記憶胞製造流程圖。 符號說明 習知技術0516-A40024twf(nl);denni s.ptd i^· 第ίο 1252488 5. On the invention description (6), a polycrystalline germanium is formed, a heavily doped region 12 and a space therebetween. The polysilicon floating gate 16 and the first plate capacitor CU, and the polycrystalline/floating emulsion layer (not shown) constitutes a first flat gate oxide layer (not 1 " to 6 and the second heavily doped region 14 4b As shown in the figure, the formation of 7 ^ hai = = two plate capacitor C12, as in the operating voltage range (for example, the second doped regions 12, 14 so that the valley, the capacitance will not change and is fixed Within the value., the first one, the second plate is doped to form a mask, and the first active region 18 is turned off by the transistor MU, such as the fifth (; Figure; ^9_ and . - source region 2 In order to form an opening, although the present invention has been limited by the present invention, it is familiar with this; the technique "I: dew: on, but it is not used in the scope of the gods, when it can be changed, it does not deviate from the present. The scope of the invention is attached to the patent application; the definition of the kg = ^ the protection scope of the invention $ 11 pages ° 516-A4 〇〇 24 twf (nl); dennis.ptd 1252488 The simple description of the diagram Figure 1 is a A schematic diagram of an EEPROM memory cell. Fig. 2 is a schematic diagram of a non-volatile memory cell of the present invention. Fig. 3 is a non-volatile memory cell of the present invention. Fig. 4a shows the structure of the MOS capacitors MCI and M3 in Fig. 1. Fig. 4b shows the CV curve of the MOS capacitor in Fig. 4a, and Fig. 4c shows the structure of the capacitor C1 in Fig. 1. The 4d diagram shows the CV curve of the capacitor C1 in Fig. 4c. Fig. 4e shows the structure of the panel capacitor in the present invention. Fig. 4f shows the CV curve of the panel capacitor in the present invention. 5a~5c The invention is a memory cell manufacturing flow chart of the present invention.
MCI :MOS 電 晶 體； M2 : NMOS 電 晶 體； M3 : 抹除 裝 置 206 :多晶矽閘極； C1 ： :電容 器 1 本發明 10 記憶 胞 ； 11 基板 12 第一 摻 雜 區， 14 第二 摻 雜 區， 16 多晶 矽 浮 置閘極； 18 第一 主 動 區； 0516-A40024twf(nl);dennis.ptd 第12頁 1252488MCI: MOS transistor; M2: NMOS transistor; M3: erasing device 206: polysilicon gate; C1: : capacitor 1 10 memory cells of the invention; 11 substrate 12 first doped region, 14 second doped region, 16 polysilicon floating gate; 18 first active region; 0516-A40024twf(nl); dennis.ptd page 12 1252488
0516-A40024twf(nl);denni s.ptd 第13頁0516-A40024twf(nl);denni s.ptd第13页