TW490859B - Methods of reading and writing data from/on semiconductor memory device, and method for driving the device - Google Patents

Abstract

In a semiconductor memory device in which a ferroelectric capacitor is connected to the gate of a field effect transistor (FET), a gate charge at the threshold voltage (Vti) of the FET is represented as Qti. In a polarization-voltage characteristic exhibited by the ferroelectric capacitor where a voltage applied thereto starts to be increased on the supposition that a polarization of 0 C/cm<SP>2</SP> initially exists in the capacitor, a voltage, associated with a polarization value corresponding to Qti, is represented as Vtf. In a read operation, the intersection between the gate charge-gate voltage characteristic of the FET and the polarization-voltage characteristic of the ferroelectric capacitor is the operating point where, a worst-case polarization of 0 C/cm<SP>2</SP> exists in the capacitor after data has been retained in the capacitor. By applying a voltage Vtf+Vth to the control electrode, the data can be read out correctly until the polarization decreases to reach 0 C/cm<SP>2</SP>.

Description

490859 __Case No. 90105477_Yan Zhengwu 5. Description of the invention (1) [Background of the invention] The present invention relates to a non-volatile method of connecting a ferroelectric capacitor in series to a field effect transistor (FET) gate. Sexual memory element. A ferroelectric FET (FeFET) is a combination of a ferroelectric and a nonvolatile memory element of a FET. The structure of this element can be roughly divided into MFS type

FeFET, MFIS type FeFET, MFMIS type FeFET ° MFS refers to Metal (Metal) / Ferroelectric (Ferroelectric) / Semiconductor (semiconductor) ° MFIS refers to Metal (Metal) / Ferroelectric (Ferroelectric) / Insulator (Insulator ) / Semiconductor (half

conductor). In addition, MFMIS-type FeFET means Metal /

Ferroelectric (Metal) / Me ta 1 (Metal) / I nsu i a tor (Insulator) / Semiconductor (Semiconductor). FIG. 9 is a cross-sectional structure diagram showing the structure of an MFMIS-type FeFET. As shown in FIG. 9, on a P-type silicon (hereinafter, referred to as si) substrate 31, the MFMIS-type FeFET includes a high-concentration n-type implanted region 32 serving as a drain electrode and a high-concentration n-type implant serving as a source electrode. The entrance region 33 is formed by forming an insulator 34, a drift gate voltage 35, a ferroelectric 36, a control electrode 37, and the like. A ferroelectric capacitor is formed on the drift gate voltage 35 of the FET, and the electrode of the ferroelectric capacitor and the gate electrode of the FET are common. Meanwhile, with

The structure that connects the electrode of the ferroelectric capacitor with the gate electrode of the FET is also a type of MFMIS FeFET. Next, the operation of the non-volatile memory element as an MFMIS-type FeFET will be described. When changing the sign of the control gate voltage (Vg) value, in this way,

490859

Reverse. Here, it is defined that a positive voltage is applied to Vg and a negative voltage is applied to Vg to write the polarization direction of the ferroelectric, and thus Vg is written to the data "i" and "0". Even if the control electrode is floated, the polarization value is maintained (residual polarization). When the data is read, keep the control electrode floating ', because the leakage caused by the resistance component, the capacitive coupling with the wiring &amp; and the potential close to the ground potential) t state, the source / electricity by iron Residual polarization of the capacitor, one of fet or negative. If the potential of the drift electrode is =====: = 成, the state of the current is: ϊί 值 = 间 的 电流 值 ⑽) and preliminary = ㈡1, if Ids &lt; f, it is defined as written The information was read correctly. J 疋 yi is lean material "0" ', then (8ΓΒΓτ! 〇7 &quot; j ^ ^ ^ ^

UrB ^ TaA), and for the insulator, the operation performance of these MFMIS-type FeFETs is proposed. Silicon silicon (S102) is shown in Figure 10. It is a special circuit diagram showing the operation of FeFET's MFMIS type FeFET. Use this figure 10 for capacitance, 42 for FET, and 43 for control mine. In Fig. 10, 41 is a ferroelectric electrode. Electrode, 44 is the source electrode, 45 is the drain electrode, each parameter is set to srBi2Ta2, the thickness is 200 dragons, the dielectric is 490859

The unitary number was 300, the coercive voltage * 〇8v no 2ii 3.5 nm, and the dielectric constant was 3.9. In addition, the polarization of the ferroelectric capacitor in the mfmis structure_2 region is Pf, the voltage between the electrodes is Vf, the control voltage is Vg, and the ° charge stored in the gate of the FET in the MIS region of the MFMIS structure is Qi, the voltage of the drain electrode is Vd, the voltage of the drift gate electrode is _ = the voltage of the electrode is ^ = ov, the potential of the substrate is, the cut-off capacitor is cut off, and the threshold of the MIS structure FET is alone For Vti = 0 · 5V 〇0 meaning 'memory unit with electric value such that the following two formulas are true

Pf (Vf)-Qi (Vi) (l) yg = Vf + Vi (2)

Pf (Vf) = Qi (Vg-Vf) (3) holds. Figure 11 Pf vs. Vf characteristics of A-series ferroelectric capacitors (referred to as, circuit). The curve 1 on the lower side represents the value of pf obtained by increasing the voltage, and the curve 2 represents the value obtained by decreasing the voltage. ^ The voltage above the characteristic = 〇C / cm2 is called the withstand voltage (Vc). # IPf Figure 11 β represents the Qi vs. Vi characteristics of the FET by curve 51. The well-known calculation method of M0S capacitor can be easily Calculate. The characteristic is to apply this Qi to the Vi characteristic, and perform a symmetrical fall on the Qi axis. By shifting Vg toward the voltage axis, Qian gets Qiff (Vg ^ ', and if only Pf vs. Vf vs. Qi vs. (Vg _ Vf) characteristics overlap characteristics. Find the intersection point on the drawing. This intersection point indicates the movement of FeFET: two to one

Page 8 490859 _Case No. 90105477 V. Explanation of the invention (4) (3) It can be seen clearly that Vx, Vi = Vg-Vx 〇— 月 日 倏 正 __ Lei Tao at the intersection, whenever Vx is set, Then Vf below two, using the movement through the graph

FeFET operation status. ^ Analytical method to simulate the initial "data" 1 "write operation when a positive voltage (Vg &gt; 〇v) is applied, that is, the control electrode line 52 indicates that the application of Pf to Vf characteristics 1, 2 $ for point analysis . Fig. 12A is a curve (Vg-Vf) characteristic. From FIG. 12A, if the Qi pair at a voltage of 8 to 15V can obtain Vx = 3V, then Vf = 3v, and the voltage value of the parent point 53 is 12V. From the formula (2) ′, then Vi 2 Next, the data “0” is written, and when a negative voltage (Vg &lt; 〇ν) is applied to the data, it is performed on the control electrode.

Pf for m temple i, 2 states = _15df; analysis. Figure 12B shows the applied characteristics.

Vx = -3.5V, so Vf = -3 5V, ± -H.5V holds. From the formula ⑴, when Vi = state, this Vx saves the data in this state, although the control electrode is floating, the voltage drop caused by the leakage of the ferroelectric and FET, and the voltage of each electrode is light. It can be tolerated that the control electrode voltage is almost 0V. Because the control electrode is in a floating state, it is assumed that Vg = ov (vi = Vg _ and -Vx). In Fig. 1, 3 shows the "pair" characteristic of the operating state in the data holding state, 2 and Qi pair (Vg-Vf) characteristic 56. After writing the above-mentioned binary data, the operating point is determined in accordance with the electric hysteresis characteristic of the ferroelectric. That is, by MM, Q〇l 05477 V. Description of the invention (5) Data "1, said correction" The clock in the writing action + 2 Vf in the operation is reduced, the voltage applied to the electricity, belt: mouth body " = 3V, guaranty, the intersection of 56 'becomes the capital, and it is expected that the voltage reduction characteristic of the / 5 channel 2 and the special feature: lean material "0" on the stomach movement action ": hold action point 3. On the other hand, at 3.5V, the voltage applied to the Vf in the holding operation is Vf = the intersection point σ 特性 of characteristic 1 and characteristic 56. The electric fort of the hysteresis loop is increased by Figure 13 because the data is "" 贝 π "0 "Keep action point 4. = -0.8V, then Vf = -〇8ν, ^ The operating point in the holding period is Vx is 〇V in the data "0" holding period, then Vi = 0.8V, because 0.7v, from vg = ov, Then Vi = point is Vx = 〇, n, then Vf = state, because Vi &gt; vth, FET · 7ν. The state of “1” is maintained, because n <Vth, the FET remains in the state of “lean” 0. The last 5V is electrically turned on and the electrode is in a sweat state, and Vd is applied to the drain electrode. (Vi &gt; vth / | ljmH s becomes higher than Yang Zhilin ET to be turned on, and the drain current is combined. On the other hand, if the voltage of the drift electrode is lower than the threshold voltage of the FET "value 1 &lt; Vth), The FET will be turned off, and the drain current will not flow. In this conventional example, because Vi = (K8V is much higher than Vth = 0.5V, which is obtained by analyzing the operating point with the data r 丨 "held in the state, the FeFET can Read the tribute "1". At the same time, because of the state of keeping the data "0"

When the point analysis obtained Vi = —0.7V is far lower than Vth = 0.5V, the FeFET can read the data “0”. In T. Nakamura et al., &Quot; Electrical

Characteristics of MFMIS FET Using STN Films'1,

Page 10 V. Description of the invention (6) r:; :: r; r \:; / i ^ r9r; 57vsDM98 · 208 '. The action simulation previously described assumes Vg g 0: as an example, in which case the same result can be obtained. For _IΪ, for non-volatile memory elements using ferroelectrics, enter # # = make a point change and face the inability to read the data correctly =: = That is, although the poem f keeps the action required ””, The permissible variation of the condition Vi> vth at the time of ON, that is, the write and read operations of electricity: electricity Γ? Ν into f poor Γ1 ”, drift closed pole =: (. There is only &quot; V. Therefore, because the lower part ... W3V, you will not be able to follow the continuity and you will not be able to read the data correctly. Νΐ · &quot; = '° · 7ν, ^ n ni Vl <VU changes The allowable value is 12 ¥. &Quot;: In the state of holding, because the FET is in the data "1" = the number of FeFETs and the electrode connected to the bit line is 5% Hl ° Lu Erjiu has been disclosed in the special Kaiping No. 5-205487 and Special Kaiping: ^ i (both are issued on August 13, 1 993: a / ^ Ϊίϊ transistor is attached to the electrode electrode. Here, we will repeat

ί: When a semiconductor memory device of two Λ and formation is used to detect the read operation of FeFET and second-generation S in # 2, it is necessary to use the other FeFET selected in the state of the transistor to have no pole current, so that the surface S product cannot be imported. The problem of integration. WU859

[Summary of the Invention] In order to solve the above-mentioned problems, the present invention provides a semiconducting method for retaining characteristics dc of a body memory device. The present invention relates to a capacitor composed of a pair of electrodes of a semiconductor memory and a ferroelectric body. The electrode is connected to a gate electrode between the above-mentioned field effect transistors. Let the other capacitor of the above capacitor be the above-mentioned% effect transistor, _ ^ ^ The other electrode on the Elbow River Valley is used as the control electrode, and change the polarization of the ferroelectric body, ^^^ The channel impedance of the effect transistor, because the above-mentioned channel impedance ^ π is low, represents the data readout of the semiconductor memory device of binary data. It is characterized in that if the positive voltage of the field-effect transistor is on the control electrode, if If the above field effect == threshold voltage is negative, a negative voltage is applied to the control electrode. According to the material readout method, a specific voltage (Vread) is applied to the control electrode during the readout operation. The conventional data readout method has a permissible value of 1.2V for the change of turn-off and a change of the turn-on. The allowable value is small, which is 0 3V, which can eliminate the difference between the allowable value of the on and off variations. That is, in order to satisfy the condition Vi &gt; vth at the time of turn-on, the allowable value of variation can be increased, and the retention characteristics can be improved. b. The present invention relates to the above-mentioned data reading method. If the threshold voltage value of the field-effect transistor is positive, the residual polarization value of the capacitor is stored in the library.

Correction code: 9010M77 V. Description of the invention (8) The state of 7 cm² will bring the interfacial electrode Π to the thunder ef which is the value between the above-mentioned field-effect transistors. The charge polarization is added, and the threshold voltage phase KG applied to the above-mentioned 应 electrode should be “voltage I; if the above-mentioned field-effect transistor is near: = the residual polarization value of the capacitor is 0, and the value is the square / square value. Threshold voltage at the time of change "„ Development is reduced to make the polarization: gate ίϋ ί the value of the polarization of the charge induced by the channel: electricity = sum the threshold voltage values of the field effect transistor, add heart The voltage value within ± 20%. It is best to get the polarization value of ㈣m 叙 Λ, cut the 1s MFeFET ferroelectric capacitor's polarization value 2! In the state, use the voltage between the electrodes ⑴) from 0V & amp The characteristic of "overtime Pf pair" and the FETiQi pair are the widest, which is the worst case for reducing bias. The dummy is Pf = 0 Coulomb / square meter ^ ^ read voltage. As a result, while the data U ”keeps moving, the value is reduced, and the FET must be turned on to reach Pf = the data can be read correctly. Also, consider the accuracy of the readout voltage ™ applied to the control electrode: ^ and the bias of the polarized non-masked stack offset, the inaccuracy of the degree = the inaccuracy of the degree, the inaccuracy of the ion implantation Accurate on page 13 is a correction of the difference 90105477_Fifth, the description of the invention (9) the impact of sex, damage, etc., plus the 15% ^ r〇 / inaccuracy to set the polarization of the ferroelectric The value is not tangible, due to the ± 5% method :: For the month, there is information about the semiconductor memory device written into the cube. Group: Iron 'body: the capacitor formed, and the gate electrode of the field effect transistor. Valley: The electrode is connected to the free-electrode of the above field-effect transistor, and the above-mentioned capacitor is recorded as the above-mentioned field-effect polarization: ::? The control electrode changes the channel impedance of the above-mentioned ferroelectric's off-channel impedance field-effect transistor. Because the above access method shows: the value of the semiconductor memory device data is written and the voltage is applied. In the non-conducting state, the state of the field effect transistor is within the range of C. According to the data writing method, the FET is turned off in each of the holding states where the data current is turned on, and the driving method of the memory device is drawn. Its characteristic data is based on the data writing method of the conductor memory device. The driver drives Fang to apply a reset voltage to the above control electrode. Operation method '☆ After the data writing operation, it will be moved to the holding position immediately. I 本 i According to the above-mentioned data writing method of the present invention, data writing and memory are performed. When the device reads its data, the control electrode above, +, and ia I ΐ I should preferably apply a positive voltage to the above, the% effect transistor above the threshold voltage value

Page 14 Month Amendment Collection 90105477 V. The voltage of the invention (10); and under the above-mentioned field effect, the application of negative electricity is negative to the above control electrode, and the monthly condition f applies a voltage higher than the threshold electrical migration value. According to the information; _, when reading, if the data is kept f "state: guide = off =" 〇 "is the closing action, the data K can be correctly made ... The electrode is connected to the PW * of the heart, and the electrode is connected to the control electrode. The above-mentioned second field-effect voltage is: the first and second electrodes are connected to the first word line, and the drain electrode is connected to the second word. Column. Therefore, even if the selection of the transistor is omitted between the drain electrode / bit line (or between the source line and the sub-line), the shell can be accurately extracted, and the degree of accumulation can be improved. # μ, according to the invention described above, not only can the allowable values of the read and voltage k movements of the FeFET be changed, but also the polarization polarization of the ferroelectric capacitor can be changed. Even in the worst case, the polarization polarization Become Coulomb / square square ", and can still read correctly. At the same time, the selection transistor between the drain electrode and the bit line can be omitted. [Detailed description of the embodiment] The embodiment of the present invention will be described with reference to the drawings. C. Embodiment 1) Page 15 490859

The semiconductor memory device of Example 1 of palladium and palladium will be described with reference to FIG. 9: the structure of the conventional and conventional technologies is the same, and its equivalent circuit diagram is the same as that of FIG. 1M. At the same time, the writing and holding actions are also the same as the conventional techniques. In the first embodiment of the present invention, the difference between the FeFET and the known FeFET is the method of setting the drive voltage Vread during the read operation. That is, if the threshold voltage value vth of the field effect transistor is positive, then by applying a positive voltage = control electrode, if the threshold voltage value vth of the field effect transistor is negative, then by applying a negative voltage to the control electrode , Set the drive voltage value Vread. Here, if the threshold voltage value Vth of the field effect transistor is positive, a voltage of Vg = 0.5 V is applied to the control electrode to perform a read operation. At this time, due to the reading operation of the data "1", I ds increases accordingly. Because it has the same FeFET structure as the conventional example, the electrode area of the ferroelectric capacitor is 2.8 / zm X 2 · 8 // for the FeFET fabricated with the following specifications. The gate length of the m FET is 0 · 8 / / m, the gate width is 4 # m, and I ds is used as an index for performance evaluation. Figure 1 shows the relationship between the I d s ratio (on / off ratio) and Vg of the data "1" and the data "0". Conventional driving method (Vg = 〇V)

At this time, the intersection point a and the I ds ratio are 104 as shown in FIG. 1. Regarding this, according to Example 1 (Vg = 0.5 V), as shown in the intersection point b shown in FIG. 1, the Ids ratio is 5 X 1 0.5 °, that is, when a voltage of 0.5 V is applied to the control electrode, the initial stage The I ds ratio is 50 times. This sample was left at room temperature for a long time to investigate the change in I ds. As a result, the I ds of the data “1” will be reduced to about the same after being left for 106 seconds.

Page 16 Case No. 90105477 V. Description of the invention (12) 1/10 of the value. However, since the Ids at the initial stage are better known, the lifespan up to the abnormal operation is longer than the conventional drive. Next, the same method as in the conventional example was used to simulate the operation of this embodiment, and its validity was verified. The start-up movement and the holding movement are the same as the conventional technique, and the same movement is performed as shown in Figure T, Figure 11B, Figure 12A, Figure 12B, and Figure 13;情 # Γ1 ”sentiment = 4 intersection point 3 shown in FIG. 13 and the case of data“ 〇 ”is shown in figure u. ^ 二 ^ 二 &amp; For example, use FIG. 2 to explain about Two =: 2 and two 2: 1 are Pf obtained by increasing the voltage of the ferroelectric capacitor: .3 Λ 'j 疋 "P f obtained by reducing the voltage of the ferroelectric capacitor is particularly responsive to V f; V / , "1" is the expected operating point; 4 is the data% reserve 6 =. … Tochi no Kou (Vg-Vf) ί times material 7 = start at point 3 ′ Pd vs. Vf characteristic when increasing voltage; 7 is:. The action points that were identified; 8 are the action cows that read out the data "0", H. The positive voltage of the setting side of the drive test ead during the read operation of Example 1 is positive, and the read action is positive. For example, as shown in FIG. 2, when the control electrode is applied, as shown in FIG. 2, under the application of Vg = 0.5V, the data factory is read out. The voltage is increased from Vg ~ 0v in the holding state. / Pair v ?: The operating point 4 is at the reason of the characteristics of Ugawa, U, obtained by increasing the voltage of the ferroelectric capacitor, Pf,

V. Description of Invention (13)

Vf) The father point of characteristic 5 is the data "0" read operation point 8. From FIG. 2, since the operating point 8 can read vx = 〇 · 8ν, vf = — vx = ~ 〇.8V, Vi = Vg ~ Vx = — 〇 3V. Next, "When the lean material" j "reads the action, the data r 丨" keeps the operating point 3 at the pf vs. vf characteristic 2 obtained by reducing the voltage of the ferroelectric capacitance. "Starting from the operating point 3, increasing For voltage, the Pf vs. Vf characteristic of the ferroelectric capacitor has to be determined. In this way, the behavior of the ferroelectric body when changing the voltage "starting from the state of the hysteresis loop below the saturation polarization value (Ps)" is described in S.L. Mierer et al., Mode 1ing ferroe 1 ectric capacitor switching with asymmetric nonperiodic input signals and arbitrary initial conditions ", as explained in Journal 〇f Appiied Physics, 70 (5), pp · 2849-2860, Sep · 1991. Using the method of M l 1 1 er et al. The polarization value is set to Psat (Psat is actually the same as the polarization value P f that has been discussed so far), and the polarization value inside the saturated hysteresis loop is set to P d (bias When the polarization value is inside the saturated hysteresis loop, it is called Pd for the purpose of distinguishing it from Psat, and the partial differential of the constant r to the electric field E applied to the ferroelectric is expressed by Equation (4). D? Dd E = Γ · d Psat / d E (4) Here, Γ can be obtained by equation (5). However, if the voltage increases, f = +1; if the voltage decreases, f -1. Γ = 1 -tanh [{(Pd-Psat) / (f · Ps-Pd)} i / 2] (5) Using this method of M i 11 er and others, find out from 3 point for start, increase

Page 18

490859 fix

Case No. 90105477 V. Description of the invention (14) The characteristics of Pd vs. Vf during application of voltage and voltage are the characteristics of Qi pair (Vg-Vf) of the FET in Figure 2 For the data "1 ^ as T. From Figure 2, Vx can be read out at action point 7: 4VU buy out ... Vx = 0.4V, Vi = Vg _ νχ = uv. Therefore, Vf because the FET is turned on The allowable value of the readout under the condition ㈣nm, 1 ″ becomes Vi _ _ 09, = 0.4V. That is, compared with the data of the conventional reading method ri.: 5V = allowable value G.3V, the allowable value of variation can only be increased by o.1V. At the same time, the change in the reading of the data "〇" due to the condition that the FET is turned off ^: becomes Vth_Vi = 0.5V-(-〇 · 3ν) = 0.8V. The value is so. Although the permissible variation of the conduction (0.3 V) is much smaller than the permissible variation of the closed U. 2 V), it can be read by applying Vg = 0.5 V, and the permissible variation of the conduction can be enlarged. In addition, a FeFET that is completely suitable for holding characteristics can be provided. Also, the first embodiment of the present invention uses a Vth = 0.5V iN channel FET, which is read by applying a voltage of the control electrode Vg = 0.5V. For example, in the case of a Vth &lt; 0V empty N-channel FET, it is understandable that the permissible variation value of the turn-off is smaller than the permissible variation value of the on-state according to the discussion so far. In this case, the allowable value of the variation of the shutdown can be increased by the negative voltage (Vg &lt; OV) applied to the control electrode. The same applies to p-channel FETs. (Embodiment 2) A semiconductor memory device according to Embodiment 2 of the present invention, and a conventional example and implementation

Page 19 490859 ---- Case No. 90105477 V. Description of Invention (15)

The structure of the first embodiment is the same as that of the equivalent circuit diagram. At the same time, the writing operation is the same as in the conventional example and the first embodiment. One hold ^ The difference between the second embodiment of the present invention and the first embodiment is that the setting method of the drive voltage MVread at each read operation is the second of the FET: Example 1, when Vth is positive, by applying The positive voltage is at the control electrode and ^ voltage = output action. The characteristic of the embodiment 2 is further the best setting method for reading the dynamic protection application = the voltage value Vread at the control electrode. Also, the voltage value Vread applied to the control electrode, if the field-effect transistor # / thus the voltage value Vth is positive, the residual polarization value of the capacitor is 0, and the voltage between the electrodes is changed. Increased from 0v, so that the threshold voltage vti when the time polarization value is changed is applied to the gate electrode of the field effect transistor, so that between the electrodes that generate the polarization value corresponding to the charge induced by the channel The voltage value is added to the threshold voltage value of the above-mentioned field effect transistor, and the obtained voltage value is a voltage value within the center ± 20%. At the same time, the applied force is the voltage value Vread of the control electrode. If the threshold voltage of the field effect transistor = the value Vth is negative, the residual polarization value of the capacitor described above will be 0 coulomb / square knife. When the inter-electrode voltage is reduced from 0V, and the polarization value is changed, the threshold voltage vth of the day guard is applied to the gate electrode of the above-mentioned field-effect transistor, so that a charge equivalent to that induced by the channel is generated. The voltage value between the electrodes and the threshold voltage value of the field effect transistor are added together, and the obtained voltage value is a voltage value within 20% of the center soil. 3A to 3C are used to explain the voltage setting method of the read operation according to the second embodiment of the present invention. The polarization value of the 21 series ferroelectric capacitor in Figure 3A is 0 coulomb / square centimeter.

Observation 59 --- 9010547J-^^ month day Article _ V. Description of the invention (16) '-The state of the minute starts, and the Pd_Vf characteristic when it increases. When the polarization value of the ferroelectric capacitance region of the FeFET is reduced during the holding operation, the worst case is when the polarization reaches a state of 0 Coulomb / cm 2. Figure 21 shows the characteristics of Pd vs. Vf from the ferroelectric capacitor region, starting from the state of 0C / cm2. The characteristic of Pd vs. Vf can be obtained from the ferroelectric capacitor region. Figure 3B. The characteristic of Vi. In this characteristic 22, the charge at the threshold voltage value (Vth = 0.5V) is set to Qti (= 〇2 Coulomb / cm 2). For the ferroelectric capacitor, it is obtained from 21 of Figure 3 The voltage value of the polarization value equal to this Qti can be obtained, and the voltage value is set to vtf (= 0.05V).

In the second embodiment, a voltage value obtained by Vread = Vtf + Vth = 0.05V + G. 5V = 0.55 V is applied to the control electrode to perform a read operation. The values of Vtf and Vth take into account the inaccuracy of the threshold voltage and the polarization. Because the inaccuracy of Vth is ± 15%, the inaccuracy of Vread is about ± 20%. At this time, 0.00475v <Vtf &lt; 〇5255v, 〇425v &lt;

Vth &lt; 0. 575V was established. Curve 23 in Fig. 3C shows the characteristics of the Qi pair (Vg-vf) of the FET with vg = Vread applied to this readout. That is to say, Fig. 3C shows the case where the state of the operation at the time of readout \ operation \ operation is started from the state of polarization of 0 Coulomb / cm 2. According to this method, starting from the state of polarized Q Coulomb / square A knife, the point where the μ pair η characteristic 21 and the Qi pair (Vg-Vf) characteristic 23 of the FET at the time of increasing the voltage are applied to the FET drift Gate voltage, the voltage Vi is the threshold voltage value vth (Vi = vth). Here, it is assumed that the operating point in the worst case is ^ = Vx〇 (= vtf).

490859 __Case No. 90105477_ 年月 月 __ V. Description of the invention (17) If it is far greater than the worst case of polarization (Pd &gt; 0 Coulomb / cm²), then Pd vs. Vf when reading Because the characteristic is on the upper side than 21 in FIG. 3C, the intersection point with the characteristic 23 of the Qi pair (Vg-Vf) of the FET is on the left of the parent figure 2C in FIG. 3C. If the voltage at the intersection is assumed to be yx 1, then 1 &lt;

VxO. Therefore, Vi 2 Vread-Vxl = Vtf + Vth-Vxl =

VxO + Vth-VX1 &gt; Vti is established, satisfying the conditions when the FET is on Vi &gt; V th 〇 If it is far less than the worst case of polarization (Pd <〇 Coulomb / cm 2) ' Because the Pd vs. Vf characteristic is lower than 21 of FIG. 3C, the intersection with the Qi pair (Vg-Vf) characteristic 23 of the FET is further to the right than 21 of FIG. 3C. If the voltage at the intersection is assumed to be Vx2, then ^ 2 &gt;

VxO. Therefore, Vi = Vread — Vx2 = Vtf + Vth ~ =

VxO + Vth-Vx2 &lt; Vth is established and Vi &lt; V ti ° is satisfied when the FET is turned off. As a result, when the reading operation is performed by the method of the second embodiment, if the control electrode voltage is set to Vread, and if Even if the polarization value is changed more than the worst case (Pd &gt; 〇C / cm2), the condition "Vi" &gt; vth when the FET is turned on must be satisfied to read the data "1" correctly. Similarly, if the polarization value is smaller than the worst case even if it changes (pd &lt; 〇 Coulomb / cm 2), the condition Vi &lt;

Vth 'can read the data "〇" correctly. In addition, the second embodiment is used to explain an n-channel FET with Vth = 0.5V. For example, in the case of the vth &lt; 〇ViP channel FET, the figure "from the state of polarization polarization 0 C / cm2, pd pair when voltage is reduced" is used.

Page 22 490859 Amendment No. 90〗 Dian 477 V. Description of the Invention (18) Property 24, Q ^ Vi characteristic of the FET shown in the figure 25 is the same as the above method, and the best Vread can be obtained. The same applies to the empty N-channel FET. (Embodiment 3) In the writing operation known at 1 | ', with a large voltage applied to the control electrode Vg = 157 ^ ^, even in the state where no voltage is applied, the ferroelectric body is flat-polarized. Current flows between the source / drain. In the control electrode of the writing operation of Example 3, although the voltage value Vg of the control electrode is applied to the control electrode, there is no applied voltage state after the voltage is applied. The upper% effect transistor is in a non-conducting voltage value. Range 2. According to this composition, the "small write voltage is applied to the gate electrode potential v of the field-effect transistor by applying a voltage value in a non-conducting state, and each of the two" / "and the data" 0 "is maintained In the state, the FET is turned off and the drain current does not flow. At the same time, the data can be read correctly by applying a small input voltage during reading. The semiconductor memory device according to the third embodiment of the present invention is basically the same as the structure of figure g for explaining the practice, and the equivalent circuit diagram is also the same. The writing operation and the holding operation are also the same as in the conventional technique. At δ, as described in the first embodiment, if the threshold voltage value th of the field effect transistor is positive, it is assumed that a voltage (0.5th) of the field-effect transistor is applied to the control line for reading. In addition, although the conventional FeFET and the FeFETs of Embodiments 1 and 2 write a voltage of Vg = ± 1 5 V to the control electrode in the writing system, this embodiment 3 is writing

Page 23 490859 Case No. 90105477 _ 'V. Description of the invention (ϊ ^ &quot;' — ----- The input voltage is set to Vg = ± 3V. In this embodiment 3, Fig. 5 shows the eighth series of application = 枓 0 "Writing operation state diagram; Figure 6 shows the state of data reading after 0.5V after f ~ 3V. • I don't know if Vg = 61, 63, 69 on Figure 5A, Figure 5B, and Figure 6 7 "糸 shows the ferroelectricity: ,, 75, line when the control electrode voltage is increased, 62, 64, 68, 70 series display = curve of characteristics, characteristic curve, each initial polarization value = = iron, body It is expected that in Fig. 05 'and Fig. 5β, 65 is the data "1" write operation 66 is the same as 2 J "&quot; operation, 67 is the holding operation, and 72 # in Fig. 6 shows the FET when it is not in operation Qi indicates that the 72 points on the ν mouth and 84 points indicate the operating points. The curve of f, 77 ~ will be described for writing from an initial state. The initial state refers to the data held by the two ^ The writing of the data; △ beauty-like evil. Compare the initial cautious action of a, Bll, and 开. If you start from this initial state, you can use HA :: different polarities obtained by applying different voltages. Compared with TU, the value is due to the strict operating conditions. Square: ί Two positive voltages in the initial state have a polarization value of 0 Coulombs / half of a ferroelectric 'like Pdfm characteristic 61. When the force 7 = 3v: 0 · Pair (Vg ~ Vf) characteristic is curve 65, pd versus "characteristic 61 2 versus two V;?) Intersection point A of characteristic 65 is data Π" Write motion ㈣ n ^ The control electrode is set to float, as described above m of

IMI II H-yuojy correction

No. 90105477 V. Description of the invention (20) U ^ Vg-Vf) Characteristic 67, which is close to Vg ~ 〇V, then who is involved, &amp; 丨 1 1 "Keeping the action point starts from the write action point gate Pd pair at reduced voltage "characteristic 62

Vf) Turn of characteristic 67. The Ql pair with the pull-over slave g VB 卞 (k-0 42V., The operating voltage of Ϊ / action point is h = set electricity; Γ is set to quickly ㈣ pair ... 1) Characteristics in the early stage of ferroelectric Based on the data "Official people's taste of Vf characteristics 63 and Vg = 3", write "m", Pd point C is the data "1 f should be included in the pair of (g-Vf) characteristics 65 at the cross electrode voltage of iron Electrical characteristics "two. 'Extremely small control: 0. Drain 0 j "1 as two come from two initial states, in the written data 1" FET drift gate electrode, 42V &amp; 0.39V, becomes Vi &lt; 柽 voltage Vl =. — Vx pole current does not flow:. In other words, the FET is in the off state. Next, "the operation of writing from the two initial stages will be described using" ㈣: month shape forgiveness ". The data will be described with reference to Fig. 5B. In the initial state, when you're ferroelectric with the name + ^, it becomes a Qi pair (vv, f 0 pair) characteristic of the FET with a bias value of 0 Coulomb / square centimeter. When Vg = -3V is applied Qi pair (Vg-Vn characteristics are curve 66,? (1 pair) characteristics 68 and

Here, float the control electrode or apply vg = ov, "then ㈡:

Case No. 90105477 V. Description of Invention (21) Action. This data "0" holds the operating point and &gt; The Pd vs. Vf characteristic fiq at the time of voltage application is given by v '., Starting from the writing operating point, at the intersection F of characteristic 67. When the operating point is maintained, g% 〇V ... For (Vg — Vf) Ferroelectrics is the initial value of the data "Operating voltage is Vx = 0.4V. For Vf characteristics 70 and Vg = -3V ○ material" μ When it has been written, the Pd point G is the data "0". The motion is: "quote Vf) The ferroelectric characteristics at the cross electrode voltage of characteristic 66. When this state starts, increase the control intersection Η to become the holding operation point. . Holding pair (V§ — 38V of V0 characteristic 67., The operating voltage of the run point is Vx = 0. So 'start from the shift of the FET n n centered by the two initial energy gates "0", at Have written data-0.40V and -0.38V 'become Vi electricity. It is ^ = Vg-VX = state, and the drain current does not flow. Vth. That is, the FET is turned off for two initial states. Action, use Figure 6 to add: Let ’s say enlightenment. Ten pairs of data “1” read the voltage on the control electrode. This action is to apply V g = 〇 · 3 V from the polarization value 〇 library inspection / period state At the beginning, the written information has been written; the first two 78 of the "0" of Guang and Zixiao, from the respective holding action, the holding action point is 77, and the voltage Vf characteristics 73 and 74 are applied to increase the voltage. 1 of the time ferroelectric

Vf) FET _ pair (1 is Vx = -0.3V and -0.28v at the intersection of characteristic 72. Vi is the operating point. This reads the operating voltage =, which is greater than the threshold voltage value :: : x = 0.6 V and 0.5 "are turned on. Therefore, the data π, / Vth), the FeFET will be read correctly.

J

P.26 490859 Case No. 9〇ηη77 77 V. Description of the Invention (22) Revision 1 Next, the operation for writing from two preliminary data “0” will be described using FIG. 6. From the beginning of 4, starting from the polarization value of 0 Coulomb / cm 2 and the data Γ1 ^ state, the written data "0" two first 80, from the respective holding action point #, pressurization The points are 79, Π characteristics 75, 76 and the applied Vg = 〇3 J, the Pd pair characteristics of the electrical body ... points 83, 84 are read-out actions; wide ^ &quot; .m and. · 44ν „νί = Vg _ νχ = _〇. The output voltage of the second output is Vx, so it is smaller than the threshold voltage (Vi <.14V, so the data“ 〇 ”can be read correctly.) 'FeFET is turned off . In this way, in the holding operation of the third embodiment of the present invention, the "FeFETs are all off", and "0.3V is added to enable correct reading." The electrode and the bit line are used immediately, that is, they can also form an mj-selecting transistor, which is a necessary embodiment. ~ 70 歹 '. Fig. 7 shows details of the ferroelectric capacitor 89 and the 90 FeFET, which are specific to Fig. 7. 9 1 indicates the gate selection transistor, '' interfering with-&amp; / body 92 (BL), 86 ΐίί «), 85 indicates the second character line (WL2), 87 indicates the source The polar lines (SL), 88 represent the basic units of the memory unit. A memory * element array of the number ZΛ2Γ column is appended to the number of the element or the number of the column of the table of each constituent element. For example, 8 6 -1, column ritual category means WU, WL2, SL in the first row, 92 — 1 means BL in the first 歹 J, 88-11 means row]! List of memory cells. Page 27 490859 Case No. 90105477 __- V. Description of the invention (23) Based on the memory cell array composed in this way, the memory cell array located at an arbitrary address is used as the non-volatile functional device by applying the driving method described above. Sex brother recalls body. The driving method is summarized in a table in FIG. 8. For example, when reading the data that has been written into the 1st row and 1st column (88-11 in FIG. 7) of the § memory cell array of FIG. 7, wli (86-u in FIG. 7 is set to 5V and the gate is selected The transistor is set to be on, and 0.3 V is applied to the breast? (85-1 in Fig. 7 '). At this time, the control electrode of the FeFET of the memory cell becomes "=, 0.3 V' if 0.3 V is applied to BL (Fig. 7). 92-1), apply (^ to 讥 (Figure 7, 87-1) ', then the drain current will flow from Bl to Sl. Connect to the terminal of BL, and output the amplifier. If the drain current is used to detect the voltage drop If the drain current value is changed according to the holding data, a correct reading operation can be performed. At this time, it is similarly connected to the memory cell of the second row and the second row of BL (88-21 in FIG. 7), although In the state of holding action, as mentioned above, because the drain current does not flow, the reading operation of the memory cells in the "!" Column does not cause any noise. Therefore, the drain electrode can be omitted. BL The memory cell of the transistor is selected in between. In addition, in Embodiment 3 of the present invention, the FeFET in the holding operation is set to off by adjusting the write voltage, except that In addition to this method, for example, by controlling the threshold voltage value by channel doping of the FET, it is also possible to set ί! T, eFET to OFF M. At the same time, adjust the ferroelectric FET / *, specific induction power constituting the FeFET. Material characteristics such as rate, impedance voltage, etc., or materials that adjust the film thickness, specific induction, impedance voltage, etc. of the gate insulation film # 2: ^ Set the FeFET during the operation to off 4 The method of controlling the threshold voltage value of the net, write the set voltage of the human voltage 490859 ___9090477_year, month, month, month, month, month, month, month, month, month, month, month, month, month, month, month, month, month, month, month, month, month, month, month, month, month, month, month, month, month, month, month, month, month, month, month, month, month, month, month, month, month, month, month, month, month, month, month, month, month, month, month, month, month, month, month, month, month, month, month, month, month, month, month, month, month, month, month, month, month, month, month, month, month, month, month, month, month, month, month for the month, and the day of the month. The effect transistor is in the range of the voltage value in the non-conducting state, and can have the same effect.

Also, in this specification, the MFMIS-type FeFET has been described. In the case of the MFIS-type FeFET, the operating voltage (writing voltage and reading voltage) can be set through the same considerations. The operating voltage setting method of this structure also includes Within the scope of patent application. That is, considering the drift gate electrode voltage in the present invention as the potential at the interface between the ferroelectric and the insulating film, the charge induced to the interface potential and the channel is calculated (and in this specification, the voltage at which the channel becomes conductive) Setting the voltage according to the relationship (vth in this specification) and the like can obtain the same effect as the present invention.

Page 29 490859-Prime No. 90105477__ 年月 日 __ Brief description of the diagram Figure 1 shows the relationship between the Ids ratio (on / of f ratio) and Vg of the data "1" and the data "0". Fig. 2 is a diagram showing an operation state of the semiconductor memory device according to the first embodiment of the present invention. 3A to 3C are diagrams showing operation states of the semiconductor memory device according to the second embodiment of the present invention. Figs. 4A and 4B are diagrams showing operation states of the semiconductor memory device according to the second embodiment of the present invention. 5A and 5B are diagrams showing the operation state of the semiconductor memory device according to the third embodiment of the present invention. Fig. 6 is an operation state diagram of the semiconductor memory device according to the third embodiment of the present invention. Fig. 7 is an array diagram of a semiconductor memory device according to a third embodiment of the present invention. Fig. 8 shows a driving voltage table of a semiconductor memory device according to a third embodiment of the present invention. The Agency has shown a cross-sectional structure diagram of the structure of a conventional semiconductor memory device according to an embodiment of the present invention. f set == There is an equivalent circuit diagram of the embodiment of the present invention and the conventional semiconductor memory configuration. The state diagrams Figure 1 and Figure m are operation diagrams of conventional semiconductor memory devices. Follow-up relationship is the operating state of a conventional semiconductor memory device

Page 30 490859 _Case No. 90105477_ Year Month Revision _ Brief Description of Drawings Figure 13 is a diagram of the operating state of a conventional semiconductor memory device. [Explanation of symbols] 85-1: Character line WL2 in the first row 85-2: Character line WL2 in the second row 86-1: Character line WL1 in the first row

86- 2 · Character line WL1 in the second line WL 1 8 7-1: Source line SL in the first line

87- 2: Source line SL in line 2

88-11: Memory cell in row 1 and column 88-12: Memory cell in row 1 and 2 88-21: Memory cell in row 2 and 1 8-22: 2nd row and 2 Memory Unit 89: Ferroelectric Capacitor

90: FET 91: Gate selection transistor

9 2-1: Bit line BL in the first row 9 2-2: Bit line BL in the second row

31 Substrate 32 High-concentration N-type implanted area of drain electrode 33 High-concentration N-type implanted area of source electrode 34 Dielectric 35 Drift gate voltage 36 Ferroelectric

Page 31 490859 _Case No. 90105477_Year_Month_Revision of the schematic diagram 37 Control electrode 41 Ferroelectric capacitor 42 FET 43 Control electrode 44 Source electrode 45 Drain electrode Vd Drain electrode voltage Vf Voltage between electrodes Vg Control gate voltage Vi Drift gate voltage Vs Source electrode voltage

Page 32

Claims (1)

-------- 6. Scope of patent application 1β Information of a semiconductor memory device 4 Capacitor AV7 * composed of a mountain electrode and a ferroelectric body, which are formed in pairs; One side electrode of the above capacitors is connected to the ν idle electrode, or one of the above capacitors is a gate electrode of a transistor of the effect type transistor; the side electrode also serves as the electric field effect, and the other side of the capacitor The electrode is used as the control electrode. Applying electricity to the above control electrode to change the upper 9 沭 ® π 4,5 $; 丨 the polarization of the electric body, and change the channel impedance of the application transistor, according to the level of the above channel impedance The table is not a binary data. Its characteristics are: = If the critical voltage value of the electric field effect transistor is positive, a positive voltage is applied to the control electrode; If the critical voltage value of the electric field effect transistor is negative, the voltage is applied. A negative voltage is applied to the control electrode. 2. If the method for funding a semiconductor memory device according to item 1 of the scope of the patent application, wherein: the voltage value applied to the control electrode is: When the threshold voltage value of the electric field effect transistor is positive, in When the residual polarization value of the capacitor is 0C / cm2, when the voltage between electrodes is increased from 0V to change the polarization value, when a critical voltage is applied to the gate electrode of the electric field effect transistor, The inter-electrode voltage value that generates a polarization value corresponding to the charge induced by the channel is added to the above-mentioned 49 859 force on page 33, the critical voltage value of the field-effect transistor in the patent application range, to obtain The voltage value is within ± 20% of the center. When the critical voltage value of the electric field effect transistor is negative, the voltage of the capacitor is 0 C / c m2. When the voltage between eggs starts to decrease from 0 V and the polarization value is changed, when the critical voltage is applied to the gate electrode of the above-mentioned electric field effect transistor, a charge equivalent to the charge induced in the channel will be generated. The voltage value between the electrodes of the polarization value is added to the above-mentioned critical voltage value of the electric field effect transistor, and the voltage value within the center of the obtained voltage value is within ± 20%. 3. Electrodes and formation; the data writing method of a semiconductor memory device in which the upper gate electric transistor will be pressed above the above low level, indicating that it is in an applied state, and a capacitor composed of a pair of ferroelectric bodies , One side electrode connected to the f capacitor of the electric field effect transistor is connected to the electric field effect transistor, which is one side electrode of the capacitor and serves as the gate electrode of the electric field body; i ί 2 ϊ the other The side electrode is used as the control electrode. By applying the polarization of the rr electric body, the impedance is changed to-ϊ 逞 through 依 impedance, according to the above-mentioned channel impedance and the value of the data; Features: The voltage value is within the range after the voltage is applied. The above electric field effect type transistor system is non-conducting Page 34 490859 VI. Application for Patent Scope 4. A method for driving a semiconductor memory device. After applying the data writing method for the semiconductor memory device in the third item of the application scope, after the data is written, a reset voltage is applied. On the control electrode. 5. · A method for reading data from a semiconductor memory device, for reading the data from the semiconductor memory device written in the lean material according to the third item of the claim range. , Characterized in that: when the critical voltage value of the electric field effect transistor is positive, a positive voltage is applied to the control electrode, and a voltage lower than the critical voltage value is applied to the electric field effect transistor; if the above If the critical voltage value of the electric field effect transistor is negative, a negative f voltage is applied to the control electrode, and a voltage higher than the critical voltage value is applied to the electric field effect transistor. 6 · The method for reading data from a semiconductor memory device according to item 5 of the scope of patent application, wherein: ^ a capacitor composed of the pair of electrodes and a ferroelectric body, and a semiconductor composed of the electric field effect transistor described above The memory devices are arranged in a plurality of matrices; the drain electrode of the electric field effect transistor is connected to the bit line, the source electrode is connected to the source line, and the source electrode of the second electric field effect transistor is connected to the control electrode; Page 490 490859 Page 36