TWI251039B - Semi-pure monocrystalline silicon wafers, pure monocrystalline silicon wafers and a Czochralski puller - Google Patents

Semi-pure monocrystalline silicon wafers, pure monocrystalline silicon wafers and a Czochralski puller Download PDF

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TWI251039B
TWI251039B TW91115554A TW91115554A TWI251039B TW I251039 B TWI251039 B TW I251039B TW 91115554 A TW91115554 A TW 91115554A TW 91115554 A TW91115554 A TW 91115554A TW I251039 B TWI251039 B TW I251039B
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Taiwan
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wafer
pure
ingot
void
interstitial
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TW91115554A
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Chinese (zh)
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Jae-Gun Park
Kyoo-Chul Cho
Gon-Sub Lee
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Samsung Electronics Co Ltd
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Priority claimed from KR1019970054899A external-priority patent/KR19980070037A/en
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Abstract

A silicon ingot is manufactured in a hot zone furnace by pulling the ingot from a silicon melt in the hot zone furnace in an axial direction, at a pull rate profile of the ingot from the silicon melt in the hot zone furnace that is sufficiently high so as to prevent interstitial agglomerates but is sufficiently low so as to confine vacancy agglomerates to a vacancy rich region at the axis of the ingot. The ingot so pulled is sliced into a plurality of semi-pure wafers each having a vacancy rich region at the center thereof that includes vacancy agglomerates and a pure region between the vacancy rich region and the wafer edge that is free of vacancy agglomerates and interstitial agglomerates. According to another aspect of the present invention, the ingot is pulled from the silicon melt in the hot zone furnace at a pull rate profile of the ingot from the silicon melt in the hot zone furnace that is sufficiently high so as to prevent interstitial agglomerates, but is also sufficiently low as to prevent vacancy agglomerates. Accordingly, when this ingot is sliced into wafers, the wafers are pure silicon wafers that may include point defects but that are free of vacancy agglomerates and interstitial agglomerates.

Description

1251039 A7 B71251039 A7 B7

經濟部智慧財產局員工消費合作社印製Ministry of Economic Affairs, Intellectual Property Bureau, employee consumption cooperative, printing

關曱 本案請求美國申請案第60/063,086號之權益 形成半導體鑄1 定之方法及由此形成的鑄錠及晶圓”,申請Ε ㈣年1〇月24日及韓國申請案第9'5娜號,二 年10月24日,此二案皆被納入於此以供參考。 發明領域 ,、本發明係關於微電子製法及裝置’特別係關於石夕鑄裁 製法及由此製造的矽鑄錠及晶圓。 發明背i 。。積體電路廣用於消費者及商業料。積體電路通常由 早晶石夕所製成。隨著積體電路的積體密度持續增高,對於 積體電路提供高品f單晶半導體材料即具有增高之重要 性。積體電路常藉由製造單晶破讀,再將大鍵切成晶圓, 方、曰曰圓進仃大量微電子製造過程,然後將晶圓模切成經封 裝之個別積體電路而製得。时_的純度及結晶度對於 最終積體電路裝置的性能具有極大的衝擊,故在製造較少 缺1¾的每錠及晶圓上已投注許多努力。 現在說明習知單晶石夕鑄旋之製法。此等方法之回顧係 提=教科書“VLSI世切加卫,第_卷,製程技術,,之 第一章,作者吳爾夫(wolf)及陶伯(Tauber), 1986年 頁(’、揭鉻内谷被納入於此以供參考)。單晶石夕製造中,電 子級多晶發被轉化成單晶石夕鑄錠。諸如石英岩之多晶石夕被 精煉,而製成電子級多晶矽。隨後,使用柴可拉斯基(cz) 及浮面區段(FZ)技術,令經精煉之電子級多晶矽增長成Regarding the case, the right to apply for US application No. 60/063,086 forms the method of semiconductor casting and the ingots and wafers formed by it," application Ε (4), January 24, and Korean application, 9'5 Na No. 2, October 24, the second case is incorporated herein by reference. In the field of the invention, the present invention relates to a microelectronic manufacturing method and apparatus, in particular to the method of cutting and casting Ingots and wafers. Inventive circuits are widely used in consumer and commercial materials. Integral circuits are usually made of early quartz. As the integrated density of integrated circuits continues to increase, for integrated products. The circuit provides high-quality single-crystal semiconductor materials, which is of great importance. The integrated circuit often cuts into large wafers by manufacturing single crystals, and then cuts into large numbers of microelectronics manufacturing processes. Then, the wafer is die-cut into a packaged individual integrated circuit. The purity and crystallinity of the wafer have a great impact on the performance of the final integrated circuit device, so that less than 1⁄4 of each ingot and crystal are produced. There have been many efforts on the circle. The method of the method of Shi Xizhuan. The retrospective of these methods = textbook "VLSI World Cut, _ volume, process technology, the first chapter, author wolf and Tauber, 1986 Page (', the chrome valley is included here for reference). In the manufacture of single crystal, the electron polycrystalline hair is converted into a single crystal ingot. Polycrystalline crystals such as quartzite are refined to form electronic grade polysilicon. Subsequently, the refined electronic grade polycrystalline silicon is grown into a chalcura (cz) and floating surface (FZ) technique.

夹紙張尺度適用中國國家標準(CNS)A4規格(210 X 297公釐)The paper size is applicable to the Chinese National Standard (CNS) A4 specification (210 X 297 mm)

• I .^1 · ->1 (請先閱讀背面之;tti意事^^填寫本頁} II _ 訂--- 1251039 A7 B7 五、發明說明(2 智 慧 財 產 局 員 費• I .^1 · ->1 (Please read the back of the article; tti means ^^ fill out this page} II _ Book--- 1251039 A7 B7 V. Invention Description (2 Zhihui Property Officer Fee

S 晶。因本發明侧於使用cz技術純切鑄錠,故現在 說明該技術。 CZ增長係關於結晶固化源自於位在界面處之液相的 原;子。特別是,將電子級多晶石夕進料載入-掛網中,並溶 化。亥進料。令具有正確定向耐受度㈣晶種下降入炫融 内。接著,沿軸向以一受控制之速率卸出該晶種。晶種 坩堝通常於提拉過程以反向旋轉。 初始提拉速率通常較快,因而產生細石夕頸。然後,降 T亚穩定化溶融體溫度’而形成所需之_直徑。此一直 徑通常係藉由控制提拉速率來維持。提拉持續至進料接近 耗盡為止,此時形成尾端。 第1圖為CZ提拉哭之+立固 租的之不思圖。如第1圖所示,cz 2器100包含一爐、-晶體提拉機構、-環境控制器及以 電腦為主的控制系統。cz^ 及 加熱元件…4’石英 外掛㈣及於第一方向、二 禍106’石墨製成的 σ 112疑轉的轉軸110(如所示)。 井114可提供額外熱分布。 該晶體提拉機構包含晶體提拉軸m,如所示,盆 朝方向112的反向122旋轉。b 八 124,节日鐘日0奸拉轴12G固持晶種 遠曰曰種124係由位在掛 ⑶中被提拉出,而形成鑄旋128。w夕進料 该核境控制系統包含腔室包圍體i3Q、_ 口 及其他流量控制器及真空通風系統(未顯示)。二 主之控制系統可用來控制加熱元件、提拉器及其他電 矽 及 注 意 提 敎 •έ 能 種 132 腦為 氣與 ^張尺—中 _鮮(CNS)A4 1251039S crystal. Since the present invention is based on the pure ingot casting using the cz technique, the technique will now be described. The CZ growth is related to the crystallization solidification originating from the liquid phase at the interface; In particular, the electronic grade polycrystalline lithofate feed is loaded into the net and melted. Hai feed. Let the seed with the correct orientation tolerance (4) fall into the glare. The seed crystal is then discharged at a controlled rate in the axial direction. The seed crystal is usually rotated in the opposite direction during the pulling process. The initial pull rate is usually faster, resulting in a fine stone neck. Then, the T substrate stabilizes the melt temperature' to form the desired diameter. This path is usually maintained by controlling the pull rate. The pulling is continued until the feed is nearly exhausted, at which point the tail is formed. The first picture shows the CZ pulling the crying + standing solid renting. As shown in Fig. 1, the cz 2 device 100 includes a furnace, a crystal pulling mechanism, an environmental controller, and a computer-based control system. Cz^ and the heating element...4' quartz plug-in (four) and the yoke 112 made of the first direction, the second fault 106' graphite, which is suspected to rotate (as shown). Well 114 can provide additional heat distribution. The crystal pulling mechanism includes a crystal pulling axis m which, as shown, rotates in a direction 122 of the direction 112. b 八 124, Festival clock day 0 rape pull shaft 12G holding seed crystals Faraway species 124 series are pulled out in the hanging (3), forming a casting spin 128. W 进 Feed The nuclear control system consists of chamber enclosures i3Q, _ port and other flow controllers and vacuum ventilation systems (not shown). The main control system can be used to control heating elements, pullers and other electric devices and to pay attention to the 敎 • έ can be species 132 brain gas and ^ ft - middle _ fresh (CNS) A4 1251039

經濟部智慧財產局員工消費合作社印製Ministry of Economic Affairs, Intellectual Property Bureau, employee consumption cooperative, printing

真實之矽鑄錠與理想之單晶矽不同,因為真實之矽鑄 錠包含缺陷或瑕疵。此等瑕疵乃是積體電路裝置製造上所 不期望者。此等瑕疵通常歸類為點瑕疵或集聚體(三度空間 瑕疵)。點瑕疵分兩大類:空隙點瑕疵及填隙點瑕疵。空隙 點瑕疵中,一個矽原子由矽晶格的正常位置喪失。這個空 隙造成空隙點瑕疵。另一方面,若一個原子出現於矽晶體 的非晶格位置(填隙位置)則造成填隙點瑕疵。 點瑕疵通常係於熔融矽126與固體矽128之間中界面 130上形成。但隨著鑄錠128繼續被提拉,界面部分開始 冷卻。冷卻過程中空隙點瑕疵及填隙點瑕疵擴散可能造成 瑕疵聚結,而形成空隙集聚體或填隙集聚體。集聚體為點 瑕疵之聚結所引起的三度空間(大型)結構。填隙點瑕疵也 稱作易位瑕疵或D-瑕疵。有時候,集聚體亦以用於檢測此 等瑕疵之技術來命名。因此,空隙集聚體偶爾亦被稱作晶 體來源顆粒(cop),雷射散射斷層掃描(LST)瑕疵,或流動 圖樣瑕疵(FPD)。填隙集聚體也稱作大型易位(L/D)集聚 體。單晶矽的瑕疵討論參考前述吳爾夫及陶伯的教科書第 2章(其揭露内容被納入於此以供參考)。 已知許多參數需被控制,俾來增長出具有少量瑕疵的 (請先閱讀背面之注意事項再填寫本頁) I· -裝 祕· 本紙張尺度適用中國國家標準(CNS)A4規格(210 1251039 A7 B7The real bismuth ingot is different from the ideal single crystal enamel because the real bismuth ingot contains defects or flaws. These defects are not expected in the manufacture of integrated circuit devices. These defects are usually classified as point or agglomerates (three-dimensional space 瑕疵). There are two main categories of points: gap points and gaps. In the void point, a germanium atom is lost by the normal position of the crystal lattice. This gap creates a void point. On the other hand, if an atom appears in the amorphous lattice position (interstitial position) of the germanium crystal, the interstitial point is caused. The spot is typically formed on the interface 130 between the molten crucible 126 and the solid crucible 128. However, as the ingot 128 continues to be pulled, the interface portion begins to cool. The void point 瑕疵 and the interstitial point 瑕疵 diffusion during cooling may cause enthalpy coalescence to form void aggregates or interstitial aggregates. The agglomerate is a three-dimensional (large) structure caused by the coalescence of the point. The gap filling point is also called translocation D or D-瑕疵. Sometimes, agglomerates are also named after the technique used to detect such defects. Therefore, void agglomerates are occasionally referred to as crystal-derived particles (COP), laser scattering tomography (LST), or flow pattern enthalpy (FPD). Interstitial aggregates are also known as large translocation (L/D) aggregates. For a discussion of the 矽 of single crystal 参考, refer to Chapter 2 of the aforementioned textbooks by Wulf and Tauber (the disclosures of which are incorporated herein by reference). It is known that many parameters need to be controlled, and then there is a small amount of defects (please read the back note and then fill out this page) I· -Installation · This paper scale applies to China National Standard (CNS) A4 specification (210 1251039 A7 B7

經濟部智慧財產局員工消費合作社印製Ministry of Economic Affairs, Intellectual Property Bureau, employee consumption cooperative, printing

尚純度鑄錠。例如,已知需控制晶種提拉速率及熱區段結 構的溫度梯度。佛隆可夫理論發現到,乂對g之比例(稱; V/G)可決定鑄鍵的點瑕_度,其中v為鑄鍵之提拉迷 率,而G為鑄㈣融體界面的溫度梯度。佛隆可夫理論詳 述於“石夕旋满瑕㈣成機制,,中,作者佛隆可夫,晶體增 長期刊59卷,1982年,625-643頁。 曰 /佛隆可夫理論的-個應用可見於本案發明人的文獻, 名稱為“晶體瑕觸裝置特性的影響,,,第2屆國際先 材料科技研討會議事錄,1996年n月25至29日,第SB 頁。該文獻第15圖(此處再製成第2圖)中顯示出,空隙濃 度及填隙濃度呈WG函數之示意說明圖。佛隆可夫理論顯 示出,曰a圓的空隙/填隙混合物的產生係由V/G來決定。詳 言之’低於一臨界比的V/G比會形成富含填隙之禱鍵,而 高於一臨界比的WG比會形成富含空隙之鑄錠。 雖然物理學家、材料學家及其他進行許多理論研究及 CZ提拉器製造商進行許多實際研究,但降低單晶矽晶圓中 的瑕疵密度仍為一個持續性的需求。最終的需求乃在於不 含有空隙集聚體及填隙集聚體之純石夕晶圓。 發明概诚 本發明係關於一種在熱區段爐中製造矽鑄錠的方法, 其藉由在一源自於位在該熱區段爐之一矽熔融體的鑄錠提 拉速率曲線圖下,由位在該熱區段爐之一矽熔融體中,沿 著軸向^拉出該每錠,該提拉速率係足夠高而可避免填 隙集聚體,但亦足夠低以將空隙集聚體限制在該鑄錠之Still ingots. For example, it is known to control the rate of pull of the seed crystal and the temperature gradient of the hot section structure. According to the Fronkov theory, the ratio of 乂 to g (called V/G) determines the point 铸 degree of the cast bond, where v is the pull-up fan of the cast bond, and G is the cast (four) melt interface. Temperature gradient. The Fronkov theory is detailed in the "Shi Xixuan Manchu (four) into the mechanism,", in the author, Fronkov, Journal of Crystal Growth, Vol. 59, 1982, pp. 625-643. 曰/Fronkov Theory - The application can be found in the inventor's literature, entitled “The influence of the characteristics of the crystal contact device,” Proceedings of the 2nd International Symposium on Materials Science and Technology, 25-29 November 1996, p. SB. The fifteenth diagram of the document (herein reproduced in Fig. 2) shows a schematic illustration of the WG function as a function of the void concentration and the interstitial concentration. The Fronkov theory shows that the generation of the void/interstitial mixture of the 曰a circle is determined by V/G. In detail, the V/G ratio below a critical ratio creates a gap-filled prayer, while a WG ratio above a critical ratio creates a void-rich ingot. Although physicists, materials scientists, and others have conducted many theoretical studies and CZ puller manufacturers have done a lot of practical research, reducing the germanium density in single crystal germanium wafers is still a continuing need. The ultimate need is for pure stone wafers that do not contain void agglomerates and interstitial aggregates. SUMMARY OF THE INVENTION The present invention is directed to a method of making a bismuth ingot in a hot zone furnace by plotting a draw rate of an ingot derived from a bismuth melt in the hot zone furnace From each of the ingots in the hot zone furnace, the ingot is drawn along the axial direction, the pulling rate is sufficiently high to avoid interstitial aggregates, but also low enough to agglomerate the voids Body is limited to the ingot

本紙張尺度適用中國國家標準(CNS)A4規格(210 X 297公釐This paper scale applies to the Chinese National Standard (CNS) A4 specification (210 X 297 mm)

-· Μ m / ϋ I n r請先閱讀背2Ϊ事調填寫本i -I I - 訂---- 1251039 A7 經濟部智慧財產局員工消費合作社印製 五、發明說明(5 ) 一富含空隙區内。隨後,將由此提拉出的鑄錠切成數片半 完美晶圓,該等晶圓於其中心處具有一個包括有空隙集聚 體的畜含空隙區,以及一個介於該富含空隙區與晶圓邊緣 間的純貝d ’该純質區不含有空p家集聚體及填隙集聚體。 本發明係基於了解到,惟有點瑕疵之濃度超過某個臨 界濃度時,才會由點瑕疵形成集聚體。若(空隙或填隙)點 瑕疫之濃度能被維持在低於此臨界濃度,則禱旋被提拉時 不會形成集聚體。為了將點瑕窥濃度維持在低於臨界點瑕 疵濃度,位在鑄錠-熔融體界面處的提拉速率對溫度梯度之 比例(V/G)被限制在高於位在鑄錠_熔融體界面處之提拉 速率對溫度梯度的第一臨界比,該第一臨界比需被維持, 以避免填隙集聚體;以及(2)低於位在鑄錠_熔融體界面處 之提拉速率對溫度梯度的第二臨界比,該第二臨界比係不 了過大俾將空隙集聚體限制在鑄錠中心處之一富含空隙 區。因此,當鑄錠由熱區段爐的矽熔融體中被提拉出時, 提拉速率之曲線圖被調整成能將提拉速率對溫度梯度維持 在高於第一臨界比且低於第二臨界比。 依據本發明之另一態樣,其係藉由在一源自於位在該 熱區段爐之一矽熔融體的鑄錠提拉速率曲線圖下,由位在 該熱區段爐之一矽熔融體中,提拉出該鑄錠,該提拉速率 係足夠高而可避免填隙集聚體,但亦足夠低以避免空隙集 來體。因此’當該鑄錠被切成晶圓時,該晶圓為包括有點 瑕疲’但不含有空隙集聚體與填隙集聚體的純質矽晶圓。 根據本發明之此態樣,其已測定出,若將V/G比例限 ^紙張尺度適用fia家標準(CN〗)A4規格(21Q χ 297公髮- (請先閱讀背面之注意事:填寫本頁) I· 丨裝 J. 發明說明(6 ) 制在一較狹窄之範圍内,則點填隙濃度及點空隙濃度此二 者均可被維持在低於形成集聚體的臨界點瑕疵濃度下。因 此,整個鑄錠可不含有集聚體。 欲幵y成純石夕,決疋於•錠炫融體界面的提拉速率變化 曲線圖對溫度梯度之第一臨界比,需維持第一臨界比以防 填隙集聚體。決定於鑄錠-熔融體界面的提拉速率變化曲線 圖對溫度梯度之第二臨界比,不可超過第二臨界比以防空 隙集聚體。然後決定提拉速率變化曲線圖而當禱鍵由熱區 段熔爐的矽熔融體提拉時,可維持提拉速率變化曲線圖對 溫度梯度比高於第一臨界比而低於第二臨界比。 欲維持於鑄錠-熔融體界面的提拉速率對溫度梯度比 介於兩種臨界比間,考慮徑向溫度梯度及軸向溫度梯度。 於徑向方向,跨越晶圓的溫度梯度通常改變,原因為晶圓 中:比較邊緣部分接觸不同熱環境故。特別晶圓邊緣的溫 度梯度通常比晶圓中心、高,此乃熱特性造成者。提拉速率 跨越晶圓通常恆定。因此V/G比於徑向方向通常由晶圓中 心朝向晶圓邊緣減低。提拉速率及熱區段爐設計成由晶圓 中心至晶圓邊緣的擴散長度以内,維持V/G比低於引起集 聚體的臨界點瑕_度,亦即介於第_臨界比與第二臨界 比間』似考慮可應用於輛向。於軸向,因鑄錠熱質量的 曰力故/皿度梯度隨著鑄旋的提拉而減小。如此當禱旋提拉 =拉速率必須減慢以維持V/G比介於第一與第二臨界比 因此,藉由控制提拉速率曲線圖,而將V/G維持在上 經濟部智慧財產局員工消費合作社印製-· Μ m / ϋ I nr Please read the back 2 Ϊ 填写 填写 填写 i i i i i i i i i i i i i i i i i i i i i i i i i i i i i i i i i i i i i i i i i i i i i i i i i i i i i i i i i i i i i i i i i i i i Inside. Subsequently, the thus-drawn ingot is cut into a plurality of semi-perfect wafers having a void region including a void agglomerate at a center thereof, and a gap region between the void-rich region and The pure shell d ' between the edges of the wafer does not contain empty p-aggregates and interstitial aggregates. The present invention is based on the understanding that an agglomerate is formed from a point enthalpy when the concentration of a certain enthalpy exceeds a certain critical concentration. If the concentration of the plague at the (void or interstitial) point can be maintained below this critical concentration, the aggregate will not form when the prayer is pulled. In order to maintain the point peek concentration below the critical point enthalpy concentration, the ratio of the pulling rate to the temperature gradient (V/G) at the ingot-melt interface is limited to be higher than the ingot_melt. a first critical ratio of the pull rate to the temperature gradient at the interface, the first critical ratio needs to be maintained to avoid interstitial aggregates; and (2) the pull rate below the ingot-melt interface For the second critical ratio of the temperature gradient, the second critical ratio is not excessively large, and the void agglomerates are confined to one of the void-rich regions at the center of the ingot. Therefore, when the ingot is pulled out of the crucible melt of the hot zone furnace, the graph of the pull rate is adjusted to maintain the pull rate versus the temperature gradient above the first critical ratio and below Two critical ratio. According to another aspect of the present invention, it is provided by one of the hot zone furnaces by a drawing rate of the ingot derived from the melt of one of the hot zone furnaces. In the crucible melt, the ingot is pulled out, the pulling rate is sufficiently high to avoid interstitial aggregates, but also low enough to avoid void collection. Thus, when the ingot is cut into wafers, the wafer is a pure tantalum wafer that includes a bit of fatigue but does not contain void aggregates and interstitial agglomerates. According to this aspect of the invention, it has been determined that if the V/G ratio is limited to the paper size, the Fia standard (CN) A4 specification (21Q 297 297 cc) is applied (please read the following notes: This page) I· Armored J. Description of invention (6) In a narrower range, both the point gap concentration and the point void concentration can be maintained below the critical point concentration of the agglomerate. Therefore, the whole ingot may not contain agglomerates. To 幵 y into pure stone eve, it is necessary to maintain the first criticality of the first critical ratio of the temperature gradient of the pulling rate change diagram of the ingot smelting interface The ratio of the pull rate change diagram of the ingot-melt interface to the second critical ratio of the temperature gradient cannot exceed the second critical ratio to prevent the void aggregate. Then the pull rate change is determined. The graph can be maintained when the prayer key is pulled by the crucible melt of the hot section furnace, and the temperature gradient ratio is higher than the first critical ratio and lower than the second critical ratio. - The pull rate of the melt interface is compared with the temperature gradient The radial temperature gradient and the axial temperature gradient are considered between the two critical ratios. In the radial direction, the temperature gradient across the wafer is usually changed because the wafer is in contact with different thermal environments. The temperature gradient at the edge is usually higher than the center of the wafer, which is caused by thermal characteristics. The pull rate is usually constant across the wafer. Therefore, the V/G ratio is usually reduced from the center of the wafer toward the edge of the wafer. The rate and heat zone furnace is designed to be within the diffusion length from the center of the wafer to the edge of the wafer, maintaining the V/G ratio below the critical point of the agglomerate, ie, the _th critical ratio and the second critical Compared with the room, it can be applied to the direction of the vehicle. In the axial direction, due to the thermal mass of the ingot, the gradient of the dish decreases with the pulling of the casting. So when the prayer is pulled, the pulling rate must be reduced. Slow to maintain the V/G ratio between the first and second critical ratios. Therefore, by controlling the pull rate graph, the V/G is maintained at the Intellectual Property Office of the Ministry of Economic Affairs.

A7 B7A7 B7

1251039 述兩種臨界濃度之間,則可生成「具有—位在中心處之富 含空隙區以及-介於該富含空隙區與晶圓邊緣間之純質區 的半純貝日日圓」。该富含空隙區可包括空隙點瑕疵以及集聚 體瑕疵,而該純質區則不含有任何空隙集聚體與填隙集聚 體。較佳地’純質晶圓可被生成,其包括有點瑕疲,但不 含有空隙集聚體與填隙集聚體。 该第一與第二臨界比可藉由實驗或模擬來測定。該等 比例可藉由將一參考鑄錠切成數片晶圓或軸向地切割該參 考鑄錠而實證地測出。亦可組合性地應用實驗及模擬技術。 特別是,该第一與第二臨界比可藉由在一個於一提拉 速率範圍内變化的提拉速率下,由熱區段爐之矽熔融體中 提拉出一苓考鑄錠而實驗性地測出。隨後,將該參考鑄錠 切成數片晶圓。對於半純質晶圓而言,可鑑定出一個具有 預疋尺寸之g含空隙區且不含有填隙集聚體的晶圓。較佳 地,鑑定出一具有最小富含空隙區且不含填隙集聚體之晶 圓。該半純質晶圓的第一及第二臨界比係由經鑑別之晶圓 的提拉速率以及經鑑別之晶圓在鑄錠中之位置而予以計算 出。 # 為測定純質晶圓的第一及第二臨界比,可提拉出參考 今、疋將之切成數片晶圓,再鑑定不含有空隙集聚體與填 隙集聚體的晶圓。純質晶圓的第一及第二臨界比係由經鑑 別之晶圓的提拉速率以及經鑑別之晶圓在鑄錠中之位置而 予以計算出。 參考鑄錠較佳以於某種提拉速率範圍改變的提拉速率1251039 Between the two critical concentrations, a semi-pure beijing circle with a void-rich region at the center and a pure region between the void-rich region and the edge of the wafer can be generated. The void-rich zone may include void spots and aggregate enthalpy, while the pure zone does not contain any void aggregates and interstitial aggregates. Preferably, a pure wafer can be formed which includes a little fatigue but does not contain void aggregates and interstitial aggregates. The first and second critical ratios can be determined by experiment or simulation. The ratios can be empirically measured by cutting a reference ingot into a plurality of wafers or axially cutting the reference ingot. Experimental and simulation techniques can also be applied in combination. In particular, the first and second critical ratios can be experimentally extracted from the crucible melt of the hot zone furnace by pulling at a pulling rate in a range of a pulling rate. Sexually measured. Subsequently, the reference ingot is cut into a plurality of wafers. For semi-pure wafers, a wafer with a pre-size of g-containing void regions and no interstitial agglomerates can be identified. Preferably, a crystal circle having a minimum void-rich region and no interstitial aggregate is identified. The first and second critical ratios of the semi-pure wafer are calculated from the extracted wafer's pull rate and the location of the identified wafer in the ingot. # To determine the first and second critical ratios of a pure wafer, the reference wafer can be pulled into several wafers and the wafers containing no void agglomerates and gap agglomerates can be identified. The first and second critical ratios of the pure wafer are calculated from the lift rate of the identified wafer and the location of the identified wafer in the ingot. The reference ingot is preferably at a pull rate that varies in a certain pull rate range

邊氏張尺度適用中國國家標準(CNSU4規格⑽Bian's Zhang scale applies to Chinese national standards (CNSU4 specifications (10)

1251039 A7 五、發明說明(8 經濟部智慧財產局員工消費合作社印製 由熱區段爐的矽熔融體提拉,由第一提拉速率之低於第一 提拉速率的第二提拉速率,至高於第二提拉速率但低於或 高於第一提拉速率的第三提拉速率。第一、第二及第二提 拉速率較佳基於所需鑄錠直徑及期望V/G比。提拉速率的 線性變化較佳用來決定第一及第二臨界比。 在另一實驗技術中,參考鑄錠係在一個於一提拉速率 範圍内變化的提拉速率下,由熱區段爐之矽熔融體中提拉 出。隨後,軸向地切割該參考鑄錠。對於半純質晶圓而言, 在經軸向切割之鑄錠中,鑑定出至少一具有最小之富含空 隙區且不含填隙集聚體的軸向位置。接著,從軸向切割鑄 録:中所鑑定出之軸向位置的對應提拉速率計算出該半純 晶圓的第一及第二臨界比。 為了生成完美的晶圓,在經軸向切割之鑄錠中,鑑 出至少一不具有空隙集聚體與填隙集聚體的軸向位置。〜 著,從鑑定出之軸向位置的提拉速率以及該軸向位置的位 置计异出該完美晶圓的第一及第二臨界比。 也可使用模擬方式理論決定第一及第二臨界比。特別 第一及第二臨界比可由佛隆可夫理論鑑別。提拉速率變 曲線圖對徑向溫度可由模擬鑄錠提拉過程的特定熱區段 的作業決定。提拉速率變化曲線圖對軸向溫度可由模擬 錠提拉時熱區段爐的作業決定。可維持提拉速率對鑄錠溫 度梯度比高於第-臨界比,而低於第二臨界比的提拉速率 變化曲線11,隨後可由模擬提拉速率聽向溫度圖及模 提拉速率對軸向溫度圖決定。 質 定 接 化 爐 鑄 擬 (請先閱讀背面之注意事:填寫本頁) 裝 ·- *k_ 11 1251039 A7 B7 五、發明說明(9 ) 也須瞭解純石夕的第一及第二臨界比可以二步驟式方法 鑑別。首先,以貫驗及/或理論方式決定半純矽的第一及第 一臨界比。然後修改熱區段結構直至以實驗及/或理論方式 決定第一及第二臨界比。 本發明提供由矽鑄錠製造的多個類似半純單晶矽晶 圓。各個半純石夕晶圓於中心具有富含空隙區其包含空隙集 聚體及介於富含空隙區與晶圓邊緣間的純質區不含空隙集 聚體及填隙集聚體。各晶圓的富含空隙區大體直握相等。 幸乂佳純貝區至少佔晶圓面積的36%。更佳純質區至少佔晶 圓面積的60%。 若更緊密控制V/G比,本發明可生產多個由單一矽鑄 奴製造的純單晶矽晶圓,其中各個純矽晶圓包含空隙集聚 體及填隙集聚體。如此經由維持提拉速率對鑄錠_熔融體界 面的溫度梯度比介於上限與下限間,可將集聚體瑕庞限制 於晶圓中心的富含空隙區或可消除集聚體而生產純矽晶 圓。 曰曰 圖式之簡單說明 第1圖為增長單晶石夕鑄錠之柴可拉斯基提拉器之示音 代表圖。 ~ 第2圖圖解說明佛隆可夫理論。 苐3 A-3 E圖示例說明於中心具有富含空隙區及介於舍 含空隙區與晶圓邊緣間具有純質區的晶圓之製造綜覽。田 第4A-4E圖示例說明不含集聚體之晶圓製造之综覽。 7本紙張尺度適用中國國家標準(CNS)A4規格(210 X 297公釐) (請先閱讀背面之注意事:填寫本頁) ,裝 輪· 經濟部智慧財產局員工消費合作社印製 12 1251039 五 發明說明 第5圖示例說明根據本發 拉速率變化錢圖。 理論^決定提 第6圖示例說明根據本發明使用軸向 决疋提拉速率變化曲線圖。 、、’X式 第7圖示例說明根據本發 決定提拉速率變化曲線圖。 明係藉晶圓鑑別以實驗方式 經濟部智慧財產局員工消費合作社印製 第8圖示例說明根據本發明製造鑄錠之模擬、 片與晶圓鑑別的組合。 第9圖為根據本發明修改而形成完美石夕之柴可拉斯基 提拉器之示意代表圖。 第10圖示例說明改變提拉速率俾決定根據本發明之 較佳提拉速率。 第11圖為X光斷層掃描影像之代表圖,示例說明根 據本發明之第一參考鑄錠的富含空隙區,富含填隙區及完 美區。 第12圖為X光斷層掃描影像之代表圖,示例說明根 據本务明之第一參考轉錠的富含空隙區,富含填隙區及完 美區。 第13及14圖圖解說明根據本發明增建富含空隙晶圓 及完美晶圓的提拉速率變化曲線圖。 元件標號對照表 木可拉斯基(CZ)提拉器 106 内掛禍 102’ 104加熱元件 1〇8 外坩塌 +紙張尺度適用中國國家標準(CNS)A4規格(210 X 297公釐) X λ L; Η 軸向切 (請先閱讀背面之注意事:填寫本頁) ·!· -裝1251039 A7 V. INSTRUCTIONS (8) The Ministry of Economic Affairs, Intellectual Property Office, Staff Consumer Cooperative, printed by the 矽 melt of the hot zone furnace, the second pull rate of the first pull rate lower than the first pull rate a third pull rate that is higher than the second pull rate but lower or higher than the first pull rate. The first, second and second pull rates are preferably based on the desired ingot diameter and the desired V/G The linear change in the pull rate is preferably used to determine the first and second critical ratios. In another experimental technique, the reference ingot is heated at a pull rate that varies over a range of pull rates. The zone furnace is pulled out of the melt. Subsequently, the reference ingot is axially cut. For semi-pure wafers, at least one of the ingots that have been axially cut is identified as having the least The void-containing region does not contain the axial position of the interstitial aggregate. Next, the first and second of the semi-pure wafer are calculated from the corresponding pull rate of the axial position identified in the axial cut casting: Critical ratio. In order to produce a perfect wafer, in the axially cut ingot, At least one axial position without the void agglomerate and the interstitial aggregate. The tensile rate from the identified axial position and the position of the axial position are different from the first wafer of the perfect wafer. The second critical ratio. The first and second critical ratios can also be determined using the analog mode theory. The first and second critical ratios can be identified by the Fronkov theory. The pull rate change graph can be used to simulate the radial temperature. The operation of the specific hot section of the pulling process is determined. The pulling rate change graph determines the axial temperature can be determined by the operation of the hot section furnace when the simulated ingot is pulled. The pulling rate can be maintained to be higher than the ingot temperature gradient ratio. - the critical ratio, and lower than the second critical ratio of the pull rate change curve 11, which can then be determined by the analog pull rate audible temperature map and the mode pull rate versus the axial temperature map. First read the note on the back: fill out this page) Loading ·- *k_ 11 1251039 A7 B7 V. Description of invention (9) It is also necessary to understand that the first and second critical ratios of pure stone eve can be identified by a two-step method. By inspection and / or theory The first and first critical ratios of the semi-pure enthalpy are determined. The thermal segment structure is then modified until the first and second critical ratios are determined experimentally and/or theoretically. The present invention provides a plurality of similar halves made from tantalum ingots. Pure single crystal germanium wafers. Each semi-pure quartz wafer has a void-rich region at the center, which contains void collectors and a pure region between the void-rich region and the edge of the wafer, which does not contain void agglomerates and interstitials. Aggregates. The gap-rich areas of each wafer are generally straight and equal. Fortunately, the pure shell area accounts for at least 36% of the wafer area. The better pure area accounts for at least 60% of the wafer area. If the V/G is tighter. In contrast, the present invention can produce a plurality of pure single crystal germanium wafers fabricated from a single germanium slave, wherein each pure germanium wafer comprises void aggregates and interstitial agglomerates. Thus, by maintaining the pulling rate against the ingot_melt The temperature gradient of the interface is between the upper and lower limits, which can limit the aggregates to the void-rich areas in the center of the wafer or eliminate the agglomerates to produce pure germanium wafers.简单 Simple description of the figure Fig. 1 is a representative diagram of the sound of the Chai Kelasji puller for growing single crystal stone ingots. ~ Figure 2 illustrates the Fronkov theory.苐3 A-3 E illustrates an overview of the fabrication of wafers with a void-rich region in the center and a pure region between the voided region and the edge of the wafer. Fields 4A-4E illustrate an overview of wafer fabrication without agglomerates. 7 paper scale applies to China National Standard (CNS) A4 specification (210 X 297 mm) (please read the note on the back: fill out this page), loading wheel · Ministry of Economic Affairs Intellectual Property Bureau employee consumption cooperative printing 12 1251039 5 OBJECT OF THE INVENTION Figure 5 illustrates an example of a money change in accordance with the present hair rate. Theory ^Decision Figure 6 illustrates a graph of the use of an axial sag pull rate as a function of the present invention. , 'X-type Figure 7 illustrates an example of a graph of the pull rate change according to the present invention. Ming Department by wafer identification experimental method Ministry of Economic Affairs Intellectual Property Bureau employee consumption cooperative printing Figure 8 illustrates the combination of simulation, chip and wafer identification for manufacturing ingots according to the present invention. Fig. 9 is a schematic representation of a perfect Shih's Chaucer puller according to the modification of the present invention. Figure 10 illustrates an example of changing the pull rate to determine the preferred pull rate in accordance with the present invention. Figure 11 is a representative view of an X-ray tomographic image illustrating the void-rich region of the first reference ingot according to the present invention, rich in interstitial regions and perfect regions. Figure 12 is a representative image of an X-ray tomography image, illustrating an example of a void-rich region of the first reference spine according to the present invention, rich in interstitial regions and a perfect region. Figures 13 and 14 illustrate plots of pull rate changes for the addition of void-filled wafers and perfect wafers in accordance with the present invention. Component label comparison table Woodcoras (CZ) puller 106 internal disaster 102' 104 heating element 1〇8 External collapse + paper scale applicable Chinese National Standard (CNS) A4 specification (210 X 297 mm) X λ L; 轴向 Axial cutting (please read the note on the back: fill out this page) ·!· -

-n / I . _輪· 13 1251039 A7 經濟部智慧財產局員工消費合作社印製 五、發明說明(11 ) 128 鑄錠 130 腔室包圍體,界面 132 冷卻口 502-514,602-612,702-712, 802-814 方塊 914 蓋 較佳具體例之詳細說明 後文將參知、附圖更詳細說明本發明,附圖顯示本發明 之較佳具體例。但本發明可以多種不同形式具體表現而不 得視為限於此處敘述的具體例;反而提供此等具體例而作 徹底完整的揭示因而完整傳遞本發明的範圍給業界人士。 全文中類似的編號表示類似的元件。 綜論··富含空隙及完美晶圓 現在參考第3A-3E圖,說明半純晶圓的製造綜論,晶 圓具有⑴於其中心之富含空隙區包含空隙集聚體,及⑺ 介於富含空隙區與晶圓邊緣間之純質區其不含空隙集聚體 及填隙集聚體。如第3A圖所示,富含空隙晶圓的製造可 始於佛隆可夫理論綜述。佛隆可夫理論圖解說明於第 圖。如始於邊緣(E)而止於中心(C)的直線顯示,發現根據 本發明右提拉速率對鑄錠熔融體表面之溫度梯度比(稱作 V/G)維持大於由邊緣E(標示為點a)擴散長度之(v/g)i而小 110 轉轴 112 第一方向 114 熱屏 120 晶體提拉軸 121 反向 124 晶種 126 火谷融多晶碎進料 ------------裝--- (請先閱讀背面之注意事:填寫本頁) . - :产紙張尺度適用中國國家標準(CNS)A4規格(210 x 297公釐) 14 1251039 經濟部智慧財產局員工消費合作社印製 A7 B7 五、發明說明(12 ) 於中心C之(V/G)2,則可製造半純晶圓其於中心具有富含 空隙區及介於富含空隙區與晶圓邊緣間具有純質區。特別 V/G可於鑄錠跨越晶圓沿徑向方向改變,由於晶圓中心及 邊緣的熱特性差異故,V/G通常由晶圓中心朝向晶圓邊緣 減低。如此特定晶圓由中心(C)至邊緣(E)出現第3A圖所示 的徑向V / G範圍。 矽鑄錠及晶圓製造上相當擔憂於晶圓内形成集聚體, 包括空隙或填隙集聚體。已知集聚體係由於最初由溶融體 製造鑄錠時形成的點瑕疵聚結形成。點瑕疵濃度通常係由 石夕鑄錠與石夕溶融體間的界面條件決定。然後隨著鑄旋的進 一步提拉’擴散及冷卻決定點瑕疲聚結而形成集聚體。 如第3B圖所示,發現根據本發明存在有臨界空隙點 瑕疵濃度[V]*及臨界填隙點瑕疵濃度[巧*,低於該濃度,點 瑕疵不會聚結形成集聚體。發現根據本發明,若點瑕疵濃 度維持低於晶圓周邊區臨界濃度,則於晶圓中心形成富含 空隙區,但介於富含晶圓區與晶圓邊緣間形成純質區。 如此如第3B圖所示’跨越晶圓空隙濃度維持低於臨 界空隙濃度[V]*,但接近中心c除外。如此如第冗圖所 示’於中心區形成富含空隙區[v] ’但富含空隙區[V]對晶 圓邊緣外側區不含空隙集聚體因此標示為[p](純或完美)。 再度參考第3B圖有關填隙,填隙濃度由晶圓中心C 至距晶圓邊緣E對應於點A的擴散長度L!維持低於臨界 填隙濃度[1]*。介於晶圓與邊緣B間之擴散長度Li,即使 填隙濃度最初高於鑄键’融體界面的臨界濃度⑴*,擴張 (請先閱讀背面之注意事:填寫本頁) —裝 15 1251039 五、發明說明(13 ) 可使填隙空隙由鑄錠擴散中 ,、月文出而於晶體增長過程不會形 聚體。擴散長度L丨對8吋日圓而_、s ^从 一 丁曰曰0而各通常約2.5至3厘米。 如此如第3C圖所示,形士士 /丄α _ “ ° /成半純日日圓於其中心具有富含处 隙區[V]及介於富含空隙區 田工 丁匕興遺緣間具有完吳區[p]。 純質區[P]至少佔晶圓面積的 口囬積的36〇/〇及更佳至少佔晶圓 的60%。 償 欲形成第3C圖的晶圓,V/G必須維料點a大於 (V/G),而於中〜C小於或等於(v/g)2。欲維持μ比介於 兩個臨界值間,必須考量兩種熱情況。第一,由晶圓中心 C至晶圓擴散長度a出現的徑向溫度梯度G必須維持於此 等值範圍内。如此,中心的V/G必須接近(v/g)2俾限制空 隙集聚體於富含空隙區。此外於距離邊緣擴散長度Ll的 WG必須維持大於(V/G)|以防填隙集聚體。如此熱區段爐 較佳設計成可維持G由晶圓中心至晶圓擴散長度之變化可 使V/G維持於(¥/(})2與(¥/(5)1間。 經濟部智慧財產局員工消費合作社印製 士第二種考量為始於晶種而止於尾當晶圓由溶融體提拉 τ G /口車由向改艾。考寺別增加鑄旋熱量,〉咸少溶融體熱量及 /、他熱考里可使G於鑄錠由熔融體提拉時下降。如此欲維 持V/G與第一及第二臨界比間,必須調整禱旋由熱區段爐 的矽熔融體提拉時的提拉速率變化曲線圖。 鑄錠提拉時經由控制V/G,可使空隙集聚體限制於接 近鑄錠軸A的富含空隙區[V],如第3D圖所示。未形成填 隙集聚體,故富含空隙區[v]外側的鑄錠區標示為[p]表示 、、屯或凡美。也如第3D圖所示,獲得多個半純晶體於其中 午紙張尺度適用中國國豕標準(CNS)A4規格(21Q X 297公釐) 1251039 五、 經濟部智慧財產局員工消費合作社印製 發明說明(14 ) 、具有包含空隙集聚體的富含空隙區 區與晶圓邊緣間富含空隙”f㈣尾触、田3工隙 田占工丨承果i體及填隙集聚體的純質區。 Μ--- (請先閱讀背面之注意事項再填寫本頁) 富含空隙區m之直徑於各晶圓相等。由單一_形成的多 個晶圓可以id編號表示,於第3D圖標示為m,通常為 標諸在每個晶圓上的文數碼。18字元域鑑別晶圓全部來自 單一鑄錠。 第3E圖示例說明當鑄錠由溶融體提拉時用來維持 V/G 於兩個臨界比間的提拉速率變化曲線圖。因〇通常-n / I . _轮· 13 1251039 A7 Ministry of Economic Affairs Intellectual Property Bureau Employees Consumption Cooperatives Printing V. Inventions (11) 128 Ingots 130 Chamber enclosures, interface 132 Cooling ports 502-514, 602-612, 702-712, 802 DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT OF THE INVENTION The present invention will be described in more detail hereinafter with reference to the accompanying drawings in which FIG. The present invention may be embodied in a variety of different forms and is not to be construed as limited to the details of the details. Similar numbers throughout the text indicate similar elements. Summary ··Enriched voids and perfect wafers Now refer to Figure 3A-3E, which illustrates the fabrication of semi-pure wafers. The wafer has (1) a void-rich region at its center containing void aggregates, and (7) The pure region rich in the void region and the edge of the wafer does not contain void aggregates and interstitial aggregates. As shown in Figure 3A, the fabrication of void-rich wafers can begin with a review of the Fronkov theory. The Fronkov theory is illustrated in the figure. As shown by the straight line starting at the edge (E) and ending at the center (C), it is found that the temperature gradient ratio (referred to as V/G) of the right draw rate to the ingot melt surface according to the present invention is maintained greater than by the edge E (marked For point a) diffusion length (v/g)i and small 110 rotation axis 112 first direction 114 heat shield 120 crystal pulling shaft 121 reverse 124 seed crystal 126 fire valley melt polycrystalline crush feed ----- -------装--- (Please read the note on the back: fill out this page) . - : The paper size applies to the Chinese National Standard (CNS) A4 specification (210 x 297 mm) 14 1251039 Ministry of Economic Affairs Intellectual Property Bureau Staff Consumer Cooperative Printed A7 B7 V. Invention Description (12) At Center C (V/G) 2, a semi-pure wafer can be fabricated which has a void-rich zone and a void-rich zone at the center. There is a pure zone between the edge of the wafer. In particular, V/G can be changed in the radial direction of the ingot across the wafer. V/G is usually reduced from the center of the wafer toward the edge of the wafer due to differences in thermal characteristics at the center and edge of the wafer. Such a specific wafer appears from the center (C) to the edge (E) in the radial V / G range shown in Fig. 3A. Tantalum ingots and wafer fabrication are of considerable concern for the formation of agglomerates within the wafer, including voids or interstitial aggregates. It is known that an agglomeration system is formed by coalescing of dots formed when an ingot is originally produced from a molten body. The point concentration is usually determined by the interface conditions between Shixi ingot and Shishi melt. Then, as the casting spin is further pulled, the diffusion and cooling determine the point of fatigue and coalescing to form an agglomerate. As shown in Fig. 3B, it was found that according to the present invention, there is a critical void point [ concentration [V]* and a critical interstitial point 瑕疵 concentration [Q], below which the point 瑕疵 does not coalesce to form an aggregate. It has been found that, according to the present invention, if the concentration of the spot is maintained below the critical concentration of the peripheral region of the wafer, a void-rich region is formed at the center of the wafer, but a pure region is formed between the wafer-rich region and the edge of the wafer. Thus, as shown in Fig. 3B, the gap density across the wafer is maintained below the critical void concentration [V]*, except for the center c. Thus, as shown in the redundancy diagram, 'the void-rich region [v] is formed in the central region but the void-rich region [V] does not contain void aggregates in the outer edge of the wafer edge and is therefore labeled as [p] (pure or perfect) . Referring again to Figure 3B for interstitial, the interstitial concentration is maintained below the critical interstitial concentration [1]* from the center of the wafer C to the diffusion length L from the edge E of the wafer corresponding to point A! The diffusion length Li between the wafer and the edge B, even if the interstitial concentration is initially higher than the critical concentration (1)* of the cast bond's melt interface, expansion (please read the note on the back: fill this page) - install 15 1251039 V. INSTRUCTIONS (13) The interstitial voids can be diffused from the ingot, and the moon will emerge without crystals during the crystal growth process. The diffusion length L 丨 is 8 吋 yen and _, s ^ is from a 曰曰 曰曰 0 and each is usually about 2.5 to 3 cm. Thus, as shown in Fig. 3C, the shape of the 士士/丄α _ " ° / semi-pure Japanese yen has a rich gap area [V] at its center and between the rich margins of the field Wu District [p]. The pure area [P] accounts for at least 36 〇 / 口 of the wafer area and preferably at least 60% of the wafer. Resolving the wafer forming the 3C pattern, V / G The dimension a must be greater than (V/G), and the middle to C is less than or equal to (v/g) 2. To maintain the μ ratio between the two critical values, two thermal conditions must be considered. The radial temperature gradient G at the wafer center C to the wafer diffusion length a must be maintained within this equivalent range. Thus, the center V/G must be close to (v/g) 2俾 to limit the void agglomerates in the void-rich In addition, the WG at the distance from the edge diffusion length L1 must be maintained greater than (V/G)| to prevent interstitial agglomerates. Such a hot segment furnace is preferably designed to maintain the change in G from wafer center to wafer diffusion length. V/G can be maintained between (¥/(})2 and (¥/(5)1. The second consideration of the Ministry of Economic Affairs Intellectual Property Bureau employee consumption cooperatives is that it starts at the seed crystal and ends at the tail. Round pulled by molten body G / Mouth from the change to Ai. The test temple does not increase the heat of the casting spin, > salt less melt heat and /, his heat test can make G fall when the ingot is pulled by the melt. So to maintain V / G Between the first and second critical ratios, it is necessary to adjust the graph of the pulling rate change when the prayer is pulled by the crucible melt of the hot section furnace. The void aggregate can be obtained by controlling V/G when the ingot is pulled up. Restricted to the void-rich region [V] close to the ingot axis A, as shown in Fig. 3D. No interstitial aggregate is formed, so the ingot region outside the void-rich region [v] is indicated by [p],屯, 凡 or 凡美. Also as shown in Figure 3D, obtain a number of semi-pure crystals at the midday paper scale for the China National Standard (CNS) A4 specification (21Q X 297 mm) 1251039 V. Ministry of Economic Affairs Intellectual Property Bureau Employees' Consumer Cooperatives Printed Inventions (14), with a void-rich zone containing void agglomerates and a gap between the edges of the wafer. f(4) Tail Touch, Field 3 Gap Fields, Occupational Fruits, and Interstitial Gathering The pure area of the body. Μ--- (Please read the note on the back and fill in this page) The diameter of the gap is m. Equivalent. A plurality of wafers formed by a single _ may be represented by an id number, and the 3D icon is shown as m, which is usually a text number marked on each wafer. The 18-character domain identification wafers are all from a single ingot. Figure 3E illustrates a plot of the pull rate change used to maintain V/G between two critical ratios when the ingot is pulled from the melt.

Ik耆鑄錠由溶融體的提拉減小,通常減慢提拉速率v來維Ik耆 ingots are reduced by the pulling of the melt, usually slowing down the pulling rate v

持WG介於兩個臨界比間。欲獲得預期的加工變化,V/G 車乂仏、准持於第一與第二臨界比中途。如此較佳維持防護帶 以容許加工變化。 綜論:純矽晶圓 第4A-4E圖對應於第3A-3E圖示例說明控制提拉速率 :成純石夕鑄旋及晶圓。如第4A圖所示,若v/g維持介於 :圓中心C與距晶圓邊緣E的擴散長度a間較緊密的公差 範圍内則可於整個晶圓防止形成空隙集聚體及填隙集聚 ^如此如第4B圖所示,於晶圓中心(鑄錠軸A),v/g比 維持低於可形成空隙集聚體的臨界比(V/G)2。同理V/G維 持n於可形成填隙集聚體的臨界比(v/g)i。如此形成第 圖的、、、屯石夕[P]其不含填隙集聚體及空隙集聚體。純缚鍵連同 一種純晶圓顯示於第4D圖。純石夕的提拉速率變化曲線圖 顯示於第4E圖。 X 297公釐) t紙張尺度中國] 17 051039Holding WG is between two critical ratios. In order to obtain the expected processing changes, the V/G rut is in the middle of the first and second critical ratios. It is thus preferable to maintain the guard band to allow for processing variations. Summary: Pure germanium wafers Figures 4A-4E correspond to the 3A-3E diagram illustrating the control of the pull rate: pure stone casting and wafer. As shown in Fig. 4A, if v/g is maintained within a tight tolerance between the center C of the circle and the diffusion length a from the edge E of the wafer, void formation and interstitial accumulation can be prevented throughout the wafer. ^ As shown in Fig. 4B, at the wafer center (ingot axis A), the v/g ratio is maintained below the critical ratio (V/G) 2 at which the void collector can be formed. Similarly, V/G maintains a critical ratio (v/g)i that can form a gap-filled agglomerate. Thus, the formation of the figure, 屯石夕 [P] does not contain interstitial aggregates and void agglomerates. The pure bond is shown in Figure 4D along with a pure wafer. The graph of the pull rate change of pure Shi Xi is shown in Fig. 4E. X 297 mm) t paper scale China] 17 051039

提拉速率變化曲線圖之決定 根據本發明欲形成於中心具有富含空隙區及介於富含 空隙區與晶圓邊緣間具有純質區的半純晶圓,決定提拉速 率變化曲線圖(第3E圖)可於鑄錠由熱區段爐之矽熔融= 提拉時,維持提拉速率對鑄錠之溫度梯度比高於第一臨界 比而低於第二臨界比。同理,欲形成包含點瑕疵但不含空 隙集聚體及填隙集聚體的純矽,決定提拉速率變化曲線圖 (第4E圖)當由熱區段爐之矽熔融體提拉鑄錠時,可維持提 拉速率對溫度梯度比高於第一臨界比而低於第二臨界比。 現在說明提拉速率變化曲線圖之決定。 提拉速率變化曲線圖可藉模擬以理論方式決定,經由 軸向切片參考鑄錠以實驗方式決定,經由將參考鑄旋切片 成晶圓以實驗方式決定或經由此等技術的組合決定。此外 純石夕之提拉速率變化曲線圖可經由首先決定半純石夕之提拉 速率變化曲線圖然後修改熱區段結構獲得純矽的提拉速率 變化曲線圖決定。現在敘述此等技術。 (請先閱讀背面之注意事^填寫本頁)The determination of the pull rate change graph according to the present invention is to form a semi-pure wafer having a void-rich region at the center and a pure region between the void-rich region and the edge of the wafer, and determining a pull rate change graph ( Fig. 3E) The temperature gradient ratio of the pulling rate to the ingot is maintained to be higher than the first critical ratio and lower than the second critical ratio when the ingot is melted by the hot zone furnace. Similarly, in order to form a pure crucible containing a point enthalpy but no void agglomerates and interstitial aggregates, the graph of the pulling rate change (Fig. 4E) is determined when the ingot is pulled by the crucible melt of the hot section furnace. The pull rate to temperature gradient ratio is maintained above the first critical ratio and below the second critical ratio. The decision of the pull rate change graph will now be described. The pull rate change profile can be determined theoretically by simulation, experimentally determined via axial slice reference ingots, experimentally determined by slicing the reference spins into wafers, or determined by a combination of such techniques. In addition, the curve of the pull rate of the pure stone can be determined by first determining the pull rate curve of the semi-pure stone and then modifying the heat segment structure to obtain the pure pull rate curve. These techniques are now described. (Please read the note on the back first) Fill in this page)

I 裝 _ 經濟部智慧財產局員工消費合作社印製I 装 _ Ministry of Economic Affairs Intellectual Property Bureau employee consumption cooperative printing

藉模擬所得提拉速率變化曲線圖 參考第5圖,現在說明藉模擬理論決定提拉速率變化 曲線圖。如第5圖所示,商業模擬軟體可用來模擬於方塊 502之V/G變化(稱作。然後於方塊5〇4決定由中 心至距邊緣的擴散長度Ll之V/G變化是否夠小而可滿足 形成半純晶圓或純晶圓的標準。特別對第3C圖示例說明 本紙張尺度適用中國國家標準(CNS)A4規格(210 X 297公髮) 18 1251039 A7 五、發明說明(16 ) 之具有富含空隙區之矽而言,介於晶圓半徑d與半徑a間 各區之Δ(ν/〇必須介於(V/G)丨與(V/G) 2。換言之,填隙 點瑕疵濃度對晶圓介於中心c與a間的半徑須小於[巧*, 而工隙點,辰度大於d之晶圓半徑而言須小於[V] *。同理如 第4圖所示,欲形成純矽,Δ(ν/(})須小於或等於(v/⑺^ 減(V/G) 1俾維持[V]低於臨界濃度[V]*,對由中心c至擴 政距離a之全部半徑而言也須維持⑴低於臨界濃度[〗]*。 繼鉍5兒明第5圖,於方塊5〇4,若於方塊5〇2決定的 V/G徑向變化過大而滿足半純晶圓或純晶圓的條件(第 及4D圖),則熱區段可於方塊5〇6修改並再度模擬直到梯 度夠小而可滿^期望條件為止。特別如第9圖所示,熱區 段可如下修改,添加蓋914至熱4 114,以保熱材料如碳 化亞鐵填滿蓋914與熱區段屏114間的空間。可作其他熱 區段修改來視需要減少溫度梯度。 再度參考第5圖,於方塊5〇8進行V/G軸向變化模 而決定當鑄錠提拉時的△(,變化。再度於方塊51〇實 瞭解變化是否夠小而可於晶圓增長時維持期望特性々 否,則熱區段於方塊506修改。然後於方塊512,決定提 拉速率變化曲線圖而維持臨界v/(},如第^或犯圖所示。 然後使用此種❹料於方塊514製輯錠。較佳提拉速 率變化曲線圖用於方塊512可維持V/G介於兩個臨界比 中途’因而維持防護帶而可考慮典型的製程變化。 之 注 擬 若 的 經由軸向切片之提拉速率變化曲 線圖 g紙張尺錢财關家標準(cns)A4 19 五 發明說明(Π ) 現在參考第6圖’說明使用轴 提,",圖所示.參考轉―心= :率提拉。欲測定較佳提拉速率,如第,。圓所示使用= 速率範圍。如第10圖所示,提拉速率由高提拉速率⑷ ^•2毫綺鐘調整至低提拉速率⑷Q5毫米/分鐘及返回 呵提拉速率。低提拉速率可低抵0.4毫米/分鐘或以下。提 拉速率(b)及⑷變化較佳為線性變化。可生產具有第"及 12圖所示剖面的鑄m1及12圖分別示例說明禱鍵之 富含空隙區’富含填隙區及完美區[v],m及[p]。業界人 士瞭解此等區具有第n及12圖之線圖未顯示的各種华聚 體濃度。 ^ 回頭參考第6圖,鑄錠於方塊6〇4軸向切片。如此參 照第11圖,對半純矽而言,鑄錠沿軸向切片,使用習知技 術如銅裝飾,Secc〇-蝕刻,X光斷層掃描分析,壽命測量 及其他習知技術測量軸向切片的集聚體濃度。較佳於集聚 體沿軸向切割,進行鏡蝕刻及於氮氣氛下於8〇(rc退火4 小時及於1000°C退火16小時後測量壽命。如第u圖所 示,軸向位置P!具有大的富含空隙區及相對小的完美區。 軸向位置P2具有較小的富含空隙區及較大的完美區。軸向 位置P3具有隶小可能的富含空隙區及最大可能的完美 區,但未引進富含填隙集聚體區。軸向位置p4具有極小的 富含空隙區但有大的富含填隙區,此乃非期望者。如此於 方塊608,基於沿第11圖軸向位置對軸向位置p3決定 V/G。於方塊610,當晶圓提拉時對此位置p3決定可滿足 -20 - 本紙張尺度適用中國國家標準(CNS)A4規格(210 X 297公釐) 經濟部智慧財產局員工消費合作社印製The graph of the pull rate change by simulation is shown in Fig. 5. Now, the graph of the pull rate change is determined by the simulation theory. As shown in Fig. 5, the commercial simulation software can be used to simulate the V/G variation of block 502 (referred to as. Then, at block 5〇4, it is determined whether the V/G variation from the center to the edge diffusion length L1 is small enough. Can meet the criteria for forming semi-pure wafers or pure wafers. Especially for the example of Figure 3C, this paper scale applies to China National Standard (CNS) A4 specification (210 X 297 mil) 18 1251039 A7 V. Invention Description (16 In the case of a region rich in voids, the Δ between the wafer radius d and the radius a (ν/〇 must be between (V/G) 丨 and (V/G) 2. In other words, fill The 瑕疵 point concentration must be less than [Q] * for the wafer between the centers c and a, and the groove radius should be less than [V] * for the wafer radius greater than d. Similarly, as shown in Figure 4. As shown, to form pure enthalpy, Δ(ν/(}) must be less than or equal to (v/(7)^ minus (V/G) 1俾 maintain [V] below the critical concentration [V]*, from center c to The full extent of the expansion distance a must also be maintained (1) below the critical concentration [〗]*. Follow the 5th picture of the 5th, at block 5〇4, if the V/G radial is determined at block 5〇2. Change too large to meet semi-pure wafers or The condition of the wafer (Fig. 4D), the hot section can be modified at block 5〇6 and re-simulated until the gradient is small enough to meet the desired condition. Particularly as shown in Fig. 9, the hot section can be as follows Modify, add cover 914 to heat 4 114 to fill the space between cover 914 and hot section screen 114 with a heat retaining material such as ferrous carbide. Other hot section modifications may be made to reduce the temperature gradient as needed. In the figure, the V/G axial change mode is performed at block 5〇8 to determine the Δ((change) when the ingot is pulled. Again, at block 51, it is understood whether the change is small enough to maintain the desired characteristics as the wafer grows. If not, then the hot section is modified at block 506. Then at block 512, the pull rate profile is determined to maintain the critical v/(} as shown in the figure or the map. Then use this trick at block 514. Ingots. The preferred pull rate curve is used in block 512 to maintain V/G midway between the two critical ratios' thus maintaining the guard band and considering typical process variations. Lifting rate change graph g paper ruler money and money standard (cns) A4 19 V. INSTRUCTIONS (Π) Now refer to Fig. 6 'Description of the use of the shaft, ", as shown in the figure. Reference to the heart =: rate pull. To determine the preferred pull rate, such as the first. The use = rate range. As shown in Figure 10, the pull rate is adjusted from a high pull rate (4) ^•2 milliseconds to a low pull rate (4) Q5 mm/min and a pullback pull rate. Low to 0.4 mm/min or less. The change of the pulling rate (b) and (4) is preferably linear. The cast m1 and 12 drawings with the profiles shown in the first and the 12th are respectively illustrated as examples of the enrichment of the prayer key. The void region is rich in interstitial and perfect regions [v], m and [p]. Industry insiders understand the concentration of various oligomers in these areas that are not shown in the line diagrams in Figures n and 12. ^ Referring back to Figure 6, the ingot is sliced in the axial direction of the block 6〇4. Thus, referring to Fig. 11, for semi-pure sputum, the ingot is sliced in the axial direction, and the axial section is measured using conventional techniques such as copper decoration, Secc〇-etching, X-ray tomography analysis, life measurement, and other conventional techniques. Aggregate concentration. Preferably, the agglomerates are cut in the axial direction, mirror-etched and measured at 8 Torr under nitrogen atmosphere (arc annealing for 4 hours and annealing at 1000 ° C for 16 hours). As shown in Fig. u, the axial position P! It has a large void-rich zone and a relatively small perfect zone. The axial position P2 has a small void-rich zone and a large perfect zone. The axial position P3 has a small gap-rich zone and the largest possible Perfect zone, but no rich interstitial agglomerate zone is introduced. The axial position p4 has a very small void-rich zone but a large rich interstitial zone, which is undesirable. Thus at block 608, based on the eleventh The axial position of the figure determines the V/G for the axial position p3. At block 610, the position p3 is determined to be satisfied when the wafer is pulled. -20 - The paper size applies to the Chinese National Standard (CNS) A4 specification (210 X 297) Gong) Printed by the Ministry of Economic Affairs Intellectual Property Bureau employee consumption cooperative

1251039 A7 B7 五、發明說明(18 ) 依據的提拉速率變化曲線圖然後製造鑄旋。 業界人士需瞭解軸向位置P3未用於真正生產,原因為 製程變化造成填隙區增長。如此可選定位置?2與P3間的 轴向位置而無論製程如何變化,可包含可接受的小型富含 空隙區而未引進填隙集聚體。 軸向鑄錠切片也可對熱區段提拉的鑄錠進行,該熱區 段设計供純矽使用。此種鑄錠顯示於第12圖。如同第U 圖,顯示富含空隙區,完美區及富含填隙區[v],m及[P]。 如第12圖所示,車由向位置1VPio包含類似帛11 ®所示富 5工隙中〜區。位置P?及P⑺包含富含填隙環及完美中 仁位置P6及p9皆完美,原因為於中心不含空隙而於 故、、彖不3填隙。如此於方塊6〇6,選定對應於位置h或P9 的軸向位置及於方塊6〇8對此轴向位置決定v/G。可維持 此種V/G的提拉速率變化曲線圖係於方塊61〇決定,鑄錠 係於方塊612增長。業界人士需瞭解可選擇就鄰位置& 及P9的軸向位置範圍而生產純矽。如此可選擇真正v/g 許可製程變化同時仍可維持完美矽特性。 藉晶圓鑑別決定提拉速率變化曲線圖 現在參照第7圖說明藉晶圓鑑別實驗決定提拉速率變 ,曲線圖。如第7圖所示,參考鑄錠係於方塊術以不等 提拉速率提拉。欲決定較佳提拉速率變化曲線圖,如第⑺ 圖所述較佳使用某種提拉速率範圍。例如提拉速率由高提 拉速率⑷(此處4 12冑米/分鐘)調整至低提拉速率^1251039 A7 B7 V. INSTRUCTION DESCRIPTION (18) Based on the graph of the pull rate change, then the casting spin is produced. The industry needs to understand that the axial position P3 is not used for real production because the process variation causes the interstitial zone to grow. So can I choose a location? The axial position between 2 and P3, regardless of process variations, may include acceptable small void-rich zones without the introduction of interstitial aggregates. The axial ingot slicing can also be carried out on ingots that are pulled up in the hot section, which is designed for use in pure crucibles. Such an ingot is shown in Figure 12. As shown in Figure U, it shows the void-rich zone, the perfect zone and the interstitial zone [v], m and [P]. As shown in Fig. 12, the car consists of a zone 5 in the rich position of the VP11-like position shown in the position 1VPio. The positions P? and P(7) contain a rich interstitial ring and the perfect middle position P6 and p9 are perfect because the center does not contain voids, and the gap is not filled. Thus at block 6〇6, the axial position corresponding to position h or P9 is selected and at block 6〇8 the v/G is determined for this axial position. The pull rate profile of such a V/G can be maintained at block 61, and the ingot is grown at block 612. The industry needs to know that pure 矽 can be produced by selecting the axial position range of the adjacent position & and P9. This allows for true v/g licensing process changes while maintaining perfect flaws. Determining the pull rate change curve by wafer identification Now, referring to Fig. 7, the pull rate change experiment and the graph are determined by the wafer identification experiment. As shown in Figure 7, the reference ingot is tied to the cube at a pull rate. To determine the preferred pull rate profile, a certain pull rate range is preferred as described in Figure (7). For example, the pull rate is adjusted from a high pull rate (4) (here 4 12 胄 m / min) to a low pull rate ^

$紙張尺錢财關格(21Qx297公爱 1251039$ paper ruler money relationship (21Qx297 public love 1251039

宅米/分鐘及返回高提拉速率。低提拉速率可低抵U毫米 /分鐘或以下。提拉速率(b)及⑷之變化較佳為線性。可生 產具有第11或第12圖所示剖面的鑄錠。 回頭參考第7圖,鑄旋於方塊7〇4沿經向方向切片而 生產多片晶圓。如此參考第11圖,對半純矽而言,鑄錠姐 切片而提供代表性晶圓W1_W4。然後使用f知技術測= 等晶圓的集聚體濃度,例如銅裝飾,secco蝕刻,壽命測 量或其他習知技術。如s u圖所示,晶圓W1具有大^ 含空隙區及相對小完美區。晶圓W2具有較小富含空隙: 及較大完美區。晶K w3具有最小可能的富含空隙區及最 大可能的完美區而未引進富含填隙集聚體區。曰曰曰s %具 有極小的富含空隙區但具有大的富含填隙區此乃非:望 值。如此於方塊708,基於晶圓沿第3圖禱鍵的轴向位置 決定晶圓1的WG。於方塊71G,決^當晶圓提拉時此晶 圓W3的提拉速率變化曲線圖,然後製造鑄錠。 經濟部智慧財產局員工消費合作社印製 業界人士須瞭解晶圓W3的軸向位置未用於真正生 產,原因為製程變化可能造成填隙區增長。如此介於晶圓 W3及晶圓W2間的晶圓軸向位置可經選定而包含可接受的 小型富含空隙區,但未引進填隙集聚體且與製程變化無 關。晶圓切片也可於設計用於完美矽的熱區段提拉的鑄錠 進行。此種鑄錠顯示於第12圖。如同第u圖,顯示富含 空隙區,完美區及富含填隙區[V],[巧及[p]。如第12圖所 不可生產多片晶圓Ws及W10。晶圓W5及Wi〇類似第^ 圖所示包含富含空隙的中心區。晶圓w?及Ws包含富含填 22 1251039 A7 ----------B7 _ 五、發明說明(2〇 ) "' 隙環及完美中心。但晶圓WdW9皆完美,原因為中心不 含空隙而邊緣不含填隙。如此於方塊706,選定對應於晶 H W64 w9的軸向位置,及於方塊7〇8對此轴向位置決定 V/G。於方塊710決定維持此種V/G的提拉速率變化曲線 圖’及於方塊712製造鑄錠。業界人士需瞭解可選擇田比鄰 位置w6及w9的某個晶圓位置範圍而生產石夕。如此選擇真 正V/G而許可多種製程變化同時維持完美矽特性。 瘦1驗及模氣技髮^定提拉速率 現在參考第8圖,使用模擬、軸向切片及晶圓鑑別的 組合俾製造本發明之鑄錠。如第8圖方塊8〇2所示,模擬 可用以決定某種提拉速率範圍。於方塊8〇4,可增長多個 參考鑄錠。若干的鑄錠係於方塊8〇6沿軸向切片,而若干 鑄錠係於方塊808切片成晶圓。經由於方塊81〇求出軸向 切片、晶圓鑑別與模擬結果的交互關係決定最佳v/g。然 後於方塊812決定提拉速率及於方塊814製造鑄錠。此種 過程進行兩次獲得純矽,故於獲得半純矽後視需要可修改 熱區段。 經濟部智慧財產局員工消費合作社印製 真正提拉速率將隨多種變數而定,變數包含但非僅限 於鑄旋直徑’使用特定熱區段爐及矽熔融體品質。第13 及14圖示例說明使用模擬與實驗技術組合決定的提拉速 率變化曲線圖(第8圖)。第13圖示例說明增長長ι〇〇厘米、 直徑200毫米鑄錠之提拉速率變化曲線圖而形成直徑12 厘求的富含空隙區及提供純矽區佔64%面積。使用三菱材 料公司製造的型號Q41熱區段爐。第14圖示例說明使用 本紙張尺度適用中國國家標準(CNS)A4規格(210 X 297公釐) 23 1251039 A7Home meter/minute and return high pull rate. The low pull rate can be as low as U mm / min or less. The change in the pull rate (b) and (4) is preferably linear. An ingot having a cross section as shown in Fig. 11 or Fig. 12 can be produced. Referring back to Figure 7, a plurality of wafers are produced by slicing in the warp direction at block 7〇4. Referring to Figure 11, for the semi-pure, the ingot is sliced to provide a representative wafer W1_W4. The aggregate concentration of the wafer, such as copper decoration, secco etching, lifetime measurement or other conventional techniques, is then measured using a known technique. As shown in the figure, the wafer W1 has a large void area and a relatively small perfect area. Wafer W2 has a smaller void-rich: and a larger perfect zone. Crystal K w3 has the smallest possible void-rich region and the most probable perfect region without introducing a region rich in interstitial aggregates.曰曰曰s % has a very small void-rich zone but has a large interstitial-rich zone. Thus at block 708, the WG of wafer 1 is determined based on the axial position of the wafer along the prayer key of FIG. At block 71G, a plot of the pull rate of the wafer W3 as the wafer is pulled is determined, and then the ingot is fabricated. Printed by the Consumer Intellectual Property Office of the Ministry of Economic Affairs. The industry insiders must understand that the axial position of the wafer W3 is not used for real production because process variations may cause the interstitial zone to grow. Thus, the axial position of the wafer between wafer W3 and wafer W2 can be selected to include acceptable small void-rich regions, but no interstitial aggregates are introduced and are independent of process variations. Wafer slicing can also be performed on ingots designed for use in the hot section of a perfect crucible. Such an ingot is shown in Figure 12. As shown in Figure u, it shows the void-rich zone, the perfect zone and the interstitial zone [V], [Q and [p]. As shown in Fig. 12, it is not possible to produce a plurality of wafers Ws and W10. Wafers W5 and Wi〇 are similar to those shown in the figure, including a void-rich central region. Wafer w? and Ws contain rich fill 22 1251039 A7 ---------- B7 _ five, invention description (2 〇 ) " 'gap ring and perfect center. However, the wafer WdW9 is perfect because the center does not contain voids and the edges do not contain gaps. Thus at block 706, the axial position corresponding to the crystal H W64 w9 is selected, and at block 7 〇 8 the V/G is determined for this axial position. At block 710, a pull rate change graph for maintaining such V/G is determined and the ingot is fabricated at block 712. Industry insiders need to know how to select a wafer location range in the field of W6 and w9 to produce Shi Xi. This selects true V/G and allows for multiple process changes while maintaining perfect 矽 characteristics. The thin 1 test and the mold technique are used to determine the pull rate. Referring now to Fig. 8, the ingot of the present invention is produced using a combination of simulation, axial slicing and wafer identification. As shown in Figure 8 and Figure 8 of Figure 8, the simulation can be used to determine a certain range of pull rates. At block 8〇4, multiple reference ingots can be grown. A number of ingots are sliced in the axial direction at block 8〇6, and a number of ingots are sliced into wafers at block 808. The optimal v/g is determined by the interaction of the axial slice, wafer identification and simulation results as determined by block 81. The pull rate is then determined at block 812 and the ingot is fabricated at block 814. This process is carried out twice to obtain a pure enthalpy, so that the heat section can be modified as needed to obtain a semi-pure enthalpy. Printed by the Intellectual Property Office of the Ministry of Economic Affairs, the Consumer Cooperatives. The true pull rate will vary depending on a number of variables, including but not limited to the diameter of the casting spin' using a specific hot zone furnace and the melt quality of the crucible. Figures 13 and 14 illustrate a plot of the pull rate change determined using a combination of simulation and experimental techniques (Figure 8). Figure 13 illustrates a plot of the pull rate of a growing ι 〇〇 cm, diameter 200 mm ingot to form a void-rich zone with a diameter of 12 PCT and a pure 矽 zone of 64%. A model Q41 hot section furnace manufactured by Mitsubishi Materials Corporation was used. Figure 14 illustrates the use of this paper scale for the Chinese National Standard (CNS) A4 specification (210 X 297 mm) 23 1251039 A7

先 閱 讀 背 面 之 注 意 事 m 填 寫驻 本衣 頁 訂First read the back of the note, m fill in the clothes page

Claims (1)

12510391251039 A8 B8 C8 D8 97公釐) 各 曰曰 出A8 B8 C8 D8 97 mm) 六、申請專利範圍 ι·:種半純質單晶權,其係由單一個發 各個半純質單晶石夕晶圓於其中心處均—衣成, 集聚體的富含空隙區’及一介於該富含空隙區::空隙 緣間之不含空隙集聚體及填隙集聚體的純質區::回, 圓的富含空隙區的直徑相等。 曰曰 2·如申請專利範圍第W之半純質單晶石夕晶圓, 晶圓上又包含鑑別指標,位在各 此, 個日日圓上之鑑別指標禆 才曰出各個晶圓係由單一個矽鑄錠所製成。 、’、 3·如申請專利範圍第i項之半純質單晶石夕晶圓,…個 晶圓具有相等的晶圓面積,及其中 ° Τ 口曰曰圓的純質區至少 佔晶圓面積的36%。 4_ :申請專利範圍第3項之半純質單晶石夕晶圓,其中各個 日日圓之純質區至少佔晶圓面積之6〇%。 5·-種純質單晶^圓’其係由單_個料錠所製成, 個純質單晶石夕晶圓不含有空隙集聚體及填隙集聚體。 •如申請專利範圍第3項之純質單晶矽晶圓,其中各個 ®上又包含鑑別指標,位在各晶圓上之鑑別指標係指 各個晶圓係由單一矽鑄錠所製成。 7·=種增長單晶砍鑄鍵之柴可拉斯基(a。如㈣提拉 為’其包含: 一包圍體; 一位於該包圍體内之坩堝; 位在β亥包圍體内之晶體提拉輛,其具有一轴線及 一鄰接該掛瑪之軸端; ^ 張尺度適_ 1251039Sixth, the scope of application for patents ι·: a kind of semi-pure single crystal weight, which is made up of a single semi-pure single crystal stone wafer at its center, the enriched void area of the aggregate A pure region between the void-rich region: the void-free agglomerate and the interstitial aggregate:: back, the rounded void-rich region has the same diameter.曰曰2·If you apply for the patent scope of the first half of the pure single crystal stone wafer, the wafer also contains the identification index, which is located in each, the identification index on the daily yen will be used to extract the wafers. Made from a single ingot casting. , ', 3 · For example, the semi-pure single crystal wafer of the i-th patent scope of the patent application, ... the wafer has an equal wafer area, and the pure region of the middle and the round is at least the wafer 36% of the area. 4_ : Apply for the semi-pure monocrystalline single crystal wafer of item 3 of the patent scope, in which the pure area of each Japanese yen accounts for at least 6〇% of the wafer area. 5·-a pure single crystal ^ round' is made of a single ingot, and the pure single crystal silicon wafer does not contain void aggregates and interstitial aggregates. • For example, the pure single crystal germanium wafers in the third paragraph of the patent application, each of which contains an identification index, and the identification index on each wafer means that each wafer is made of a single tantalum ingot. 7·=Growth growth single crystal cut casting bond of the Chailasaki (a. Such as (four) lifted as 'which contains: a bounding body; a beak inside the surrounding body; crystal in the body surrounded by β Hai a pulling vehicle having an axis and an axial end adjacent to the hanging horse; ^ Zhang scale suitable _ 1251039 、申請專利範園 用以將該軸沿軸向拉離坩堝之裝置; 禍周個加熱器’其位於該包圍體内且圍繞於該增 一罢一:於該料與晶體提拉轴間之熱屏,其一端包含 盍,蓋内包封有一保熱材料。 δ·如申請專利範圍第7項之柴可拉斯基提拉器: ★,其中该熱屏為-介於該㈣與晶體提拉軸間之圓 、土幵/熱屏’该熱屏m向由鄰接的第—端延伸至 遠離掛堝的第二端;以及 其中該蓋係位於圓柱形熱屏之第一端。 9.如申請專利範圍第8項之柴可拉斯基提拉器,其中該保 熱材料為碳化亞鐵。 -26 本紙張尺度適用中國國家標準(〇jS) A4規格(210X297公釐)Applying for a patented garden to pull the shaft axially away from the device; the surrounding heater is located in the enclosure and surrounds the addition: between the material and the crystal pulling shaft The heat shield has a crucible at one end and a heat retaining material inside the cover. δ·If the application of the scope of the patent scope item 7 is the Chaucer base puller: ★, wherein the heat screen is - between the (four) and the crystal pulling shaft, the soil / heat screen 'the heat screen m Extending from a first end adjacent to a second end remote from the hanger; and wherein the cover is located at a first end of the cylindrical heat shield. 9. A Chaucer base puller according to claim 8 wherein the heat retaining material is ferrous carbide. -26 This paper scale applies to Chinese national standard (〇jS) A4 specification (210X297 mm) ........................袭...... (請先閲讀背面之注意事項窝本頁) 、盯— •線:丨丨_........................attack... (Please read the note on the back of the page first), stare at – line: 丨丨_
TW91115554A 1997-02-13 1998-02-06 Semi-pure monocrystalline silicon wafers, pure monocrystalline silicon wafers and a Czochralski puller TWI251039B (en)

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KR19970004291 1997-02-13
KR1019970054899A KR19980070037A (en) 1997-02-13 1997-10-24 Optimization method of pulling rate of seed crystal during semiconductor ingot growth, semiconductor ingot growth method using the same, semiconductor ingot and semiconductor wafer and semiconductor device grown accordingly

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