TWI250589B - Method for improving doping profile of lightly doped source/drain - Google Patents

Method for improving doping profile of lightly doped source/drain Download PDF

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TWI250589B
TWI250589B TW93140949A TW93140949A TWI250589B TW I250589 B TWI250589 B TW I250589B TW 93140949 A TW93140949 A TW 93140949A TW 93140949 A TW93140949 A TW 93140949A TW I250589 B TWI250589 B TW I250589B
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lightly doped
sacrificial layer
semiconductor substrate
layer
improving
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TW93140949A
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Chinese (zh)
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TW200623279A (en
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Yun-Jun Huh
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Grace Semiconductor Mfg Corp
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Abstract

The present invention disclose a method for improving doping profile of lightly doped source/drain, which employs the wet etching on the lining layer and the lightly doped sacrifice layer after dry etching; then, employing the isotropic etching theorem of wet etching to form a residual lining layer and a residual lightly doped sacrifice layer; next, employing the gate structure, the residual lining layer and the residual lightly doped layer as a mask for conducting the source/drain doping process with lower density; and, conducting the doping atom diffusion driving to obtain a lightly source/drain extension doping region with better inclined profile.

Description

1250589 五、發明說明(1) 【發明所屬之技術領域】 本發明係關於一種對、、原/ 方Φ认 對/原人及極區域進行輕離子摻雜的 方法特別疋關於一種能夠適用於製程尺寸進入 後之=成較佳源/沒極輕離子摻雜輪廓的方法。 放未 【先前技術】1250589 V. INSTRUCTION DESCRIPTION OF THE INVENTION (1) Technical Field of the Invention The present invention relates to a method for performing light ion doping of a pair, an original/square Φ pair, an original person, and a polar region, particularly regarding a process that can be applied to a process. A method of forming a preferred source/no very light ion doping profile after size entry. Unreleased [previous technology]

當半導體元件為生盡、隹λ d subiearOtil ’ 到深次微米(deeP —η)來有效降低=輕f雜汲極(11卸y d_d 長度變短時,將產/通When the semiconductor element is born, 隹λ d subiearOtil ′ to deep sub-micron (deeP — η) to effectively reduce = light f-heterogeneous pole (11 unloading y d_d length becomes shorter, will be produced / pass

下方為高電場區域因此最一 相對冒大,而閘極邊壁的正 子注人邊壁將造成輕摻;電游離現象’此時熱電 增加,造成LDD特有的劣化模式&域產生空乏,而導致電阻 因此,由於LDD雷曰舰、皇L 區域進行回火時, 對此輕摻雜汲極 產生上述問題,為了 體+邊土下方的輕摻雜汲極區域會 Over lap LDD電晶體姓槿、乂個問題,所以發展出Gate 長度延至閘極結構下I ,糟由將輕摻雜汲極區域之延伸 極延伸區域14,使電曰,利用閘極結構10下方之輕摻雜汲 摻雜汲極區域累積電$體運作時施加在閘極的正電壓使輕 法注入邊壁,來達到右j而使得電阻降低,使熱電子將無 請參閱第一圖所示政的抑制晦有的劣化模式。 極結構1 0 (有時也奋:,Gate 0ver lap LDD係採用利用閘 )為LDD製程時的離胃子加入修補閘極蝕刻損傷的氧化層j 2 雜汲極區域輪廓將直入罩幕,此種方式所形成之輕摻 反u — 弟—f A)圖所示 、為離子濃度與接受到的熱驅動能量The lower part is the high electric field, so the most relatively large, and the positive side of the gate side wall will cause light mixing; the electric free phenomenon' at this time the thermoelectricity increases, causing LDD-specific degradation mode & the domain is depleted, and As a result, the light-doped bungee has the above problem due to the tempering of the LDD Thunder Ship and the Emperor L region. For the lightly doped bungee region below the body + side soil, the Overlap LDD transistor surname is 槿乂 乂 , , , , , , , , 所以 所以 所以 所以 所以 G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G The positive voltage applied to the gate during the operation of the drain region allows the light method to be injected into the side wall to reach the right j, so that the resistance is lowered, so that the hot electrons will be absent. Please refer to the suppression shown in the first figure. Degradation mode. The pole structure 10 (sometimes also: the Gate 0ver lap LDD system uses the gate) for the LDD process to add the oxide layer of the etched gate to the etched gate. The outline of the hybrid region will go straight into the mask. The light-doped anti-u-di-f A) pattern formed by the method shows the ion concentration and the received thermal driving energy.

第5頁 1250589 五、發明說明(2)-- 使的輕摻雜汲極區 雜汲極區域t M ^ 輪廓形成如第二(β)圖所f & 知的製程ίί伸輪靡,由第二(B)圖中=之輕摻 J ^ ^無法形成6 M ^可明顯發現習 深次微米,如此不1的傾斜狀延伸輪廓,且當製程、隹 效應的改善並不完善控制的延伸區輪廓對短通道及熱電^ 因此,本發明总 雜輪廓的方法:來解:對上述問題提出-種改善淺籬子 【發明内ίί應的改善不完善的缺失。 T對短通 本發明之主要 極之摻雜輪廓的方、I在於提供一種改善輕摻雜源/沒 進行濕式蝕刻,使复,,、係利用對襯底層與輕摻雜犧牲屏 供續利用閘士 刹餘輕摻雜犧锉 為罩幕,來i%彳-_〜構、剩餘襯底層與剩餘輕摻雜g ^ Ϊ 極輕離子ί;仃輕摻雜及極製程,以獲得—,2犧牲層 :于摻雜輪廓。 行#又佳的源/汲 本發明之另— 極之摻雜於 目的’在於提供一種改盖知4Α 次婵丄輪庵的方法,J:处私士 t 又善輕摻雜源/汲 微:製程後無法;得的改善習知製程進入深 極之摻雜輪ί:―目的,在於提供-種改C缺失。 化下的所產::方* ’其能夠有效避免元;雜源/汲 I本發明之^ Ϊ通道及熱電子效應。 尺寸逐漸微小 J摻雜輪廓的=霄施態樣為提供- #改善和換Μ 區蜮之半導辦I法,其首先提供一内係形成=雜源/沒極 基底;在半導體基底上形成—數個隔-離 ^〜匕含一閘氧化 第6頁 1250589 — —— 五、發明說明(3) |層及其上方之多晶矽層的電 ^〜 丨對該輕摻雜犧牲岸愈:極、、、。構側壁形成-輕摻:二f基底 I穆雜犧牲層與―二::襯底層進行触刻,以形:犧牲層; h層與剩餘氧層進…閘極= 丨一輕,雜=以的離子乂 丨數個隔#區域•導二=樣為首先提供-#内係… 丨閉極結構,a包:基底;於半導體基底上炉成士成有複 ί極結構側壁形ί二二閘氧化層及其上方之多晶ί二電晶體 刻,以形&輕摻雜犧牲層,·對輕# # 日,於閘 以升y成一剩餘輕早杉雜犧牲層進 犧牲層為罩幕,、p 犧牲層,以閘極結構鱼兮± : 底内开…:進行一低濃度的離子佈植,Γ ί輕摻雜 I 二成輕摻雜源/汲極區域。 在半導體基 lli ^ ^ I 貝審查委員對本發明之目的、# Λ 合詳細之說明,二;佐以較佳 丨方法本t:::: -種改善輕摻雜源/沒極之摻雜輪廓的 以:摻雜過程能夠得到較佳 :使後續 首先,請先夂關楚—闽& -心彳,雜源/及極輪廓。 成有複數個用4 ,先於半導體基底2〇上_ 體基底中的主動元件及被= 丨22,再於束道。° 或 Shall〇W trench isolation,STI) 、+導體基底20表面形成一包含閘極氧化層^及位 1250589 五、發明說明(4) 於閘極氧化層2 4上太 夕 接續’為修補製i二i: j:的:=閘極結構28 士2〇所造成的損傷,可採行;導對半導體基 製程,以形成—掘丁才°亥丰導體基底2 0進行一 (CVD)於半導體%/ 〇,然後,再利用化學氣相沈錯、 犧牲層32,其厚/底2上沈積一材質為氧化矽之麵< 雜务 利用乾心= 〜咖A。 基底20上之輕捧雜向性’將大部分沈積於半導體 加以去除,以形成& 二其所沈積的厚度為基準 :;利用氯氣酸或依稀; =容液對輕摻雜犧牲層32進1之稀釋氫 ^所不之剩餘輕摻雜犧牲層34,此日t刻,以形成如第五 =犧牲層32之材質同樣為b、因為襯底層30與輕 進行蝕刻時將-併移除部分襯底^此於對輕摻雜犧牲 底層36。 ^刀觀底層30,形成—剩餘襯 以閘極結構2 8、剩铪酤协故 為罩幕,對半導體基底2〇‘ :二犧,層34與剩餘觀底層36 佈植,使其在半導體基 & /辰度的源極/汲極離子 。 底20内形成輕摻雜源/汲極區域38 請參閱第六(A)阖與第六 之方式所形成的輕摻雜源 圖’其係將一本發明 第五(A)圖中可顯著的區域⑼的輪廓放大圖,於 子佈植時,閘極結構28、 進仃低濃度的源/汲極離 層36將有效的阻擋低濃度離子f ^雜犧牲層34與剩餘襯底 ^ ’以獲得較佳的輕摻雜源/ 125〇589 °區,3 8輪廓^ 區埤,然後對半導體基底2〇進行k执ί# 牲Ϊ <離子擴散之回火製程,此;因;極 成一具良奸陡純八你々 傾斜散的擴散,以形 ,如第五(B) g刀所—閘極重豐輕摻雜源/汲極區域輪, 構邊壁的上)圖所不,以解決通道長度變短時,閘:扉 輕抖2正下方發生電游離、所產峰& M 極結 ::極特有劣化模式。 注入邊壁之 J稀釋氫氟:;:::;:: = ::例為1〇: 1〜100: ! 除剩=摻:犧牲層34與行靡刻,以移 直接採用化學=接修補氧化製牙呈,而 3。〇〜iOOOA。裉牲層32’如第七圖所示,其厚度大。 利用乾餘刻,將女 … 犧Ϊ層,…沈積的厚力導體基底上之輕摻雜 如第八圖所示之輕摻雜=,^ 2來加以去除,以形成一 稀釋比例為10:卜、 9 32輪廓,再利用氫氟酸或 ,牲層32進行濕式蝕刻,以之稀釋氫氟酸溶液對輕摻雜犧又 犧牲層34。 y成如第九圖所示之剩餘輕接雜 再以間極結槿9 2 ' 導體基底20進杵,=輕播雜犧牲層34為罩幕 低艰度的没極/源極離子佈植,使其1+Page 5 1250589 V. Invention Description (2)-- The light-doped bungee region heterodymium region t M ^ contour is formed as the second (β) map f & know the process ίί 靡 靡, by In the second (B) diagram, the lightly doped J ^ ^ can not form 6 M ^ can be clearly found in the sub-micron, so not inclined extension profile, and the improvement of the process and enthalpy effect is not perfect control extension The outline of the area is short-circuited and thermoelectric. Therefore, the method of the present invention is to solve the above problems: to improve the shallow hedges [the improvement of the imperfections in the invention]. The principle of T to short-pass the main doping profile of the present invention is to provide an improved light doping source/no wet etching, and the use of the counter substrate layer and the lightly doped sacrificial screen. Using the brakes, the lightly doped sacrificial sputum is used as the mask, and the i% 彳-_~ structure, the remaining substrate layer and the remaining lightly doped g ^ 极 extremely light ion 仃; 仃 light doping and extreme process to obtain - , 2 sacrificial layer: in the doping profile. Line #又好的源/汲 The other part of the invention - the extreme doping in the purpose 'is to provide a way to change the cover 4 Α 婵丄 婵丄 ,, J: 私客 t and good light doping source / 汲 micro : Can not be processed after the process; the improvement of the known process into the deep doping wheel ί: "The purpose is to provide - a change in C. The production produced by:: * * ' can effectively avoid the element; the source / 汲 I of the invention Ϊ channel and thermionic effect. The size of the gradually smaller J-doped profile is provided as a # improve and replace the 半 半 半 半 , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , —Several isolation-ion^~匕 contains a gate oxidation page 6 1250589 — —— V. Description of invention (3) | Layer and the polycrystalline layer above it ^ 丨 丨 轻 轻 轻 轻 轻, ,,. Forming the sidewalls - lightly doped: the two f-substrate I-mole sacrificial layer and the "two:: substrate layer are etched to form: sacrificial layer; h layer and residual oxygen layer into the gate... gate = 丨一轻, 杂 = The number of ion 乂丨 个 区域 区域 区域 区域 区域 区域 区域 区域 区域 区域 区域 区域 区域 区域 区域 区域 区域 区域 区域 _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ The oxide layer of the gate and the polycrystalline crystals above it are engraved, and the sacrificial layer is lightly doped, and the light is ##日, and the remaining layer of the light and early sacrificial layer into the sacrificial layer is covered by the sacrificial layer. Curtain, p sacrificial layer, gate structure fish 兮 ± : bottom opening...: perform a low concentration ion implantation, Γ ί lightly doped I ii into a lightly doped source/drain region. In the semiconductor base lli ^ ^ I Review Committee for the purpose of the present invention, # Λ detailed description, two; with a better 丨 method this t:::: - improved light doped source / immersion profile The doping process can be better: for the first step, please first check the Chu-闽 & - heart, miscellaneous / and polar contours. There are a plurality of 4, which are preceded by the active element in the _ body substrate of the semiconductor substrate 2 and are = 丨 22, and then the beam path. ° or Shall〇W trench isolation, STI), the surface of the + conductor substrate 20 is formed with a gate oxide layer and a bit 1250589. 5. Description of the invention (4) On the gate oxide layer 2 4 on the eve of the splicing system II: j:: = damage caused by the gate structure 28 ± 2 ,, can be taken; guided by the semiconductor-based process to form - Diding only ° Haifeng conductor substrate 20 to a (CVD) semiconductor %/ 〇, then, using chemical vapor deposition, sacrificial layer 32, its thickness / bottom 2 deposited a material on the surface of yttrium oxide &yt; use chores = ~ coffee A. The light-heavy heterogeneity on the substrate 20 is mostly deposited on a semiconductor to be removed to form a thickness based on the deposited thickness: using a chlorine acid or a faint; 1 diluted hydrogen is not left over the lightly doped sacrificial layer 34, this day t to form a material such as the fifth = sacrificial layer 32 is also b, because the substrate layer 30 is lightly etched - and removed A portion of the substrate is thus lightly doped to the sacrificial underlayer 36. ^Knife bottom layer 30, formed - the remaining lining with the gate structure 28, the remaining 铪酤 为 罩 罩 , , 半导体 半导体 半导体 半导体 半导体 半导体 半导体 半导体 半导体 半导体 半导体 半导体 半导体 半导体 半导体 半导体 半导体 半导体 半导体 半导体 半导体 半导体 半导体 半导体 半导体 半导体 半导体 半导体 半导体 半导体Source/amplitude source/drain ions. Forming a lightly doped source/drain region 38 in the bottom 20, please refer to the lightly doped source diagram formed in the sixth (A) and sixth modes, which will be significant in the fifth (A) of the present invention. The enlarged outline of the region (9), during the sub-planting, the gate structure 28, the low-concentration source/drain isolation layer 36 will effectively block the low-concentration ion f ^ impurity sacrificial layer 34 and the remaining substrate ^ ' To obtain a better lightly doped source / 125 〇 589 ° region, 3 8 contour ^ region 埤, and then to the semiconductor substrate 2 k 执 Ϊ Ϊ 离子 离子 离子 离子 离子 离子 离子 离子 离子 离子 离子 离子 离子 离子 离子 离子 离子 离子 离子 离子 离子 离子 离子 离子Into a traitor, the steepness of the pure eight, your slanting diffusion, to the shape, such as the fifth (B) g knife - the gate is heavy and lightly doped source / bungee region wheel, on the side wall of the structure In order to solve the problem that the length of the channel becomes shorter, the gate: 扉 抖 2 2 is electrically discharged, the peak produced & M pole: :: extremely degraded mode. J-diluted hydrogen fluoride injected into the side wall: ;:::;:: =:1 Example: 1~100: ! Excess = blending: sacrificial layer 34 and row engraving, to directly use chemical = repair Oxidation is made by teeth, and 3. 〇~iOOOA. The eucalyptus layer 32' has a large thickness as shown in the seventh figure. Using dry remnants, the female... sacrifice layer, ... the light doping on the thick conductor substrate deposited as shown in Figure 8 is removed by light doping =, ^ 2 to form a dilution ratio of 10: Bu, 9 32 outline, and then hydrofluoric acid or the liquid layer 32 is wet etched to dilute the hydrofluoric acid solution to the lightly doped sacrificial layer. y into the remaining light junction as shown in the ninth figure and then the interfacial junction 9 2 'conductor substrate 20 into the 杵, = lightly spread the sacrificial layer 34 as a mask with low difficulty of the immersion / source ion implantation To make it 1+

KM $ 9頁 1250589 五、發明說明(6) 半導體基底2 0内形成輕摻雜源/汲極區域3 8。 然後對半導體基底2 0進行一使輕摻雜源/汲極區域3 8 之離子擴散之回火製程,以形成一具極佳延伸輪廓之輕摻 雜源/沒極區域,接續,再利用一氫氟酸或依稀釋比例為 1 0 : 1〜1 0 0 : 1之稀釋氫氟酸溶液對半導體基底2 0進行濕 式餘刻,以移除剩餘輕換雜犧牲層3 6。 當然,完成輕摻雜汲極製程後,可接續進行一高濃度 離子佈植與金屬矽化物製程等步驟,但本發明之技術特點 係為輕離子摻雜佈植以獲得較佳延伸輪廓之輕摻雜源/汲 極區域的製程方式,所以於此係不針對後續製程詳加贅述 〇 綜上所述,本發明為一種改善輕摻雜源/汲極離子摻 雜輪廓的方法,其係有效解決習知製程進入深次微米階段 後,所使用之閘極輕摻雜汲極延伸製程,並無法獲得較佳 陡峭之延伸區域輪廓之缺失,並進而避免通道長度變短情 況下,所產生的通道導電度變大,熱電子注入閘極邊壁造 成輕摻雜區域產生空乏的現象。 惟以上所述者,僅為本發明一較佳實施例而已,並非 用來限定本發明實施之範圍,故舉凡依本發明申請專利範 圍所述.之形狀、構造、特徵及精神所為之均等變化與修飾 ,均應包括於本發明之申請專利範圍内。KM $9 page 1250589 V. DESCRIPTION OF THE INVENTION (6) A lightly doped source/drain region 3 8 is formed in the semiconductor substrate 20. Then, a tempering process for diffusing ions of the lightly doped source/drain region 38 is performed on the semiconductor substrate 20 to form a lightly doped source/no-polar region with an excellent extended profile, and then reused. Hydrogen fluoride or a dilute hydrofluoric acid solution having a dilution ratio of 10:1 to 1 0 0:1 wets the semiconductor substrate 20 to remove the remaining lightly modified sacrificial layer 36. Of course, after the lightly doped drain process is completed, a high concentration ion implantation and metal germanium process can be successively performed, but the technical feature of the present invention is light ion doping implant to obtain a lighter extended profile. The method of doping the source/drain region, so this is not described in detail for subsequent processes. The present invention is a method for improving the doping profile of lightly doped source/dip ions, which is effective. After the conventional process is entered into the deep submicron stage, the gate is lightly doped with a drain extension process, and the missing contour of the extended extension region cannot be obtained, and the channel length is shortened, thereby preventing the channel length from being shortened. The conductivity of the channel becomes large, and the injection of hot electrons into the sidewall of the gate causes a lack of light-doped regions. However, the above description is only a preferred embodiment of the present invention, and is not intended to limit the scope of the present invention. Therefore, the shape, structure, characteristics, and spirit of the present invention are equally varied. And modifications are intended to be included in the scope of the invention.

第10頁 1250589 圖式簡單說明 【圖式簡單說明】 第一圖為習知具有延伸淺離子摻雜之閘極構造剖視圖。 第二(A)圖為習知製程之輕離子摻雜輪廓外觀。 第二(B)圖係為習知之輕離子摻雜區域經過回火製程後 之輪廓外觀。 第三圖至第五圖係為本發明之各步驟構造剖視圖。 第六(A)圖為本發明於輕離子摻雜輪廓外觀。 第六(B)圖係為本發明之輕離子摻雜區域經回火製程後 之輪廓外觀。 第七圖至第九圖係為本發明之另一實施例之各步驟構造剖 視圖。 【主要元件符號說明】 1 0閘極結構 1 4輕摻雜源/汲極區域 2 0半導體基底 2 2淺溝渠隔離區域 2 4閘極氧化層 2 6多晶矽層 2 8閘極結構 3 0襯底層 3 2輕摻雜犧牲層 3 4剩餘輕摻雜犧牲層 3 6剩餘襯底層 3 8輕摻雜源/汲極區域Page 10 1250589 Brief Description of the Drawings [Simplified Schematic] The first figure is a cross-sectional view of a gate structure with extended shallow ion doping. The second (A) diagram shows the appearance of a light ion doped profile of a conventional process. The second (B) pattern is the outline appearance of a conventional light ion doped region after a tempering process. 3 to 5 are cross-sectional views showing the steps of the present invention. The sixth (A) diagram is the appearance of the light ion doped profile of the present invention. The sixth (B) diagram is the outline appearance of the light ion doped region of the present invention after the tempering process. 7 to 9 are cross-sectional views showing the steps of another embodiment of the present invention. [Main component symbol description] 1 0 gate structure 1 4 lightly doped source/drain region 2 0 semiconductor substrate 2 2 shallow trench isolation region 2 4 gate oxide layer 2 6 polysilicon layer 2 8 gate structure 3 0 substrate layer 3 2 lightly doped sacrificial layer 3 4 remaining lightly doped sacrificial layer 3 6 remaining substrate layer 3 8 lightly doped source / drain region

第11頁Page 11

Claims (1)

1250589 六、申請專利範圍 1 · 一種改善輕摻雜源/汲極之摻雜輪廓的方法,其包括 下列步驟: 提供一半導體基底,其内係形成有複數個隔離區域; 在該半導體基底上形成一電晶體閘極結構; 於該半導體基底上形成一襯底層; 於該閘極結構側壁形成一輕摻雜犧牲層; 對該輕摻雜犧牲層進行蝕刻,以形成一剩餘輕摻雜犧 牲層; 對該襯底層進行蝕刻,以形成一剩餘襯氧化層;以及 以該閘極結構、該輕摻雜犧牲層與該剩餘氧化層為罩 幕,進行一低濃度的離子佈植,以在該半導體基底 内形成輕摻雜源/汲極區域。 2 ·如申請專利範圍第1項所述之改善輕摻雜源/汲極之 摻雜輪廓的方法,其中當完成該輕摻雜源/汲極區域 製程後,對該半導體基底進行一回火製程,以進行摻 雜原子的擴散,以形成一延伸輕摻雜輪廓,並重整該 半導體基底表面之碎原子結構。 3 ·如申請專利範圍第1項所述之改善輕摻雜源/汲極之摻 雜輪廓的方法,其中該輕摻雜犧牲層的形成步驟, 其包括有下列步驟: 於該半導體基底上沈積一氧化矽層;以及 對該氧化矽層進行乾式蝕刻,以形成一位於該閘極結 構側壁之輕摻雜犧牲層。 4 ·如申請專利範圍第3項所述之改善輕摻雜源/汲極之1250589 6. Patent Application No. 1 - A method for improving the doping profile of a lightly doped source/drain, comprising the steps of: providing a semiconductor substrate having a plurality of isolation regions formed therein; forming on the semiconductor substrate a transistor gate structure; forming a substrate layer on the semiconductor substrate; forming a lightly doped sacrificial layer on the sidewall of the gate structure; etching the lightly doped sacrificial layer to form a remaining lightly doped sacrificial layer Etching the substrate layer to form a remaining liner oxide layer; and performing a low concentration ion implantation with the gate structure, the lightly doped sacrificial layer and the remaining oxide layer as masks A lightly doped source/drain region is formed within the semiconductor substrate. 2. The method of improving the doping profile of a lightly doped source/drain according to claim 1, wherein the semiconductor substrate is tempered after the lightly doped source/drain region process is completed. The process is performed to diffuse dopant atoms to form an extended lightly doped profile and reform the fractured atomic structure of the surface of the semiconductor substrate. 3. The method of improving the doping profile of a lightly doped source/drain according to claim 1, wherein the step of forming the lightly doped sacrificial layer comprises the steps of: depositing on the semiconductor substrate a ruthenium oxide layer; and the ruthenium oxide layer is dry etched to form a lightly doped sacrificial layer on the sidewall of the gate structure. 4 · Improved lightly doped source / bungee as described in item 3 of the patent application 第12頁 1250589 六、申請專利範圍 摻雜輪廓的方法,其中該氧化矽層係利用化學氣相沈 積法所形成。 5 ·如申請專利範圍第1項所述之改善輕摻雜源/汲極之 摻雜輪廓的方法,其中對該輕摻雜犧牲層進行蝕刻 時,係採用濕式蝕刻技術。 6 ·如申請專利範圍第5項·所述之改善輕摻雜源/沒極之 摻雜輪廓的方法,其中該濕式蝕刻劑係選自氫氟酸或 稀釋氫氟酸溶液。 7 · —種改善輕摻雜源/汲極之摻雜輪廓的方法,其包括 下列步驟: _ 提供一半導體基底’其内係形成有複數個隔離區域; 在該半導體基底上形成一電晶體閘極結構,其包含一 閘氧化層及其上方之多晶矽層; 於該閘極結構側壁形成一輕摻雜犧牲層; 對該輕摻雜犧牲層進行蝕刻,以形成一剩餘輕摻雜犧 牲層; 以該閘極結構與該輕掺雜犧牲層為罩幕,進行一低濃 度的離子佈植,以在該半導體基底内形成輕摻雜汲 極區域。 8 ·’如申請專利範圍第7項所述之改善輕摻雜源/汲極之 摻雜輪廓的方法,其中當完成該輕摻雜及極區域製程 後,可對該半導體基底進行一回火製程,以進行摻雜 原子的擴散,並重整該半導體基底表面之矽原子結 構0Page 12 1250589 VI. Patent Application The method of doping a profile, wherein the yttrium oxide layer is formed by a chemical vapor deposition method. 5. The method of improving the doping profile of a lightly doped source/drain according to claim 1, wherein the lightly doped sacrificial layer is etched using a wet etching technique. 6. A method of improving a lightly doped source/dipole doping profile as described in claim 5, wherein the wet etchant is selected from the group consisting of hydrofluoric acid or dilute hydrofluoric acid solution. A method for improving a doping profile of a lightly doped source/drain, comprising the steps of: providing a semiconductor substrate having a plurality of isolation regions formed therein; forming a gate on the semiconductor substrate a pole structure comprising a gate oxide layer and a polysilicon layer thereon; forming a lightly doped sacrificial layer on the sidewall of the gate structure; etching the lightly doped sacrificial layer to form a remaining lightly doped sacrificial layer; A low concentration ion implantation is performed with the gate structure and the lightly doped sacrificial layer as a mask to form a lightly doped drain region in the semiconductor substrate. 8. The method of improving the doping profile of a lightly doped source/drain according to claim 7 of the patent application, wherein the semiconductor substrate is tempered after the light doping and polar region process is completed a process for performing diffusion of dopant atoms and reforming the germanium atomic structure of the surface of the semiconductor substrate 第13頁 1250589 六、申請專利範圍 9 ·如申請專利範圍第7項所述之改善輕摻雜源/汲極之摻 雜輪廓的方法,其中該輕摻雜犧牲層的形成步驟,其 包括有下列步驟: 於該半導體基底上沈積一氧化矽層;以及 對該氧化矽層進行乾式蝕刻,以形成一位於該閘極結 構側壁之輕摻雜犧牲層。 1 0 ·如申請專利範圍第9項所述之改善輕摻雜源/汲極之 摻雜輪廓的方法:其中該氧化矽層係利用化氣相沈積 法所形成。Page 13 1250589 6. Patent Application No. 9: A method for improving the doping profile of a lightly doped source/drain according to claim 7 of the patent application, wherein the step of forming the lightly doped sacrificial layer includes The following steps: depositing a hafnium oxide layer on the semiconductor substrate; and dry etching the germanium oxide layer to form a lightly doped sacrificial layer on the sidewall of the gate structure. A method for improving the doping profile of a lightly doped source/drain according to claim 9 wherein the yttrium oxide layer is formed by a vapor phase deposition method. 1 1 ·如申請專利範圍第7項所述之改善輕摻雜源/汲極之 摻雜輪廓的方法,其中對該輕摻雜犧牲層進行蝕刻 時,係採用濕式蝕刻技術。 1 2 ·如申請專利範圍第1 1項所述之改善輕摻雜源/汲極之 摻雜輪廓的方法,其中該濕式蝕刻劑係選自氫氟酸或 稀釋氫氟酸溶液。1 1 . The method of improving the doping profile of a lightly doped source/drain according to claim 7, wherein the lightly doped sacrificial layer is etched using a wet etching technique. The method of improving the doping profile of a lightly doped source/drain according to claim 1 wherein the wet etchant is selected from the group consisting of hydrofluoric acid or a dilute hydrofluoric acid solution. 第14頁Page 14
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