TWI249644B - A method for forming a lightly doped drain - Google Patents

Abstract

A television signal processing apparatus is In accordance with the present invention, the gate electrode structure with inclined planes is used as a mask when performing an ion implant process. The inclines planes are used to define the lightly doped drain (LDD) region. Therefore, the width of the LDD can be decided by the appearance of the inclined plane.

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of forming a lightly doped element in a transistor thin film transistor element, and more particularly to a method for forming a dopant region. [Prior Art] In general, a TFT-LCD includes a TFT transparent substrate formed of a thin film transistor (TFT) and a pixel electrode, and a transparent top plate having a color filter. Liquid crystal molecules are filled between the TFT transparent top plate and the CF transparent substrate. Further, in each unit pixel, by controlling the gate of the thin film transistor as the switching element, a signal voltage can be transmitted from the data bus Hnes to the unit pixel. When the TFT receives the signal voltage, it will turn on. Therefore, the data voltage carrying the image information can be applied to the corresponding pixel electrode and liquid crystal via the TFT. It is worth noting that when a data voltage is applied to the TFT, the alignment of the liquid crystal molecules changes, thereby changing its optical characteristics and displaying an image. The structure of a general thin film transistor is as shown in Fig. 1, wherein an active substrate structure 构成 4 composed of a polycrystalline thin film having a position and a size defined by a photoresist is provided on a glass substrate 100. A portion of the active region structure 丨04 is then covered with a patterned photoresist (shown in the figure) and ion implanted to form the source/drain structure 112. An insulating layer 1 6 is then formed over the active region, the structure 104, and the glass substrate 100 as a gate dielectric layer. A metal layer is formed over the insulating layer 106 and defined by a patterned photoresist layer 11 t

1249644 V. INSTRUCTIONS (2) The position and size of the gate structure 1 2 2 (as shown in Figure 2). Referring to Figure 2, in order to avoid the short-channel hot electron effect or punch-through that may occur, and to reduce the leakage current in the closed state of the transistor, the original source/drain is close to the channel, and then one is added. The group is doped to a much lower extent than the original source/汲. Therefore, the photoresist layer 1 10 defines the gate electrode position, and a portion of the active region structure 1 〇 4 is retained for subsequent use to form a lightly doped region (LDD) 1 16 . The method of forming is to perform light doping ion implantation with the gate structure I 2 2 as a mask. However, in the conventional art, at least one different mask is required to define the source/no-polar structure 1 1 2 and the nudge region 116, so that if an alignment error occurs, such as an offset occurs during exposure, The width of the light-doped region II 6 formed on both sides is different, and even the lightly doped region formed only falls on one side, which will cause the electrical displacement of the device, so there is an urgent need for a new process that can solve the above disadvantages. . Therefore, the main object of the present invention is to provide a thin film electrical method which utilizes the inclined structure of the element itself to produce a lightly doped film, which can reduce a lithography process and thereby reduce the alignment difference. According to another object of the present invention, a method of manufacturing yield of an ancient-liquid crystal display is proposed. Inter-film transistor In accordance with the preferred embodiment of the invention, f is formed over an active layer on top of the substrate, and an insulating layer is formed over the active layer; a gate is electrically

$6, page 1249644 Description of the invention (3) - a f on the insulating layer, wherein the gate electrode is formed by isotropic wet etching of the layer, so that the formed gate electrode has an inclined appearance; The upper-shaped bungee electrode performs an ion implantation process for the mask, so that the active layer is replaced by the dummy region, wherein the active layer portion exposed outside the gate electrode is shaped into a parallel region, which is the present invention. The source/drain region is located in the portion where the gate is electrically formed and below the slope. Due to the blocking of the gate electrode, the portion is shaped to be t-doped with the drain region; a protective layer is formed on the gate electrode and Above the 绝 and 曰, a layer of holes passes through the above protective layer to expose part of the source.

[Embodiment] Without limiting the spirit and scope of the present invention, the following is a description of the implementation of the present invention; those skilled in the art, after understanding the spirit of the present invention, may apply this method to A variety of different thin film transistors ^ privately 'to eliminate traditionally because at least one more than one mask is needed to define the source/drain structure and lightly doped regions, which will result in source/drain structure and heavily doped When the areas are exposed by exposure, it is easy to cover each other, which causes the electrical potential of the components to be disturbed. The application of the present invention is not limited to the embodiments described below. The manufacturing method is as follows. Referring to FIG. 3, in a preferred embodiment, a glass, quartz, or the like is provided as a transparent insulating substrate 300, and the transparent insulating substrate 3 is used. Forming an amorphous film on 0 0 and converting the amorphous film into a polycrystalline film by excimer laser annealing, followed by a photoresist layer pattern 1249644 V. Description of the invention (4) (not shown in the figure) For the mask, a masking method is applied to form the thin film transistor active region 304. Then, the photoresist layer pattern is removed. Then, as shown in FIG. 4, an insulating layer 3〇6 is formed on the active region 3〇4, According to a preferred embodiment of the present invention, the insulating layer 3 〇 6 is used as the gate dielectric layer 'the material is selected from the yttrium oxide layer, and the deposition method may be plasma assisted 4 · vapor deposition (PECVD) Then, a metal layer 32〇 may be formed on the insulating layer 306 by using a sputtering method to define a gate structure. Generally, the material of the metal layer 32 may be selected from chromium, tungsten, or the like. Niobium, titanium, molybdenum or any combination thereof, in addition, such as chrom aluminide can also be used as metal layer 3 Then, a patterned photoresist layer 3 0 is formed on the metal layer 32 0 to define a gate structure. Then, the photoresist layer 310 is patterned as a mask to perform a metal layer 32 0 . The isotropic wet residue engraves the gate electrode 'the contact solution may be a mixed solution of He 1 and ΗΝΟ 3 or a mixed solution of HC 1 and F e C 1 & because the metal layer 3 2 〇 Each direction is subjected to an equal amount of etching, so that a part of the metal layer 320 of the photoresist layer 31 is eroded, and a gate structure 32 2 having an inclined surface as shown in Fig. 5 is formed. In addition to the photoresist layer 310, it is worth noting that the angle of the inclined surface of the gate structure 32 can be adjusted by adjusting the ratio of the etching solution. As shown in Fig. 6, the gate structure 322 is used as a mask to the film. The transistor active region 3 0 4 is subjected to N-type or P-type ion implantation in a direction 3 2 4 as indicated by an arrow to form four doped regions 314A, 312A, 314B and 312B. wherein the dummy region 3 1 4A And the 3 1 4B system is exposed outside the gate structure 32 2 , so that it will form a heavily doped region, which in this embodiment is a heavily doped N+ Area, while doping

Page 8 1249644 V. INSTRUCTIONS (5) The regions 312A and 312B are located in the gate structure 32 2 barrier gate structure 32 2 barrier, below which, due to 314A and 314B, a light doping, Chen is lower than the lightly doped region of the doped region N-, wherein the lightly doped region is related to the size of the slope, which is easy to say, the J F two-pole structure 32 2 tilt 3 2 2 tilt The shape of the face, indirectly, to control the width of the gate structure. On the other hand, the gate region is 312, 314A and 312B, and the measurement region is 3m. Then, as shown in Fig. 7, the channel region with the V3=transistor is formed. The regions 314A, 312A, 314B, and 312B are over the insulating layer 3〇6. The material of the protective layer 328 can be selected from a general dielectric material: if an oxide, a nitride oxide or any combination thereof can be selected into a two-car embodiment, a chemical vapor deposition method (CVD) can be used. A layer of yttrium oxide or tantalum nitride having a thickness of about 2 Å to 4 Å is formed in an environment at a temperature of about 3 30 ° C. As for the reaction gas used in the process, s i H 4 , Ν , NH 3 , N salty SiH 2 Cl 2 , NH 3 , N 2 , N 20 are used. Then, a contact hole 3 3 is formed using a photolithography process to be sandwiched between the protective layer 328 and the insulating layer 306 to expose the upper surfaces of the doped regions 3 丨 4 a and 3 丨 2 a, respectively. Then, a transparent conductive layer 326 is formed on the surface of the protective layer 328, wherein the transparent conductive layer 326 is also formed in the doped regions 3 1 4 A and 3 1 2 A exposed by the contact hole 310 Upper surface to create conduction. In a preferred embodiment, an indium tin oxide (ITO) film having a thickness of about 200 to 800 angstroms can be formed by sputtering in an environment at a temperature of about 25 ° C. Photoconductive layer 326. 1249644 V. INSTRUCTIONS (6) The present invention has many advantages. First, please refer to FIG. 5 and FIG. 6 simultaneously. The thin film transistor formed by the method of the present invention uses a gate structure as a mask, and uses the inclined surface of the gate structure to simultaneously define light blending. In the case of a hybrid pole region, in other words, the present invention does not require the use of another mask as in the prior art to define a lightly doped drain region (LDD), so that no alignment errors occur. On the other hand, the lightly doped drain region of the present invention can be indirectly controlled by controlling the shape of the inclined surface of the gate structure, so that the width of the lightly doped drain region is relatively easy to control.

Although the present invention has been described above in terms of a preferred embodiment, it is not intended to limit the invention, and it is obvious to those skilled in the art that various changes and modifications can be made without departing from the spirit and scope of the invention. The scope of the invention is defined by the scope of the appended claims.

The above and other objects, features, and advantages of the present invention will become more apparent and understood. 1 and 2 are diagrams showing a conventional method of forming a thin film transistor; and Fig. 3 is a schematic view showing the formation of a thin film transistor active region on a substrate according to a preferred embodiment of the present invention; Figure 4 is a schematic view showing the formation of an insulating layer, a metal layer, and a photoresist layer sequentially on the active region of the thin film transistor according to a preferred embodiment of the present invention. Figure 5 is a view according to the present invention. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT A schematic diagram of a metal layer isotropically etched using a photoresist layer as a mask; FIG. 6 is a diagram showing ion implantation using a gate electrode as a mask according to a preferred embodiment of the present invention. A schematic representation of source, drain and lightly doped drain regions is formed; and Figure 7 is a schematic view of a thin film transistor completed in accordance with a preferred embodiment of the present invention. [Simple description of component symbol] 1 0 0 glass substrate 1 0 4 and 3 0 4 active area 1 0 6 and 3 0 6 insulating layer 1 0 8 and 3 2 0 metal layer

1249644 Schematic description 1 1 0 and 3 1 0 patterned photoresist layer 1 1 2 source/drain structure 1 1 6 lightly doped region 1 2 2 and 3 2 2 gate structure 3 0 0 insulating transparent substrate 314A , 312A, 314B, and 312B doped regions 3 2 4 N-type or P-type ions 3 2 6 transparent conductive layer 3 2 8 protective layer

3 3 0 contact hole

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Claims (1)

1249644 6. Patent application scope 1. A method for forming a lightly doped drain region, the method comprising: providing a substrate; forming an active layer on the substrate; forming an insulating layer on the active layer; forming a metal layer is formed on the insulating layer; a patterned photoresist layer is formed on the metal layer; and the metal layer is isotropically etched by using the patterned photoresist layer as a mask to form a gate with an inclined surface a pole structure; removing the patterned photoresist layer; performing an ion implantation process on the active layer with the gate structure as a mask to form a source/drain structure and a lightly doped drain region, wherein the light The doped drain region is located below the inclined surface of the gate structure; forming a protective layer over the insulating layer, the active layer and the gate structure, wherein the protective layer has a plurality of openings to expose the source\ An upper surface of the drain structure; and a transparent electrode layer formed over the protective layer, wherein the transparent electrode is in contact with the source/drain structure via the contact hole. 2. The method of claim 1, wherein the active layer is a polycrystalline layer. 3. The method of claim 1, wherein the insulating layer is a layer of oxidized stone. Patent application No. 1249644. The method of claim 4, wherein the method of claim 1 is characterized in that the isotropic residue of the metal layer is wet-engraved. The bottom of the material method should be the middle layer, the upper layer of the edge method is extremely dynamic, the main layer is mixed with the light position to form a shape and the upper layer, and the material layer Tf/ is mainly composed of a kind of 5 upper and lower layers. The layer is: 0^^ The gold-containing package is reduced to the shape to etch the same direction, and the layer is layered with a metal. The gold is formed on the cover layer as a resist layer resistive photo-pattern. The shape is structured to be connected to the pole; the barrier layer of the barrier layer is tilted and tilted. The implementation area is fortunately $layer 3⁄4下动|> I _ J ± ® 该 轻 该 该 该 该 该 该 该 该 该 该 该 该 该 该 该 该 该 该 该 该 该 该 该 该 该 该 该 该 该 该 该 构 构 构 构 构 构 构 构 构 构 构The method of claim 5, wherein the active layer is a polycrystalline layer. The method of claim 5, wherein the active layer is a polycrystalline layer. 7. The method of claim 5, wherein the insulating layer is a layer of oxidized stone. 8. The method of claim 5, wherein the isotropic etching of the metal layer is performed using a wet etching method. Page 14