JP2005347683A - Method of forming drain lightly doped in thin film transistor - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a method of making a drain region which is lightly doped in a thin film transistor. <P>SOLUTION: According to this method, a gate electrode structure provided with an inclined plane is used as a mask at the time of performing an ion implantation process, and the inclined plane is used for dividing a drain (LDD) region which is lightly doped in an activation region. Thereby, a width of the LDD is divided in accordance with a geometrical profile of the inclined plane. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to transistor devices, and in particular to a method for making lightly doped drain regions in thin film transistors.

  Generally, a TFT-LCD includes a bottom plate on which a thin film transistor and a pixel electrode are formed, and a top plate on which a color filter is formed.

  Liquid crystal molecules are filled between the top plate and the bottom plate. During operation, a signal voltage is applied to the TFT which is a switch element of each pixel unit.

  The TFT receives the signal voltage and turns on so that the data voltage carrying the image information can be applied to the corresponding pixel electrode and to the liquid crystal via the TFT.

  When a data voltage is applied to the TFT, the orientation of the liquid crystal molecules is changed, thereby changing the optical properties and displaying the image.

  FIG. 1 shows a typical thin film transistor structure. The active region 104 is formed by a thin film of polysilicon and is delimited by a patterned photoresist layer (not shown in the figure) deposited over the glass substrate 100.

  Next, another patterned photoresist layer (also not shown in the figure) is formed over the substrate 100 and partially over the active region 104.

  Next, an ion implantation process is performed using this photoresist as a mask to form the source / drain structure 112 in the active region 104.

  In order to make the insulating layer 106 serve as a gate electrode dielectric layer, it is formed covering the activated region 104 and the glass substrate 100.

  Next, a metal layer 108 is formed on the insulating layer 106. A patterned photoresist layer 110 is then formed over the metal layer 108 to partition the gate structure 122 as shown in FIG.

  In FIG. 2, an additional lightly doped region adjacent to the source / drain structure 112 is used to reduce current leakage while the transistor is in the “off” state, and the thermionic electron effect and punchthrough phenomenon. In order to avoid this, it is formed in the activation region 104.

  An additional ion implantation process is performed using this gate structure as a mask to form a lightly doped drain region designated lightly doped drain 116.

  According to the prior art, at least one mask is required for each to form the source / drain structure 112 and the lightly doped drain 116.

  If misalignment occurs during the exposure process, the two lightly doped drains 116 will result in different widths. Even if only one lightly doped drain 116 is formed in the active region 104, such misalignment creates a structure that shifts the electrical characteristics of the transistor.

  Therefore, a manufacturing method for solving the above problem is required.

  The main object of the present invention is to provide a method of manufacturing a thin film transistor. A gate electrode with an inclined plane is used to form a lightly doped drain, which eliminates the use of photolithography and thereby reduces the probability of misalignment.

  Another object of the present invention is to provide a high yield manufacturing method of a thin film transistor liquid crystal display.

  In accordance with the foregoing objectives, the present invention discloses a method for forming a lightly doped drain.

  The method comprises the following steps. First, an activation layer is formed on the substrate. An insulating layer is formed on the activation layer. A gate electrode having an inclined plane is formed on the insulating layer.

  An isotropic wet etching process is performed on the metal layer to form this gate electrode. An ion implantation process is then performed to form a doped region in the activation layer using the gate electrode as a mask.

  The region in the activation layer exposed by the gate electrode is heavily doped to form the source / drain electrode. The region in the activation layer below the inclined plane of the gate electrode is lightly doped to form a lightly doped drain. A passivation layer is formed on the gate electrode and the insulating layer. Finally, a contact hole is formed in the passivation layer to expose the top surface of the source / drain electrode.

  The foregoing aspects and many of the attendant advantages of this invention will be more readily appreciated and better understood by reference to the following details, taken in conjunction with the accompanying drawings, in which:

  Without limiting the spirit and scope of the present invention, the method proposed by the present invention is depicted as one preferred embodiment for forming a lightly doped drain in a thin film transistor.

  Those of ordinary skill in the art will recognize this embodiment, and to reduce the misalignment that must be attributed to the different photolithography steps that are necessarily involved in the formation of source / drain electrodes and lightly doped electrodes, It can be applied to a TFT device.

  Different photolithography processes often cause overlap between the source / drain electrodes and the lightly doped drain, shifting the electrical properties.

  In the following section, the production method of the present invention is described. The use of the present invention is not limited by the specific examples that follow.

  FIG. 3 shows a transparent insulating substrate, which is made of glass, quartz or the like. In this preferred embodiment, the transparent insulating substrate is a glass substrate 300.

  Next, an amorphous silicon layer is formed on the glass substrate 300. An annealing process is performed to convert the amorphous silicon layer into a polysilicon layer.

  Next, a patterned photoresist layer (not shown in this figure) is formed over the polysilicon layer. An etching process is performed on the polysilicon layer using a patterned photoresist layer as a mask to form an activation layer 304 on the substrate 300.

  Finally, the patterned photoresist layer is removed.

  In FIG. 4, an insulating layer 306 is formed over the activated region 304 to serve as a gate insulating layer. In a preferred embodiment, the insulating layer is made of silicon oxide. This layer of silicon oxide can be formed by plasma enhanced chemical vapor deposition (DECVD).

  Next, the metal layer 320 is formed to cover the insulating layer 306. In a preferred embodiment, the metal layer 320 can be formed by sputtering. Typically, the metal layer 320 is made of chromium (Cr), tungsten (W), titanium (Ti), tantalum (Ta), molybdenum (Mo), aluminum (Al), copper (CU), and various alloys. You can choose from a group of

  A patterned photoresist layer 310 is then formed on the metal layer 320 to define the gate electrode structure.

  An isotropic etching process is performed on the metal layer 320 using a patterned photoresist layer 310 as a mask to form a gate electrode structure.

In a preferred embodiment of the invention, this layer is wet etched using a solution of HCl and HNO ₃ or a solution of HCl and FeCl ₂ .

  Since every location of the metal layer 320 is equally etched, the metal layer 320 under the photoresist layer 310 also forms a gate electrode with a sloped plane 322A as shown in FIG. Etched.

  Next, the photoresist layer 310 is removed. It is noted that the angle of inclination of the inclined plane 322A of the gate electrode can be controlled by modifying the etchant ratio.

  In FIG. 6, P-type or N-type ion implantation is performed in accordance with arrow direction 324 to form four doped regions 314A, 312A, 314B, and 312B in the activation region 304.

Doped regions 314A and 314B exposed by gate electrode 322 are heavily doped to form source / drain electrodes. In the preferred embodiment, the doped polarity of doped regions 314A and 314B is N ⁺ , but the inclined plane 322A can partially resist ion implantation.

Accordingly, doped regions 312A and 312B under the inclined plane 322A of the gate electrode are lightly doped to form a lightly doped region. In the preferred embodiment, the doped polarity of doped regions 312A and 312B is N ⁻ .

  The widths of doped regions 312A and 312B are related to the inclined plane 322A of gate electrode 322.

  In other words, the present invention can be indirectly controlled by changing the geometric shape of the inclined plane 322A.

  The region below the insulating layer 306 on the gate and surrounded by the four doped regions 314A, 312A, 314B and 312B is the channel of the thin film transistor structure.

  Next, in FIG. 7, a passivation layer 328 is formed over the gate electrode 322, the four doped regions 314 A, 312 A, 314 B and 312 B and the insulating layer 306.

  The passivation layer 328 can be selected from the group consisting of oxides, nitrides, and oxynitrides. In a preferred embodiment, an oxide layer having a thickness of 2000 to 4000 Angstroms can be formed by using chemical vapor deposition at about 330 ° C.

The reactive gas for forming the oxidized or silicon nitride layer may be SiH ₄ , NH ₃ , N ₂ and N ₂ O.

  Next, an etching process is performed to form a contact hole 330 on the passivation layer 328 and the insulating layer 306 to expose the top surfaces of the doped regions 314A and 314B.

  Next, a transparent conductive layer 326 is formed over the exposed top surfaces of the passivation layer 328 and doped regions 314A and 314B for electrical connection to the doped regions 314A and 314B.

  In a preferred embodiment, the indium tin oxide layer 326 serving as the transparent conductive layer 326 is formed by sputtering at a temperature of about 25 ° C.

  As described above, with reference to FIGS. 5 and 6, a gate electrode with an inclined plane is used to serve as a mask for forming a lightly doped drain according to the present invention.

  In other words, no additional photolithography steps are required to form a lightly doped drain.

  Therefore, misalignment can be reduced. Furthermore, the width of the lightly doped drain is related to the inclined plane of the gate electrode.

  In other words, the width of the lightly doped drain can be easily controlled by changing the geometry of the inclined plane.

  As can be appreciated by one skilled in the art, the above preferred embodiments of the present invention illustrate the invention rather than limit it.

  It is intended to encompass various modifications and similar arrangements included within the spirit and scope of the claims, and the scope is intended to cover all such modifications and similar structures as much as possible. The broadest interpretation should be followed.

  While preferred embodiments of the invention have been illustrated and described, it will be appreciated that various changes can be made therein without departing from the spirit and scope of the invention.

It is sectional drawing of a typical thin-film transistor. It is sectional drawing of a typical thin-film transistor. FIG. 3 is a cross-sectional view of a substrate showing steps of forming an activation region over the substrate according to the present invention. 1 is a cross-sectional view of a substrate showing steps of sequentially forming an insulating layer, a metal layer, and a photoresist layer according to the present invention. FIG. 4 is a cross-sectional view of a substrate showing the step of isotropically etching a metal layer using a photoresist layer as a mask according to the present invention. FIG. 4 is a cross-sectional view of a substrate showing steps of performing ion implantation to form source / drain regions and lightly doped regions according to the present invention. 1 is a sectional view of a thin film transistor according to the present invention.

Claims (3)

A method for forming a lightly doped region over a substrate, wherein an activation layer is disposed on the substrate, and an insulating layer is disposed on the activation layer, The method is:
Forming a metal layer on the insulating layer;
Forming a patterned photoresist layer on the metal layer;
Performing isotropic etching on the metal layer to form a gate electrode structure with an inclined plane using the patterned photoresist layer as a mask;
Removing the patterned photoresist layer; and ions into the activation layer to form a source / drain electrode structure and a lightly doped drain using the patterned gate electrode structure as a mask. Performing an implantation, wherein the lightly doped drain is disposed below an inclined plane of the gate electrode structure;
A method comprising:   The method of claim 1, wherein the activation layer is a polysilicon layer and the insulating layer is a silicon oxide layer.   The method of claim 1, wherein the isotropic etch is a wet etch.

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