TWI249204B - Semiconductor resistance device, and manufacturing method for the same - Google Patents

Abstract

The present invention discloses a semiconductor resistance device and the manufacturing method for the same. When the polysilicon is used as the resistance device, both sides of it will be formed with salicide having pads for connection to external leads. However, if the resistance device has high resistance coefficient, it will generate the interface resistance between the salicide and the barrier oxide layer, and will have unstable resistance value by voltage and temperature variance. The present invention provides a high density ion implantation at both ends of polysilicon resistance device, and the high density ion implantation process is completed before forming of salicide. Thus, both sides of resistance device has lower resistance coefficient than the polysilicon under salicide, so as to greatly reduce the interface resistance, and greatly eliminate the influence of resistance device caused by voltage and temperature variation.

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a technique for directly fabricating a resistive element on a semiconductor substrate, and more particularly to a polycrystalline germanium resistive element of a semiconductor and a method of fabricating the same. 2. [Prior Art] According to the so-called polycrystalline stone Ρ Ρ 1 1 1 就是 就是 就是 就是 就是 就是 就是 就是 就是 就是 就是 就是 就是 就是 就是 就是 就是 就是 就是 就是 就是 就是 就是 就是 就是 就是 就是 就是 就是 就是 就是 就是 就是 就是 多 多 多 多 多 多 多The parental early crystal grains are separated by a grain interface (G rai π Boundary). And because of the various line defects and point defects in the grain interface, the diffusing ability of the dopant atoms through the grain boundaries will be faster than that through the grain interior. Based on the above factors, polycrystalline germanium can be doped to change its electrical properties and obtain a polycrystalline germanium material that meets the processing conditions; in other words, the fabrication of solid electronic components is usually adjusted by doping dopants of different properties and concentrations. The characteristics of polycrystalline germanium materials, and then the electrical characteristics of the changes, to design electronic components with different functionalities. Therefore, the use of polysilicon itself has a high electrical resistivity, so it can be used as a resistor element for the I C design. When the polysilicon is used as the resistive element, as shown in the first and second figures, the ends of the polycrystalline layer 10 are formed with self-aligned metal telluride (sa 1 ici de) 1 having a contact 14 . 2, used to connect with external wires. Since the resistive element itself must be a non-metal stellite (η ο η - sa 1 icide ), a surface of the polycrystalline layer 10 is covered with a barrier oxide layer 16 to prevent A metal halide 12 is formed. However when the resistance element

1249204 V. INSTRUCTIONS (2) For high resistivity, if greater than 1 ΚΩ / m, an interface resistance will occur between the metal telluride 12 and the barrier oxide layer 16. The interface resistance will be affected. A change in voltage or temperature causes the resistance value to be unstable. As shown in the third figure, the resistance element of the P-type high resistance is affected by the voltage, so that its resistance value becomes quite unstable. In view of the above, the present invention proposes a semiconductor resistor element which can reduce the interface resistance and a method of manufacturing the same, to effectively solve the defects existing in the prior art. Third, [invention content]

The main object of the present invention is to provide a semiconductor resistor element and a method of fabricating the same, which form a high concentration ion doping region at both ends of the resistor element, so that the polysilicon at both ends of the resistor element has a lower resistivity, The interface resistance between the metal telluride and the barrier oxide layer is lowered. Another object of the present invention is to provide a semiconductor resistor element and a method of fabricating the same, which utilizes reducing the interface resistance between a metal telluride and a barrier oxide layer, so that the resistance element can be greatly reduced by voltage and temperature, thereby effectively reducing Solving the problem that the conventional resistance element is subjected to voltage and temperature changes will cause instability of the resistance value.

An embodiment of the present invention provides a semiconductor resistor element structure for forming a polysilicon layer on a semiconductor substrate; two self-aligned metal halides on two sides of the polysilicon layer, and Aligning the surface of the polycrystalline germanium layer between the metal tellurides has a barrier oxide layer, and forming a high concentration ion doping region by ion implantation in the polycrystalline germanium layer below the self-aligned metal germanide; Have a chemical vapor phase

Page 6 1249204 V. Description of the Invention (3) The oxide layer formed by the deposition (CVD) technique covers the surface of the barrier oxygen & metal halide, and only a part of the metal halide is exposed as a layer and a pad. use. In another embodiment of the present invention, a semiconductor electrical manufacturing method is proposed. First, a guest is formed on a semiconductor substrate, and a component is formed thereon to form a patterned barrier. The oxide layer; the barrier oxide layer '', a high concentration ion doping of the semiconductor substrate, so as to form an ion doped region in the polycrystalline germanium layer on both sides of the curtain layer; The layer is a mask, and the self-aligned metal lithium is made by Jiang T. 11 The early-clothing madness is formed on the surface of the polycrystalline stone layer at both ends of the preparation layer. The layer covers the surface of the barrier oxide layer and the metal halide to expose the portion of the metal halide as a contact pad. And the detailed description of the specific embodiments, the technical contents, the features, and the § § is more effective. J. Fourth Embodiment [Embodiment] The present invention provides a semiconductor resistor element and a method of fabricating the same, which are capable of performing a high concentration ion implantation before forming a self-aligned metal telluride at both ends of the resistive element. The interface resistance between the metal telluride and the barrier oxide layer is lowered. As shown in the fourth and fifth figures, a polycrystalline germanium layer 2 2 is formed on a semiconductor substrate 20; and two self-aligned metal tellurides (sa 1icide) 2 4 ' are disposed on two sides of the polycrystalline germanium layer 2 2 . And the surface of the polycrystalline germanium layer 22 between the self-aligned metal lithium 2 4 has a barrier oxide layer (bl0(:k)

Page 7 1249204 5. Inventive Note (4) oxide) 26, wherein the polycrystalline germanium layer 2 under the self-aligned metal germanide 24 is ion-doped by a high-concentration ion doping technique. The concentration needs to be greater than 1015/cm 2 to form the ion doping region 28 of the dinan concentration, and the oxide layer 30 formed by the chemical vapor deposition (CVD) technique, which covers the barrier oxide layer 26 With respect to the surface of the dimetal telluride 24, only a portion of the metal halide 24 is exposed for use as a contact 32. Wherein, in the case of performing high-concentration ion implantation, if the resistive element is an N-type resistor, the ion doped region 28 is implanted with a high concentration of n-type dopant: conversely, if the resistive element is a P-type resistor, Then the ion' is implanted with a high concentration of P-type dopant, and the doping concentration is ♦ > The sixth degree (a) to the sixth (d) of the present invention are respectively a cross-sectional view of the preferred embodiment of the present invention for fabricating a polycrystalline stone by a self-aligned metal telluride process; as shown in the figure, Each step of the invention is performed. ^ The legal system includes the following: please read the second (...), 隹 _ main, first form a polysilicon layer 22, and then use the chemical wind conductor substrate 20 technology with the lithography etching process, in the polycrystalline germanium layer deposition (CVD) row The patterning resistance of the metalloid telluride barrier is formed as a self between 200 Å (A) and 20,000 Å, and the thickness of the layer 26 is used as a self-avoiding Aligning the metallization of the barrier oxide layer of the 6-series metal telluride. Produced during the formation of the genus

Then, the patterned barrier oxide layer 26 is used as a mask (Mask) to the semiconductor.

547 1249204 V. DESCRIPTION OF THE INVENTION (5) Substrate 20 performs a high concentration of ion implantation as shown in the sixth (b) diagram to dope in the polysilicon layer 2 2 on both sides of the barrier oxide layer 26. The N-type or P-type high concentration ion doped region 28; followed by a rapid thermal tempering treatment. The metal tantalum process can be self-aligned after the connection. Referring to FIG. 6(c), a metal layer 34 is first sputtered on the surface of the polysilicon layer 22 and the patterned barrier oxide layer 26; and the first high temperature rapid heating (RTA) process is performed to make the metal. The portion of the layer 34 that is in contact with the surface of the exposed polycrystalline layer 2 2 undergoes a deuteration reaction to self-align to form a metal telluride 24; while the remaining metal layer 34 which is not involved in the reaction or reaction is selectively wet-etched. The ground is removed and a second, warm and rapid heating process is performed, so that a stable self-aligned metal telluride 24 structure as shown in the sixth (d) is formed on the semiconductor substrate 20. Finally, as shown in the sixth (d) diagram, an oxide layer 30 is deposited on the semiconductor substrate 20 by chemical vapor deposition to cover the surface of the barrier oxide layer 26 and the metal halide 24 Only a portion of the metal halide 2 4 is exposed for use as a contact pad 32 for electrically connecting to an external lead. Wherein, the material of the metal layer may be a metal such as cobalt, titanium, nickel, palladium or platinum, and is formed to form a cobalt metal telluride, a titanium metal telluride, a nickel metal telluride, a palladium metal telluride or a platinum metal. Metal halides such as tellurides. The invention firstly forms a high concentration ion doping region before forming a self-aligned metal telluride step on both ends of the resistive element, so that the polysilicon layer at both ends of the resistive element has a lower resistivity, thereby greatly reducing gold

Page 9 1249204 V. Description of the invention (6) It is the interface resistance between the telluride and the barrier oxide layer, so that the resistance element can be greatly reduced by voltage and temperature. As shown in the seventh figure, it is subject to voltage change. The influence becomes more stable, so as to effectively solve the problem that the conventional resistance element is subjected to voltage and temperature changes, which may cause instability of the resistance value. The embodiments described above are merely illustrative of the technical spirit and the features of the present invention, and the objects of the present invention can be understood by those skilled in the art, and the scope of the present invention cannot be limited thereto. That is, the equivalent variations or modifications made by the spirit of the present invention should still be included in the scope of the present invention.

Figure number description: 10 polysilicon layer 12 white line alignment gold 14 contact pad 16 barrier oxide layer 20 semiconductor substrate 22 polysilicon layer 24 white line alignment metal germanide 26 barrier oxide layer 28 ion doped region 30 oxide layer 32 contact Pad 34 metal layer

Page 10 1249204 BRIEF DESCRIPTION OF THE DRAWINGS The first figure is a cross-sectional view of a conventional resistive element. The second figure is a top view of the construction of a conventional resistive element. The third figure is a schematic diagram of a conventional resistive element affected by a voltage change. The fourth figure is a cross-sectional view showing the structure of the resistive element of the present invention. Fig. 5 is a plan view showing the structure of the resistive element of the present invention. 6(a) to 6(d) are respectively sectional views showing the steps of the steps of fabricating the resistive element of the present invention. The seventh figure is a schematic diagram of the resistance element of the present invention affected by the voltage change.

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Claims (1)

1249204 6. Patent application scope 7. The semiconductor resistor element according to claim 1, wherein the oxide layer is formed by chemical vapor deposition technology. 8. A method of fabricating a semiconductor resistive element, comprising the steps of: forming a polycrystalline layer on a semiconductor substrate; forming a patterned barrier oxide layer on a surface of the polysilicon layer; The mask is subjected to a high concentration ion doping, and an ion doped region is formed in each of the polysilicon layers on both sides of the barrier oxide layer; and the barrier oxide layer is used as a mask at both ends of the barrier oxide layer Forming a layer of metal-lithium on each of the surface of the polycrystalline layer; and depositing an oxide layer on the surface of the semiconductor substrate to cover the surface of the barrier oxide layer and the metallization, only the exposed portion Metal telluride acts as a contact pad. 9. The method of fabricating a semiconductor resistive element according to claim 8, wherein the resistive element is an N-type resistor, and the ion doped region is implanted with a high concentration of N-type dopant. The method of manufacturing a semiconductor resistor element according to claim 8, wherein the resistor element is a P-type resistor, and the ion doping region is implanted with a high concentration of a P-type dopant. The method of fabricating a semiconductor resistive element according to claim 8, wherein the doping concentration of the ion doped region is greater than 10 15 /cm 2 . 1 2. Manufacturing of a semiconductor resistor element as described in claim 8 Page 13 1249204 6. Patent application method, wherein the metal telluride is a self-aligned metal halide (sal ici de) 〇1 3 , the manufacturing method of the semiconductor resistor element according to claim 12 The step of forming the self-aligned metal telluride further comprises forming a metal layer on the semiconductor substrate; performing a high-temperature heat treatment to cause a deuteration reaction between the metal layer and the surface of the polycrystalline stone layer. The metal halide is formed by self-alignment; and the metal layer which is not reacted into the metal halide is removed. The method of manufacturing a semiconductor resistor element according to claim 13 wherein the high-temperature heat treatment is performed by a rapid heating process. The method of manufacturing a semiconductor resistive element according to claim 13 wherein the step of removing the unreacted metal layer is selectively removed by wet etching. The method for manufacturing a semiconductor resistor according to claim 13, wherein after the step of forming the self-aligned metal telluride, a rapid heating process can be performed to generate a stable metal halide. The method for producing a semiconductor resistor according to claim 8, wherein the material of the metal halide is selected from the group consisting of cobalt metal telluride, titanium metal telluride, nickel metal telluride, and palladium metal telluride. And a group consisting of platinum metal tellurides. Page 14 1249204 VI. Patent Application Range 1. The method for manufacturing a semiconductor resistor element according to claim 8, wherein the oxide layer is formed by chemical vapor deposition technology. Page 15 5Λ4