TWI248172B - Self-aligned trench DMOS transistor structure and its manufacturing methods - Google Patents

Abstract

A self-aligned trench DMOS transistor structure of the present invention comprises a self-aligned source structure and a self-aligned trench gate structure, in which the self-aligned source structure comprises a p- base diffusion region, a self-aligned n+ source diffusion ring, a self-aligned p+ contact diffusion region, and a self-aligned source contact window; the self-aligned trench gate structure comprises a self-aligned silicided conductive gate structure, a self-aligned polycided conductive gate structure, or a self-aligned polycided trenched conductive gate structure. The self-aligned trench DMOS transistor structure as described is fabricated by using only one masking photoresist step and can be scaled down to get a high-density trench DMOS power transistor with ultra low on-resistance, low parasitic gate-interconnect resistance, and high device ruggedness.

Description

1248172 V. INSTRUCTION DESCRIPTION OF THE INVENTION (1) Technical Field The present invention relates to a recessed double diffused gold-oxygen semiconductor (Trench DMOS) power transistor and a method of manufacturing the same, and particularly to an automatic alignment groove type The double-diffused MOS half-power transistor structure and its manufacturing method are related. [Prior Art] A double-diffused gold-oxygen half-power transistor has a very low on-resistance and has become an important semiconductor component and is widely used in battery protection, switching, linear regulators, amplifiers, and power management. . Basically, the double-diffused MOS half-power transistor structure can be divided into two categories: a Planar double-diffused MOS semi-transistor structure and a trench double-diffused MOS semi-transistor structure. The above-mentioned planar double-diffused MOS semi-transistor structure has a semiconductor surface formed by a gold-oxygen semi-reverse layer channel formed on a plane, and generally presents a larger cell than the grooved double-diffused MOS structure described above. The area of the element and a large on-resistance. Therefore, the above-described recessed double-diffused MOS semi-transistor structure has become a major development of a double-diffused MOS/semi-power transistor or an insulated gate-bias transistor (IGBT). Figure 1A shows a schematic cross-sectional view of a prior art recessed double-diffused MOS transistor structure in which a shallow recess is formed by placing a mask photoresist step on an N-turn substrate 1 2 0 An N epitaxial crystal

1248172 V. Description of the invention (2) Within a part of the 1⁄5 5th layer. The shallow groove is lined with a thermal oxide layer 112 and then filled with a doped polysilicon layer 1丨4 as a conductive gate for isolating the P-diffusion region (or p_base) 1 〇 5. A rigorous mask photoresist step (not shown) is used to selectively form the n + source diffusion region 丨3 〇. Another critical mask photoresist step (not shown) is used to form an oxide layer 140 on top of the shallow recessed region and adjacent to a portion of the surface of the n铄 diffusion region 130. Above, then an auto-aligned ion implant is used to form the Ρ + diffusion region 133 as a ρ-based contact. Obviously, the doping concentration within the p-diffusion region 132 must be less than the concentration within the n+ source diffusion region 130. A metal layer 150 is formed on a portion of the surface of the η + source diffusion region 1300 and over the ρ Μ diffusion region 133 and is patterned to form a source electrode. It can be clearly seen here that Figure 1A requires two rigorous mask photoresist steps to form the η + source diffusion region 1 3 0 and the ρ diffusion region 132, thus causing the ρ-diffusion region 1 0 5 The size cannot be increased by miniaturization. Furthermore, the stray resistance of the doped polysilicon layer 11 as a gate metal layer is quite large for the gate connections of many recessed double-diffused transistor cell elements, resulting in slower switching. speed. Figure 1 shows a schematic cross-sectional view of another recessed double-diffused MOS structure in the prior art, in which a larger Ρ-diffusion region is formed before the shallow groove is formed. An N-layered epitaxial layer above a 0 0 2; a gate oxide layer 2〇\ groove and formed on top of the surface of the crucible; _彳/ I々成= 2 1 0 a part of the void filled with the shallow groove, a multi-hybrid polycrystal, and a tantalum chloride layer 2 15 are formed on the top of the doped polysilicon layer 2 1 〇 2 phase

1248172 V. DESCRIPTION OF THE INVENTION (3) Similarly, a rigorous mask photoresist step (not shown) is used to form the η + source diffusion region 2 1 2 while another rigorous mask photoresist step (not shown) It is used to simultaneously form an oxide layer 2 14 and the gate oxide layer 2 0 6 g. The p-diffusion region 132 of Figure 1A is not shown in Figure 1 to improve the contact resistance between the p-diffusion region 220 and the source metal layer 2 16 . It can be clearly seen here that Figure 1 B still requires two rigorous mask photoresist steps to form the contact of the η source diffusion region 2 1 2 and the source metal layer 2 16 . Comparing the figure and the figure, it can be clearly seen that the overlapping area between the η source diffusion region 2 1 2 and the doped polysilicon layer 2 10 in FIG. 1 is small, thus reducing the gate The capacitance between the source and the source improves the leakage between the η + source diffusion region 2 1 2 and the doped polysilicon layer 2 10 . It is apparent that the recessed double-diffused MOS structure shown in Figure 由于 requires two rigorous mask photoresist steps to define the η + source diffusion region 2 1 2 and the source metal contact, thus It is quite difficult to add to the miniaturization. Accordingly, it is a primary object of the present invention to provide an auto-aligned recessed double diffused MOS semi-transistor structure that is fabricated without the need for a rigorous mask photoresist step. Another object of the present invention is to provide an auto-aligned recessed double-diffused MOS structure having high doping source η + and ρ-based contact diffusion regions to improve contact resistance and ruggedness of components. . It is a further object of the present invention to provide an auto-aligned recessed double diffused MOS semi-transistor structure having a variety of different self-aligned conductive gate structures to reduce gate line stray resistance and capacitance. Another important object of the present invention is to provide a high density automatic alignment

1248172 V. INSTRUCTIONS (4) The grooved double-diffused MOS semi-transistor structure has a reducible P-base size. SUMMARY OF THE INVENTION The present invention discloses an auto-aligned recessed double-diffused MOS semi-transistor structure and a method of fabricating the same. The self-aligning groove type double-diffused MOS semi-transistor structure of the present invention comprises at least one self-aligned source structure located within one source region and an auto-aligned groove gate structure located within a recess gate region The self-aligned source structure described above includes at least one p-based diffusion region, an auto-aligned η+ source diffusion ring, an auto-aligned p-contact diffusion region, and an auto-alignment source contact window; The quasi-groove gate structure comprises at least one self-aligning deuterated conductive gate structure, an auto-aligned polysiliconized conductive gate structure, or an auto-aligned polysiliconized recessed conductive gate structure. The self-aligned η+ source diffusion ring described above is formed on the p-based diffusion by a second self-aligned ion implantation window between a protective dielectric layer and an auto-aligned ion implantation mask layer Within a surface portion of the region, wherein the self-aligned ion implant mask layer is formed within a void surrounded by a sacrificial dielectric layer and the second self-aligned ion implant window Formed by removing the sacrificial dielectric pad layer. The automatic alignment Ρ + contact diffusion region described above is formed by a first self-aligned ion implantation window surrounded by the sacrificial dielectric pad. The self-aligned source contact window described above is formed by a self-aligned contact window formed by a side wall dielectric pad formed over a side wall of the protective dielectric layer.

Page 10 1248172 V. Inventive Description (5) wherein the protective dielectric layer is formed in an etch back blanket oxide layer located within the recess gate region and a buffer oxide layer located within the source region on. The self-aligned deuterated conductive gate structure comprises at least one gate oxide layer overlying a trench surface, an etch back heavily doped polysilicon layer formed over the gate oxide layer, and an automatic pair a quasi-high temperature resistant metal telluride layer is formed on a top surface of the etch back highly doped polysilicon layer, wherein a top surface level of the etch back high doped germanium layer is higher than the buffer oxide layer A top surface is high. The self-aligned polysiliconized conductive gate structure comprises at least one gate oxide layer lining a surface of a recess, and an etch back high-doped polysilicon layer is formed on a portion of the surface of the gate oxide layer a pair of overlying oxide underlayers formed over the side surface portions of the etch back high doped germanium layer and an etch back overlying conductive layer formed between the pair of overlying oxide pads The high-doped polysilicon layer is etched back, wherein a top surface level of the etch back high-doped germanium layer is lower than a bottom surface level of the buffer oxide layer. The above-mentioned polycrystalline germanium recessed conductive gate structure comprises at least one gate oxide layer lining a surface of a recess, and a recessed highly doped polysilicon layer formed on a part of the surface of the gate oxide layer Forming a pair of overlying oxide pads formed on a side surface portion of the highly doped polysilicon layer of the recess to form the recessed highly doped polysilicon layer and an etch back overlying conductive layer for filling A recess formed by the highly doped polysilicon layer of the recess and a portion of the void between the pair of overlying oxide pads. The self-aligning groove type double-diffused MOS structure described above is manufactured by only one mask photoresist step and has the following advantages and features compared with the prior art: the source region can be easily added

1248172 V. Description of the invention (6) miniaturization to obtain a minimum grooved double-diffused MOS semi-transistor size; the self-aligned η+ source diffusion ring and the self-aligned p-contact diffusion region are an automatic pair A high-level doping is added to improve the contact resistance of the η + source and the ρ-based diffusion region; the auto-aligned source contact window is formed in an automatic alignment manner to improve the grooved double The resistance of the diffused gold-oxide semi-transistor; and a highly conductive composite gate layer is used as a recessed gate conductive layer to improve the gate line stray resistance and the groove width can be easily added further Miniaturization. [Embodiment] Referring now to Figures 2A to 2J, a process step and a schematic cross-sectional view of an automatic alignment groove type double-diffused oxy-oxygen semiconductor structure for fabricating a first aspect of the present invention are disclosed. Figure 2A shows that a p-diffusion region 3 0 2 is formed having one [the epitaxial layer 3 0 1 formed over an N + germanium substrate 300; then, a buffer oxide layer 3 0 3 is formed in The p-diffusion region 30 2 is over; then, a mask dielectric layer 340 is formed over the buffer oxide layer 300. The mask dielectric layer 340 is composed of tantalum nitride and deposited by a low pressure chemical vapor deposition (LPCVD) method. The buffer oxide layer 303 described above is a layer of thermal dioxide or a layer of ruthenium dioxide deposited by LPCVD. It is worth noting here that the doping profile shown in Figure 2A is used to fabricate recessed η-channel double-diffused MOS transistors. Similarly, grooved Ρ-channel double diffused gold oxide

Page 12 1248172 V. INSTRUCTIONS (7) Semi-transistors can also be fabricated using different doping patterns. Figure 2B shows a mask photoresist (PR1) step (not shown) for defining a recess gate region; then, the mask dielectric layer 340, the buffer oxide layer 300, the The p-diffusion region 3 0 2 and the N − epitaxial layer 3 0 1 are sequentially etched by anisotropic dry etching to form a shallow groove. It is worth noting here that the complex p-based diffusion region 3 0 2 a is isolated by the shallow pits, and the shape of the complex P-based diffusion region 3 0 2a may be square, hexagonal, rectangular or Round and so on. The depth of the shallow groove described above is deeper than the depth of the junction of the p-based diffusion region 3 0 2a. Figure 2C shows that a gate oxide layer 3 0 6 a is formed over an exposed trench surface, and an etch back conductive layer 3 0 7 a is formed over the gate oxide layer 3 0 6 a. . It is worth noting here that a liner oxide layer (not shown) is formed on the surface of the exposed recess by a conventional thermal oxidation process before the gate oxide layer 306a is formed, and then diluted. The hydrogen acid is soaked to remove the plague caused by the grooves. The gate oxide layer 3 0 6 a is nitrided by a thermal ceria layer or a thermal ceria layer grown in a dry oxygen atmosphere in a laughing atmosphere. The above-mentioned back conductive layer 307a is composed of doped clonylite and is deposited by LPCVD method, and a doped polysilicon layer having a thickness equal to or slightly larger than one half of the width of the shallow groove is first deposited. 3 0 7 (not shown), then a thickness of the doped polysilicon layer 307 deposited by etch back is added by anisotropic dry etching. A top surface level of the return conductive layer 307a is higher than the buffer oxide layer 3 0 3 a. It is worth emphasizing that the etchback conductive layer 3 0 7 a can be highly doped with arsenic or phosphorus ions.

Page 13 1248172 V. INSTRUCTION DESCRIPTION (8) Ion implantation, and a refractory metal lithium layer can be formed on the top of the etch back conductive layer 307a by an automatic alignment process (not shown) ). Figure 2B shows an etch back blanket oxide layer 3 0 8 a for filling a void in the shallow recess. The etch-back blanket oxide layer is composed of cerium oxide and is deposited by LPCVD. The cerium oxide layer having a thickness equal to or slightly larger than one-half of the width of the shallow groove is first deposited. (not shown), then a thickness of the deposited ceria layer 308 is etched back by anisotropic dry etching. Figure 2E shows that the patterned mask dielectric layer 340a in the source region is selectively removed by non-isotropic dry etching or hot phosphoric acid. It can be clearly seen here that the p-based diffusion region 3 0 2 a can be formed by ion implantation in this step instead of the p-based diffusion region 3 0 2a formed in Fig. 2A. The p-based diffusion region 31 2a formed in FIG. 2A is subjected to a larger boron doping segregation effect than the p-based diffusion region 302a formed in FIG. 2E, thereby causing the concave The trench double-diffused MOS transistor has a lower breakdown voltage. Figure 2F shows a protective dielectric layer 309 formed over a surface of the structure of Figure 2E; then, a sacrificial dielectric spacer 310a is formed within each of the source regions. Above the side wall; then, ion implantation is performed across the protective dielectric layer 309 and the buffer oxide layer 3 0 3 a in an auto-aligned manner, in the p-based diffusion region 3 0 2 a A surface portion of the surface forms an auto-aligned P+ contact diffusion region 3 1 1 a. The above-mentioned protective dielectric layer 309 is composed of tantalum nitride and deposited by LPCVD. The sacrifice mentioned above

Page 14 1248172 V. Description of the invention (9) Dielectric mat layer 3 1 Oa is made up of a thin layer of cerium oxide, first deposited with a layer of cerium dioxide (the group is not formed and deposited by LPCVD method 309) Above, the money is etched back to the second (gas is not /:) in the protective dielectric layer. Figure 2G shows a thickness of a self-aligned ίίΐ匕 layer 310. ^ t ,, 310a„ ^ Λ Λ ^ l12; : ^ ^ Ion cloth planting cover sound 3 1 2 b passed by right her · ^ eight ° ° 5 'automatic alignment, Sun: = two 4 ί organic south molecule or polycrystalline stone material composed of a cover layer 3l2a (not shown), and then etch back the stack J m (layer 31 2a. The above organic polymer material is composed of photoresist or bismuth sulphur = (Polyimide). If the crystallization material is used as the automatic cloth The cover layer 3 1 2W, the dryness of the polysilicon layer 3 1 2a (not shown) is approximately equal to or slightly larger than a f-space stack surrounded by the sacrificial dielectric layer 3丨〇a Full of voids, and then etched back to a predetermined thickness by non-isotropic dry etching. If the organic polymer material is used as the self-aligned ion implantation mask layer 3 1 2 b, the organic polymer layer 3 The 1 2 system is first spin-coated on the wafer and then etched back to the desired thickness by chemical etching or plasma etching. Figure 1 shows that the sacrificial dielectric layer 3 1 0 a is buffered with hydrogen peroxide. Selectively removing; then, performing ion implantation across the protective electrical layer 309 and the buffer oxide layer 3 0 3 a in an auto-aligned manner and in the p · -based diffusion region 3 0 2 a One surface portion forms an automatic alignment source diffusion ring 313a 〇', and FIG. 2J shows the sequential removal of the protective dielectric layer 309 surrounded by a side wall dielectric pad 3 14a and The buffer oxide layer 3003a forms an auto-aligned contact window (not shown) in each of the source regions 1248172, in the description of the invention; then, an automatic alignment is performed (si 1 An icidati ο η) process, forming a refractory metal bismuth layer 3 1 5 a in each of the self-aligned contact windows; and then forming a metal layer 3 16 (not shown) formed in one Above the structure and added to form the high temperature resistant metal stone Each of the above-mentioned high-temperature resistant metal-lithium layer 3 1 5a is made of titanium telluride (TiSi 2 ), cobalt telluride (CoS i 0 or nickel telluride (N i S i 2), etc. The formed metal layer 3 1 6 a comprises at least one aluminum alloy layer formed on a barrier metal layer (not shown), and the barrier metal layer is made of titanium nitride (T i N) Or consisting of tantalum nitride (TaN). It is worth noting here that the high temperature resistant metal telluride layer 3 15 a shown in Figure 2J can be added and removed, and the aluminum alloy layer can be directly used as a contact metal. It can be clearly seen from the first connotation of the present invention shown in FIG. 2J that the above-described automatic alignment groove type double-diffused MOS semi-transistor structure is compared with the prior art, and the present invention has the following advantages and features. (a) Compared to a rigorous mask photoresist step required by the prior art, the above-described auto-aligned η + source diffusion ring and the self-aligned p + contact diffusion region are implanted by an auto-aligned ion The mask layer is applied with high concentration doping without any mask photoresist steps. (b) In contrast to a rigorous mask photoresist step required in the prior art, the automatic alignment source contact window described above need not be formed using any mask photoresist step.

Page 16 1248172 V. Description of the Invention (11) (c) Since the self-aligned η diffusion ring and the self-aligned p-contact diffusion region have a low source contact resistance, the above-described automatic alignment groove type double diffusion The gold-oxygen semi-transistor structure can be easily further miniaturized to provide a smaller cell size. (d) The self-aligning groove type double-diffused MOS semi-transistor structure described above is more tolerant than the prior art by non-automatic alignment. Referring now to Figures 3A through 3C, there is shown a simplified process step and a cross-sectional view of a second embodiment of the present invention. Figure 3A shows that a top surface level of the etch back conductive layer 3 0 7 a in FIG. 2C is etched back to a bottom surface equal to or less than the buffer oxide layer 3 0 3 a; then, a pair A blanket oxide layer 3 17a is formed over the side wall of the patterned mask dielectric layer 3 0 a and over the side portion of the etch back conductive layer 3 0 7 b. Figure 3B shows an etch back overlying conductive layer 3 1 8 a formed over the etch back conductive layer 3 0 7b between the pair of capping oxide underlayers 3 17a; then, an etch back blanket oxide layer 3 1 9 a fills a gap between the pair of overlying oxide pads 3 1 7a and is placed over the etch back over conductive layer 3 18a. The etch back cover conductive layer 3 18a is composed of tungsten germanium (WS i Ο or tungsten (W). Similarly, the second process of the present invention according to the same process steps as shown in FIG. 2E to FIG. The connotation can be obtained as shown in Figure 3C. According to Figure 3C

Page 17 1248172 V. INSTRUCTIONS (12) It is clearly seen that the main difference between Figure 3C and Figure 2J is: (a) The tip of the groove shown in Figure 3C is covered with a pair of cover oxidation. The pad layer 317a, thus the leakage between the self-aligned η+ source diffusion ring 3 1 3 a and the back # conductive layer 3 0 7 b can be eliminated, and the overlapping capacitance between the gate electrode and the source electrode is also Can be reduced. (b) The etch back conductive layer 3 0 7 b shown in Fig. 3C is covered with an etch back cover conductive layer 3 18 a, so that the stray resistance of the gate line can be reduced. Referring now to Figures 4A and 4B, there is shown a simplified process step and a cross-sectional view of a third embodiment of the invention in connection with Figure 3A. Figure 4A shows that the etch back conductive layer 3 0 7b between the pair of capping oxide underlayers 3 1 7a is etched back by non-isotropic dry etching to form a recessed conductive layer 3 0 7c; An etch back cover conductive layer 31 8b is used to fill a gap between the pair of cover oxide pads 3 17 7; then, an etch back cover oxide layer 3 1 9 a is formed on the pair of covers This etch back between the oxide underlayers 31 7a covers the conductive layer 318b. Similarly, in accordance with the same process as shown in Figs. 2E to 2J, the third connotation of the present invention can be easily obtained as shown in Fig. 4B. As can be clearly seen from Figure 4B, the recessed conductive layer 3 0 7c provides a larger volume to form the etch back overlying conductive layer 318b, thereby improving the stray resistance of the gate shown in Figure 3C. It is worth emphasizing that this is not the case of Figure 2J, Figure 2C and Figure 4B.

Page 18 1248172 V. INSTRUCTIONS (13) Automatically aligning the grooved η-channel double-diffused MOS semi-transistor structure can use the opposite doping type to fabricate the self-aligned grooves in various semiconductor regions Ρ-channel double diffused gold oxide semi-transistor structure. In addition, the above-described self-aligning groove type double-diffused MOS semi-transistor structure can be further promoted to manufacture an insulated gate bipolar transistor (I GBT) and a MOS semi-controlled thyristor fluid (MCT).

The present invention has been illustrated and described with particular reference Furthermore, the invention is not limited to the details shown, and those skilled in the art will appreciate that various shapes or details can be made without departing from the true spirit and scope of the invention, but also The scope of the invention.

Page 19 1248172 Brief Description of the Drawings Figure 1A and Figure 1B show a schematic cross-sectional view of a prior art grooved double diffused gold-oxygen semiconductor structure. Figures 2A through 2J illustrate the process steps and cross-sectional views of an auto-aligned recessed double diffused oxy-oxygen semiconductor structure for fabricating a first aspect of the present invention. 3A to 3C show a simplified process step and a cross-sectional view of a second embodiment of the present invention in which a self-aligning groove type double-diffused MOS transistor structure is continued. Figures 4A through 4B illustrate a simplified process step and a cross-sectional view of a third embodiment of a self-aligning recessed double diffused oxy-oxygen semiconductor structure in accordance with a third aspect of the present invention. Representative figure description: 3 0 0 N矽 substrate 3 0 2 ρ - diffusion layer 3 0 3 buffer oxide layer 3 0 4 mask dielectric layer 3 0 6 gate oxide layer 3 0 7b etch back polysilicon gate Layer 3 0 8 a etch back cover oxide layer 3 0 9 a shape protective dielectric layer 3 1 1 a ρ contact diffusion zone 3 1 3 ant original diffusion ring 3 01 N is a crystallographic layer 3 0 2a ρ-based diffusion Zone 3 0 3a/ 3 0 3b Forming Buffer Oxide Layer 3 0 4a Forming Mask Dielectric Layer 3 0 7a Deuterated Conductive Gate Layer 3 0 7c Groove Conductive Gate Layer 3 0 9 Protective Dielectric Layer 3 1 0 a Sacrificial Oxidation The mat layer 312b is automatically aligned with the ion implant mask layer 3 1 4 a side wall dielectric mat layer

Page 20 1248172

Page 21

Claims (1)

1248172 VI. Patent application scope 1. An automatic alignment groove type double-diffused MOS semi-transistor structure, comprising at least: a semiconductor substrate of a first conductivity type, wherein the semiconductor substrate comprises at least one lightly doped epitaxial semiconductor The layer is formed on a highly doped semiconductor substrate, and a source region is formed in the lightly doped epitaxial semiconductor layer surrounded by a recess gate region, wherein the source region includes at least one of the second conductivity type a moderately doped base diffusion region, an auto-aligned highly doped contact diffusion region of the second conductivity type is formed in an intermediate surface portion of the moderately doped diffusion region through a first self-aligned ion implantation window a self-aligned high-doping source diffusion ring of the first conductivity type is formed on an outer surface portion of the moderately doped diffusion region through a second self-aligned ion implantation window and placed in the automatic An outer surface portion of the highly doped contact diffusion region and an auto-alignment source contact window are formed by the self-aligning high-doping source diffusion ring The semiconductor surface of the self-aligned high-doped contact diffusion region and an inner semiconductor surface of the self-aligned high-doped source diffusion ring; the recess gate region is formed within the semiconductor substrate and has a shallow The groove depth is slightly larger than a junction depth of the moderately doped diffusion region and is located within the lightly doped epitaxial semiconductor layer, wherein the recess gate region further comprises at least one gate oxide layer formed in the dimple Above a semiconductor surface of the trench, a highly conductive composite gate layer is formed over the gate oxide layer, and an etch back blanket oxide layer is formed over the highly conductive composite gate layer; Page 22 1248172 VI. Patent Application Scope A source metal layer is formed at least over the self-aligned source contact window within the source region and is disposed within the recess gate region. on. 2. The self-aligning groove type double-diffused oxy-oxygen semi-transistor structure as described in claim 1, wherein the semiconductor substrate is composed of early crystal grains. 3. The self-aligning recess type double-diffused MOS semi-transistor structure according to claim 1, wherein the highly conductive composite gate layer comprises at least one etch back high-doped polysilicon layer formed on the gate Above the oxide layer and on the top surface thereof, there is a high temperature resistant metal lithium layer. 4. The self-aligning recessed double-diffused MOS semi-transistor structure according to claim 1, wherein the highly conductive composite gate layer comprises at least one etch back high-doped polysilicon layer formed on the gate An etchback-covered refractory metal bismuth or refractory metal layer is formed on the side wall of the recessed gate region and the side portion of the etched highly doped polysilicon layer The upper pair of overlying oxide pads is over the etched highly doped polysilicon layer. 5. The self-aligning groove type double-diffused MOS semi-transistor structure according to claim 1, wherein the highly conductive composite gate layer comprises at least one groove high-doped polysilicon layer formed by An etch back high-doped polysilicon layer between a pair of overlying oxide pads over the sidewalls of the recess gate region and over the side surface of the etch back heavily doped germanium layer Form a concave inside Page 23 1248172 6. Patent application range slot and an etch back covered high temperature resistant metal telluride or high temperature resistant metal layer are placed in the groove of the highly doped polysilicon layer of the groove and located in the pair of capping oxide Within a portion of the gap between the mats. 6. The self-aligning groove type double-diffused MOS semi-transistor structure according to claim 1, wherein the first self-aligned ion implantation window is formed by forming a protective dielectric layer The protective dielectric layer over a sidewall of the recess gate region and formed within the source region is surrounded by a sacrificial dielectric layer overlying a buffer oxide layer. 7. The self-aligning groove type double-diffused MOS semi-transistor structure according to claim 1, wherein the second self-aligned ion implantation window is removed in a protective dielectric layer formed in the concave The sacrificial dielectric pad layer is formed over a side wall of the trench gate region and between a self-aligned ion implant mask layer surrounded by a sacrificial dielectric pad layer. 8. The self-aligning groove type double-diffused MOS semi-transistor structure according to claim 1, wherein the self-aligning source contact window is formed by a side wall formed on a protective dielectric layer A semiconductor surface portion surrounded by a side of the dielectric layer disposed on a side surface portion of the protective dielectric layer disposed within the source region. 9. The self-aligning groove type double-diffused oxy-oxygen semi-transistor structure according to claim 1, wherein the source metal layer comprises at least one high temperature resistant gold Page 24 1248172 VI. Patent Application A telluride layer is formed on the self-aligned source contact window and a metal layer is formed on at least one barrier metal layer over the refractory metal germanide layer. The first round of Fanli specializes in the application of the body of crystal electric semi-oxygen gold # scatter back to the double-layer curtain cover concave concave cloth on the sub-moving away from the white quasi-there is the god of the 7 machine has a - The upper layer is protected. The shape of the layer is covered by the layer of the layer, or the layer of the layer is covered by the high layer. 1. An automatic alignment groove type double-diffused gold-oxygen semi-transistor structure, at least : A single-crystal germanium substrate of a first conductivity type, wherein the single crystal germanium substrate comprises at least one lightly doped epitaxial layer formed on a highly doped germanium substrate; and a recess gate region having a shallow recess Formed in the lightly doped epitaxial layer, wherein the recess gate region further comprises at least one gate oxide layer formed on a trench surface, and a highly conductive composite gate layer formed on the gate oxide layer And an etch back blanket oxide layer is formed on the highly conductive composite gate layer; a source region is surrounded by the recess gate region, wherein the source region further comprises at least one medium conductivity type The doped diffusion region has a junction depth slightly smaller than a groove depth within the gate gate region, and a highly doped contact diffusion region of the second conductivity type is surrounded by a sacrificial dielectric layer A self-aligned ion implantation to form a window in the Page 25 1248172 6. An intermediate surface portion of the moderately doped diffusion region of the patent application range, a highly doped source diffusion ring of the first conductivity type is located in a protective dielectric layer and is provided by the sacrificial dielectric pad a second self-aligned ion implantation window between the layers of the self-aligned ion implant mask surrounded by the layer to form a side surface portion of the moderately doped diffusion region and the high doping An outer surface portion of the contact diffusion region and an auto-alignment source contact window are formed in the source region and are formed on a side wall of the protective dielectric layer by a side wall dielectric pad layer Formed on a window surrounded by a side portion of the protective dielectric layer; and a source metal layer formed at least over the self-aligned source contact window. The self-aligning groove type double-diffused oxy-oxygen semiconductor structure according to Item 1, wherein the protective dielectric layer is formed of tantalum nitride and is formed in the recess gate region to be oxidized and oxidized. Above the object layer and placed on the source Above a buffer oxide layer within the zone. 1 3. The self-aligning groove type double-diffused MOS semi-transistor structure as described in claim 1 wherein the self-aligning ion implantation mask layer utilizes an etch back organic polymer or complex A crystalline layer is formed. The self-aligning groove type double-diffused MOS semi-transistor structure according to claim 11, wherein the source metal layer comprises at least one refractory metal bismuth layer formed on the self-aligning source Touching the window and a gold Page 26 1248172 VI. Scope of Application The genus layer is placed on top of a barrier metal layer over at least the refractory metal ruthenium formed above the auto-alignment source contact window. 15. The self-aligning groove type double-diffused gold-oxygen semi-transistor structure comprises at least: a single-crystal slab substrate of a first conductivity type, wherein the single crystal slab substrate comprises at least one lightly doped amorphous crystal The dream layer is formed on a highly doped stone substrate; & within a concave layer, formed in a side surface of the gate oxide layer which is oxidized on the gate layer, and the conductive layer of the oxide cap oxide layer is covered The above one source contains a joint depth slightly less than the Tth hundred I I J IHE II... ·/, long time W money repairing the spar in the evening, the groove question area further contains at least one gate Above the surface of the oxidized groove, above a portion of the etch-back high doping layer, a pair of inner side walls covering the layer of the 曰 曰 layer and placed on the etchback layer Above the part, an etchback height guides the mine: a part of a gap between the matte layers of the hetero-poly compound, and the charge is located in the pair of overlying oxide blankets. The etchback height region is surrounded by the sluice gate region, and the conductive enamel layer is included in the 苴One of the hetero-f-types, one of the two-conducting type, a moderately doped group of two, and further one of the two regions having one of the two regions having a high doped contact diffusion region Depth, first-automatically aligning ions; 2 is formed by sacrificing a middle surface portion of the bulk region of the diffusion region 1248172 VI. Patent Application Scope A second self-aligned ion implantation window formed between an auto-aligned ion implant mask layer surrounded by the sacrificial dielectric mat layer is formed in the moderately doped diffusion. a side surface portion of the region and an outer surface portion disposed on the highly doped contact diffusion region, and an auto-alignment source contact window formed within the source region and transmitted through a side a wall dielectric layer formed on a side wall of the protective dielectric layer and formed by a window disposed on a side portion of the protective dielectric layer within the source region; and a source The metal layer is formed at least on the contact surface of the self-aligned source. The self-aligned recessed double-diffused MOS semi-transistor structure as described in claim 15 wherein the etch back is highly doped. The polycrystalline germanium layer is anisotropically etched to form a shallow groove between the pair of overlying oxide pads, and the recess is formed in a concavely oriented system. The sacrifice of the sacrifice of the 15th y ί body special f L crystal please electric 〇 士 氧 oxygen 7 1 gold oxygen ^ ^ ^ slow one ο the upper wall of the side of the source side of the one and the layer of electricity on the wall On the side of the side of the side of the area, the gates of the area are surrounded by Fan Li. By means of the system of the group, the hard layer of the 15th layer is the hard 'crystal structure complex or the body part crystal is high I half machine. Oxygen has 8 1 gold# Page 28 1248172 VI. Application for patent coverage Surrounded. The self-aligning groove type double-diffused MOS semi-transistor structure according to claim 15, wherein the source metal layer comprises at least one refractory metal bismuth layer formed on the automatic alignment source An aluminum alloy metal layer is disposed on the barrier window and is formed on the barrier metal layer at least on the refractory metal halide layer. The self-aligning groove type double-diffused MOS semi-transistor structure according to claim 15, wherein the sacrificial dielectric pad layer is selectively removed by a cerium oxide layer to form The second self-aligning ion implantation window Page 29