1247978 九、發明說明： 【發明所屬之技術領域】 =線f穩壓n，_是指 一輸入端，可接收一直流輪入電壓；氧性％尾态。包含 一輸出端，可輸出一直流輪出電壓； 一功率單元，具三端跸，分別盥鈐 路連接，可經由輸人端接收端及回授網 流；及 員载所需之負載電 一 具二端點，分別與輸出端及該功率單元、車垃 的功能。 平疋之_點，相穩定輸出電壓 【先前技術】 參閱圖一，習知的低壓降線性# -回授網路2G、—輸人端VinH/端v力率甘單元1〇、 與該低壓降線性穩壓器之輸出端v晴連接。ουτ’而”負載30 誤差回授網路2。包括一取樣電路μ盘- 且包括一第一回授電阻2〇11及 授網路的誤差放大器202具有-輪入㈣=山〇12 °而該回 白知的功率早兀是一電晶體1(H，該電晶 5亥誤差放大器202之輸出端連接，而該電晶體 該降線性穩壓器輸人端Vin，可接收 = 體1G1 _即為該低壓降線^ ίί 知ν=τ ’可輸出—轉壓後之直流輸出電壓。 翰出 該回授網路可藉由調整功率單元的閘極電壓，即圖二之節 1247978 點Va之電壓，進而調整該低壓降線性穩壓器之輸出端ν〇υτ之 直流電壓以達成穩壓的功能。 m負载單元30與電晶體101之汲極，即該低壓降線性穩壓 =之輸出端V0UT連接，消耗該低壓降線性穩壓器提供之電 流。，負載單元30包括一負載電容301、一第一負載電阻302 及一第二負載電阻303。該第一負載電容3〇1與該第二負載電 阻303串聯，且該負載電容3〇1與該第二負載電阻3〇3串聯形 f的迴路與該第一負載電阻3〇2並聯。第二負載電阻303乃代 表負載電容301寄生之等效串聯電阻值，而非外加之電阻元 #备低壓降線性穩壓器於穩態正常工作時，該取樣電路2〇1 電壓與參考電壓Vref辭相同，因此可由該取樣電 ==1中之第一回授電阻2011與第二回授t阻2012之電阻值 ¥爾之直流輸出電壓。當之直流輸出電 之-ί 負載電阻3〇2變動而變化時，會造成該取樣電路2〇1 點J電壓異於參考電壓VrEF，經由誤差放大器202將節 極電壓，進而由V0UT提供-固定直流輸出電t曰體101之閘 線性之直流輸出電壓之敎，需針對該低壓降 w生振盪。f知的頻率補償方式係利用ίΐ ^且值達到足夠的相位邊界，進而令健降= ^阻^ ’即第二負載電阻3〇3之限制如圖三 ， 二4f「3r之等效串聯電阻值’即第二1247978 IX. Description of the invention: [Technical field to which the invention belongs] = line f voltage regulation n, _ refers to an input terminal that can receive the current input wheel voltage; oxygenity % tail state. The utility model comprises an output end, which can output a constant current output voltage; a power unit with three end turns, respectively connected to the circuit, can be connected to the receiving end and the feedback network flow; and the load electric power required by the member With two endpoints, respectively, with the output and the power unit, car function.疋 疋, phase stable output voltage [prior art] See Figure 1, the conventional low-dropout linear # - feedback network 2G, - input terminal VinH / end v force rate unit 1 〇, with the low voltage The output of the linear regulator is reduced to a clear connection. Ουτ' and "load 30 error feedback network 2. Includes a sampling circuit μ disk - and includes a first feedback resistor 2 〇 11 and the network error amplifier 202 has - wheel (4) = Hawthorn 12 ° The power of the returning light is earlier than that of a transistor 1 (H, the output of the transistor 5 error amplifier 202 is connected, and the transistor is reduced to the linear regulator input terminal Vin, can receive = body 1G1 _ That is, the low-voltage drop line ^ ίί ν = τ ' can output - the DC output voltage after the voltage conversion. The feedback network can adjust the gate voltage of the power unit, that is, the section 1247978 points Va of Figure 2 The voltage, and then adjust the DC voltage of the output terminal ν〇υτ of the low-dropout linear regulator to achieve the voltage stabilization function. The load of the m load unit 30 and the transistor 101, that is, the output of the low-voltage drop linear regulator= The terminal VOUT is connected to consume the current provided by the low-dropout linear regulator. The load unit 30 includes a load capacitor 301, a first load resistor 302 and a second load resistor 303. The first load capacitor 3〇1 and the The second load resistor 303 is connected in series, and the load capacitor 3〇1 and the second load The circuit of the resistor 3串联3 series f is connected in parallel with the first load resistor 3〇2. The second load resistor 303 represents the equivalent series resistance of the parasitic load capacitance 301, instead of the external resistor element When the voltage regulator is in steady state, the voltage of the sampling circuit 2〇1 is the same as the reference voltage Vref, so the resistance value of the first feedback resistor 2011 and the second feedback resistor 2012 of the sampling power==1 can be used. When the DC output voltage is changed, the load resistance is changed by 3〇2, which causes the sampling circuit to be different from the reference voltage VrEF, and the node voltage is via the error amplifier 202. And further provided by V0UT-fixed DC output power 曰 body 101 linear linear DC output voltage, need to oscillate for the low voltage drop w. The known frequency compensation method is to use ί ΐ ^ and the value reaches a sufficient phase boundary And then let the weight drop = ^ resistance ^ 'that is the limit of the second load resistor 3 〇 3 as shown in Figure 3, two 4f "3r equivalent series resistance value" is the second
定於“之區域聽證線性穩定器之直流輸㈣壓ν咐I 當第-負載電阻302由大至小在瞬間，舉例而言，〇 ι微 1247978 劇趣化，舉例而言， 小電屢νΜΙΝ1與穩態電ϋ電[之暫態響應如圖四。其暫態最 二負載電阻303之電阻值。之差異Vdiffi大致正比於第 阻值有限制而不能!^低从^^第二負載電阻303之最小電 輕夺’其暫態最小雜V讀與穩態 性器之暫態響應降至最低，即導致該健降線 【發明内容】 ，、、取住化。 該低麗降線提供—種低塵降線性穩壓器， 降線性電阻值可以為零’因此可改善低廢 降深^ 嫌出輕之暫態響應。 於疋，本發明低M降線性穩厪器是包含： ,Λ輸入端’可接n赌入電壓； []輸^ ’可輸出—直流輪出電壓； 點’分別與該輸入端、該輸出端及回授網 輸出-言^輸入端接收一直流輸入電壓’並經由輸出端 流；及直机輸出電壓，且可供應穩壓器負載所需之負載電 Γ可 端點’分職錄_及該功料元連接， 壓的m賴碰辨單狀操翻，奴狱輸出電 【實施方式】 配人明f前述及其他技術内容、特點與功效，在以下 it 佳實闕的詳細巾，财清楚的呈現。 含一二ΐ ^本發明低祕雜顏11H佳實施例包 ουτ: Λ載60與該低壓降線性穩壓器之輪出端v瞻連ί -口 >考圖六，該回授網路5〇包括一取樣電路5〇1與_ 1247978 誤差放大器502。該回授網路的取樣電路5〇1具有分壓的功能 且包括一第一回授電阻5011及一第二回授電阻5〇12。 匕 其負載單元60與該功率單元40連接，且包括一負載電容 綱、一第一負載電阻602及一第二負載電阻6〇3。該 容601與該第二負載電阻6〇3串聯，且該負载電容6〇1盥第二 負載電阻603串聯的迴路與該第一負載電阻6〇2並聯。^玄 負載電阻603之值為負載電容601寄生之等效 非外加之電阻元件。。 μ網路5G與該負鮮元6G_部元件及組成方式 均與習知相同，故在此不再贅述。 茂ϊίΐ單A t可由VIN端接收—未經穩壓之直流輸入電 &，並由νουτ端輸出一經穩壓之直流輸出電壓，且 ^曰曰體楊、一第二電晶體4G2、—第三電晶體彻、一第 一電阻性元件撕、-第二電阻性元件撕、—第 性元 一第二電容性元件407及一第三電容性元件408。且 ϊίΐΐϋ阻性元件、電容性元件形成—種分離式結構。 Γ ΐί電晶體是—種ρ型金氧半場效電晶體， 1，的疋’財電晶體並不以此為限，也可以為Ν型 性晶體、雙極性接面1晶體或其他具鐘電晶體特 一電33=，4()4連接該第一電晶體401之閑極與第 j曰日體402之閘極，而該第二電阻性元件4()5連接 件406位於續第一雷曰^ : 1 ^閘極。且该第一電容性兀 繁二六Φ & - Μ 乐一冤日日體402之閘極G2與源極間，該 g了奋電性讀408位於該第三電晶體4G3之閘極G3與雜 器之Sit體之源極均連至同一節點，即該低壓降線性穩壓 Θ月，j h IN，且未穩壓直流輸入電壓即由節點ViN輸入。 8 1247978 =，該等電晶體之汲極也連至同—節點，即該低壓降線性穩 堅斋之輸出端νουτ,而穩壓後的直流輸出電壓即由此節點 ^ουτ輸出。且第一電晶體401之閘極Gl與誤差放大器5〇2之 輸出端連接。 且值得注思的是’該功率單元40的第一電阻性元件404、 ^二電阻性元件405可由電阻或電阻件元件或其他具電阻性 ，二組合元件，如工作在線性區之金氧半電晶體，所構成。而 ^荨電容性讀可由電晶體杨之寄生元件、外加電容性元件 或其他具電容性質之組合元件，如薄膜電容，所構成。 此外，本實施例中該功率單元所包括的電晶體數目、電容 ^件數目、電阻性元件數目並^；以上述所提為限。只要該功 =早70包括N(N為大於或等於2的正整數)個電晶體、N個電 各性兀件及(N-1)個電阻性元件，且該等電阻性元件、電容性 元件:，晶體的連接方式與上述相似即可達到本發明的功效。 而該等兀件的連接方式即為該N個電容性 電晶體的閉極與源極間，而該等電阻性元件之一端 =晶體的，中之-的閘極端’此閘極端乃與誤差放大器輸出 ^ ^該^阻性元件之另—端分別連接至其他電晶體之閘 t此外’該Ν個電晶體之源極均連至同—節點，即該低壓 ΪΪί，益之輸入端〜’且未穩壓之直流輸入電壓即由此 =點、輸人。電晶體找極 vOUT, 由此郎點V〇uT輸出。 会私使可視使用情形調整該功率單元中，每個元件的相關 他可調整之參數。冑曰曰體之面積大小、長寬比例或其 雷元制的分離式結構可使輸_ 電1的電屢的轉移函數之頻率響應如圖七實線所 不。該分離式並聯結構在指定頻率範圍Β間可產生數個極 1247978 點-零點對，即圖七中之込、 零點在相位偏移上有相消“y，) =3:Z3。由於極點與 功率單元的分離式結構内之每別調整本發明之 Zl、p2、Z2、p3、Z3之參，，可以分別移動Pl、 節點Q的電麗轉移函數之=率而2出端νουτ電顯 度，而增益之等效斜率為手/應上之相位偏移最小為-45 此可使低壓降線性釋壓^ ecade，如圖七虛線所示。如 八實線所示，其i 移函數之頻率響應如圖 阻602所造成的極點位置3由於一„電，6,與第一負载電 相位偏移，因此由圖八可知备個，至夕會造成_90度之 因此可令低_生穩_伴以相少為45度， 零點對相義償方式。保持。此補償方式即為極點_ 之值容：有串聯電阻時’即第二負載電阻6〇3 成=2^^^_阻6()3會與負載電容6〇1本身造 zesr=(2 7Γ ResrCl)'1 之值其載電容601之值，^為第二負載電阻603 負载電容601之等效串聯電阻值。由圖八可預知，若 士 S ^於，頻時’會使單增盈頻率(unity gain frequency)提高， 不籍上因南頻寄生極點的影響，而使相位邊界降低，導致系統 侔因此需限制第二負載電阻603之值R之上限以確 先穩定，但不需界定其下限。因此利用極點-零點對相消 尺讀方式之低壓降線性穩壓器，其第二負載電阻6〇3之值 R即負載電谷601之等效串聯電阻值限制如圖九。 由於除去了第二負載電阻603之下限值，因此可以使用等 ^串聯電阻值極小之負載電容601，即令第二負載電阻603之 以改善該低壓降線性穩壓器直流輸出電壓之暫態響 =右弟一負載電阻603之值極小，當圖六中負載電阻602由 至小在瞬間，舉例而言，〇1微秒内，有一劇烈變化，導致 1247978 ，出，流有一劇烈變化，舉例而言，100mA，輸出端ν〇υτ直 流電壓之暫態響應如圖十。其暫態最小電壓VMiN2與穩態電壓 VSTEADY之差異VDIFF2較圖四中之VDlm小，明顯可改善低壓 降線性穩壓器直流輸出電壓之暫態響應。 歸納上述’本發明可去除低壓降線性穩壓器中，負載電容 601寄生等效串聯電阻值之下限，即負載電容6〇1寄生之等效 串聯電阻值可以為零，如此可儘量降低負載電容6〇1之等效串 聯電阻值，以有效提昇低壓降線性穩壓器之暫態響應。 惟以上所述者，僅為本發明之較佳實施例而已，當不能以 此，定本發明實施之範圍，即大凡依本發明申請專利範圍及發 明說明内容所作之簡單的等效變化與修飾，皆仍屬本發明專利 _ 涵蓋之範圍内。 【圖式簡單說明】 圖一係先前技術之低壓降線性穩壓器之系統方塊圖。 圖二係先前技術之低壓降線性穩壓器電路示意圖。 - 圖三係先前技術之低壓降線性穩壓器中，負載電容之等效串聯 電阻限制圖。 圖四係先前技術之低壓降線性穩壓器中，當負載變動時，直流 輸出電壓之暫態響應圖。 ； 圖五係根據本發明的一個具體實施例之低壓降線性穩壓器之 籲 系統方塊圖。 " 圖/、係根據本發明的一個具體實施例之低壓降線性穩壓琴電 路示意圖。 ° 圖七係根據本發明的功率單元中二端點之電壓轉移函數率 響應特性圖。 圖八係根據本發明之低壓降線性穩壓器開回路增益頻率響應 特性圖。 曰心 圖九係根據本發明之低壓降線性穩壓器中，負載電容之等效串 聯電阻限制圖。 > 11 1247978 圖十係根據本發明之低壓降線性穩壓器，當負載變動時，直流 輸出電壓之暫態響應圖。 【主要元件符號說明】 101:電晶體 201:取樣電路 2011:第一回授電阻 2012:第二回授電阻 202:誤差放大器 301:負載電容 302:第一負載電阻 303:第二負載電阻 401:第一電晶體 402:第二電晶體 403:第三電晶體 404:第一電阻性元件 405:第二電阻性元件 406:第一電容性元件 407:第二電容性元件 408:第三電容性元件 501:取樣電路 5011:第一回授電阻 5012:第二回授電阻 502:誤差放大器 601:負載電容 602:第一負載電阻 603:第二負載電阻The DC input (four) voltage ν咐I is determined by the “area hearing linear stabilizer”. When the first-load resistor 302 is from large to small in an instant, for example, 〇ι微1247978 is interesting, for example, small electric repeatedly ΜΙΝ1ΜΙΝ The transient response of the steady-state electric current [Figure 4 is the resistance value of the transient second load resistor 303. The difference Vdiffi is roughly proportional to the resistance value is not limited! ^ Low from ^ ^ second load resistance The minimum electric power of 303 is 'the transient minimum miscellaneous V reading and the transient response of the steady state device are minimized, which leads to the subduction line [invention], and the retention. The low drop line provides - A low-dust-drop linear regulator, the linear resistance can be zero, so it can improve the low-decrease depth and the light transient response. In the present invention, the low-M-down linear stabilizer of the present invention comprises: The input terminal can be connected to n gambling voltage; [] input ^ ' can output - DC wheel voltage; point 'receives the input current, the output terminal and the feedback network output - the input terminal receives the DC input voltage' And flow through the output; and straight machine output voltage, and can supply the load required by the regulator load Γ 端点 端点 ' ' 分 分 分 分 及 及 及 及 及 及 端点 端点 端点 端点 端点 端点 端点 端点 端点 端点 端点 端点 端点 端点 端点 端点 端点 端点 端点 端点 端点 端点 端点 端点 端点 端点 端点 端点 端点 端点 端点 端点 端点 端点 端点 端点The following is a detailed description of the best 巾 , , , 含 含 含 含 含 含 含 本 本 本 本 本 本 本 本 本 本 本 本 本 本 本 本 本 本 本 本 本 本 本 本 本 本 本 本 本 本 本 : : : : : : : ί -口> Figure 6, the feedback network 5〇 includes a sampling circuit 5〇1 and _ 1247978 error amplifier 502. The sampling circuit 5〇1 of the feedback network has a function of voltage division and includes a first a feedback resistor 5011 and a second feedback resistor 5〇12. The load unit 60 is connected to the power unit 40, and includes a load capacitor, a first load resistor 602 and a second load resistor 6〇3. The capacitor 601 is connected in series with the second load resistor 6〇3, and the circuit in which the load capacitor 6〇1盥the second load resistor 603 is connected in series is connected in parallel with the first load resistor 6〇2. The value of the load resistor 603 is The equivalent of the load capacitor 601 parasitic non-additional resistance element. μ network 5G and the negative fresh element 6G_ components and The method is the same as the conventional one, so it will not be described here. The A ϊ A A can be received by the VIN terminal - the unregulated DC input power & and the νουτ terminal outputs a regulated DC output voltage, and ^曰曰体杨, a second transistor 4G2, a third transistor, a first resistive element tear, a second resistive element tear, a first element a second capacitive element 407 and a first The three capacitive elements 408, and the resistive elements and the capacitive elements form a separate structure. Γ 电 电 电 电 电 电 ρ ρ ρ ρ ρ 1, 1, 1, 1, 1, 1, 1, 财 财 财 财 财 财 财 财 财For example, it may be a Ν-type crystal, a bipolar junction 1 crystal or the other with a clock transistor, a battery 33=, 4 () 4 connected to the idle pole of the first transistor 401 and the j-th body 402 The gate of the second resistive element 4 () 5 is located at the first thunder ^ : 1 ^ gate. And the first capacitive 兀 六 Φ Φ Φ Φ 冤 冤 402 402 402 402 402 402 402 402 402 402 402 402 402 402 402 402 402 402 402 402 402 402 402 402 402 402 402 402 402 402 402 402 402 402 402 402 402 402 402 402 402 402 402 402 402 402 402 402 402 402 402 402 402 402 402 402 402 402 402 402 402 402 402 402 402 402 402 402 402 402 402 402 402 402 402 402 402 402 402 402 402 402 402 402 402 402 402 402 402 The source of the Sit body of the multiplexer is connected to the same node, that is, the low-voltage drop linear regulator is Θ month, jh IN, and the unregulated DC input voltage is input by the node ViN. 8 1247978 =, the drain of the transistors is also connected to the same-node, that is, the low-voltage drop linearly stabilizes the output terminal νουτ, and the regulated DC output voltage is output from this node ^ουτ. The gate G1 of the first transistor 401 is connected to the output terminal of the error amplifier 5〇2. And it is worth noting that 'the first resistive element 404 of the power unit 40, the ^ two resistive element 405 can be made of a resistive or resistive element or other resistive, two combined elements, such as a gold oxide half operating in a linear region. A crystal is formed. The capacitance reading can be made up of a parasitic element of the transistor, an external capacitive element, or other combination of capacitive elements, such as a thin film capacitor. In addition, the number of transistors, the number of capacitors, and the number of resistive elements included in the power unit in this embodiment are limited to the above. As long as the work = early 70 includes N (N is a positive integer greater than or equal to 2) transistors, N electrical components, and (N-1) resistive elements, and the resistive elements, capacitive Component: The crystal is connected in a similar manner to the above to achieve the effects of the present invention. And the connection manner of the components is between the closed pole and the source of the N capacitive transistors, and one of the resistive elements = the crystal, and the gate terminal of the - the gate is the error Amplifier output ^ ^ The other end of the resistive component is connected to the gate of other transistors respectively. In addition, the source of the transistor is connected to the same node, that is, the low voltage ,, the input end of the benefit ~ And the unregulated DC input voltage is thus the point = input. The transistor finds the vOUT, which is the output of the 点V〇uT. The private use case adjusts the parameters of each component in the power unit that can be adjusted. The size of the carcass, the ratio of length to width, or the separate structure of the ray-element system can make the frequency response of the transfer function of the _1 electric power 1 as shown in the solid line of Figure 7. The split parallel structure can generate a number of poles of 1247978 point-zero pairs in the specified frequency range, that is, the 零 and zero points in Fig. 7 have a phase offset of "y,) = 3: Z3. Due to the poles Each of the separate components of the power unit adjusts the parameters of Z1, p2, Z2, p3, and Z3 of the present invention, and can respectively shift the rate of the electric transfer function of P1 and node Q, and the electrical output of the second end νουτ. And the equivalent slope of the gain is the minimum phase shift of the hand/should be -45. This can make the low pressure drop linear pressure release ^ ecade, as shown by the dotted line in Figure 7. As shown by the eight solid line, its i shift function The frequency response is as shown in Figure 602. The pole position 3 is due to a „Electrical, 6. It is phase-shifted from the first load. Therefore, it can be seen from Figure 8 and it will cause _90 degrees to cause low _ The stability _ is accompanied by a minimum of 45 degrees, and the zero point is the same as the compensation method. maintain. This compensation method is the value of the pole _: when there is a series resistance, that is, the second load resistor 6〇3 becomes =2^^^_ resistor 6()3 will be built with the load capacitance 6〇1 itself zesr=(2 7Γ The value of ResrCl) '1 is the value of its load capacitance 601, and ^ is the equivalent series resistance value of the second load resistor 603 load capacitance 601. It can be predicted from Fig. 8 that if the S S is in the frequency, it will increase the unity gain frequency, and the phase boundary will be reduced due to the influence of the parasitic pole of the south frequency. The upper limit of the value R of the second load resistor 603 is limited to be stable first, but the lower limit thereof is not required to be defined. Therefore, the value of the second load resistor 6〇3, which is the value of the second load resistor 6〇3, is the limit of the equivalent series resistance of the load valley 601, as shown in Fig. 9. Since the lower limit of the second load resistor 603 is removed, the load capacitance 601 having a very small series resistance value can be used, that is, the second load resistor 603 can improve the transient state of the DC output voltage of the low-dropout linear regulator. = Right brother a load resistor 603 value is very small, when the load resistor 602 in Figure 6 is from small to instant, for example, within 1 microsecond, there is a drastic change, resulting in 1247978, out, the flow has a dramatic change, for example That is, 100mA, the transient response of the DC voltage at the output ν〇υτ is shown in Figure 10. The difference between the transient minimum voltage VMiN2 and the steady-state voltage VSTEADY VDIFF2 is smaller than that of VDlm in Figure 4, which significantly improves the transient response of the DC output voltage of the low-dropout linear regulator. In the above-mentioned invention, the lower limit of the parasitic equivalent series resistance value of the load capacitor 601 in the low-dropout linear regulator can be removed, that is, the equivalent series resistance value of the load capacitance 6〇1 parasitic can be zero, so that the load capacitance can be minimized. The equivalent series resistance of 6〇1 is used to effectively improve the transient response of the low-dropout linear regulator. However, the above is only the preferred embodiment of the present invention, and the scope of the present invention is not limited thereto, that is, the simple equivalent changes and modifications made by the scope of the present invention and the description of the invention, All are still within the scope of the patent of the present invention. BRIEF DESCRIPTION OF THE DRAWINGS Figure 1 is a system block diagram of a prior art low dropout linear regulator. Figure 2 is a schematic diagram of a prior art low dropout linear regulator circuit. - Figure 3 is an equivalent series resistance limit diagram for load capacitance in a prior art low dropout linear regulator. Figure 4 is a transient response diagram of the DC output voltage when the load changes in a prior art low dropout linear regulator. Figure 5 is a block diagram of a low voltage drop linear regulator in accordance with an embodiment of the present invention. " Figure/ is a schematic diagram of a low dropout linear regulator circuit in accordance with an embodiment of the present invention. Figure 7 is a graph showing the voltage response function rate response characteristics of the two terminals in the power unit according to the present invention. Figure 8 is a graph showing the open loop gain frequency response characteristic of a low dropout linear regulator according to the present invention. Figure 9 is an equivalent series resistance limit diagram of a load capacitor in a low dropout linear regulator according to the present invention. > 11 1247978 Fig. 10 is a diagram showing the transient response of the DC output voltage when the load changes according to the low dropout linear regulator of the present invention. [Main component symbol description] 101: Transistor 201: Sampling circuit 2011: First feedback resistor 2012: Second feedback resistor 202: Error amplifier 301: Load capacitance 302: First load resistor 303: Second load resistor 401: First transistor 402: second transistor 403: third transistor 404: first resistive element 405: second resistive element 406: first capacitive element 407: second capacitive element 408: third capacitive Element 501: sampling circuit 5011: first feedback resistor 5012: second feedback resistor 502: error amplifier 601: load capacitor 602: first load resistor 603: second load resistor