TW200845546A - Low dropout (LDO) linear voltage regulator - Google Patents

Abstract

A low dropout (LDO) linear voltage regulator is provided to employ a nested Miller compensation (NMC), is referred to as the basic structure, for designing a low dropout voltage regulator (LDO) without an output capacitance. An active resistor may be added to the Miller capacitance feedback circuit. Thus, the increase of the damping coefficient control can accommodate the wide range of the output capacitance and its parasitic resistance, and further resolve the tradeoff between the damping coefficient control and the system loop gain. Furthermore, the use of capacitor-sharing switch technique reduces the Miller capacitance value in the whole system, and thereby reduces the output-voltage stabilization time without affecting its stability.

Description

200845546 IX. Description of the Invention: [Technical Field of the Invention] A low-dropout linear voltage regulator is a low-dropout linear voltage regulator that uses active resistors and shared capacitor switching techniques without the need for output capacitors. [Prior Art] As the communication market matures, the application of related ic continues to grow. With the development of portable electronic products such as mobile phones, the length of battery life used for power supply springs is even more important. How to improve the efficiency of the battery and maintain its stability is a very challenging topic. In recent years, low-dropout linear regulators have become the mainstream of low-power step-down and voltage regulator circuits because of their improved conversion efficiency and their small size and low noise. It is widely used in a variety of portable systems that supply power from batteries and communication-related electronic products. In existing products (methods), in order to make the low-dropout linear regulator more accurate, a three-stage amplifier is generally used to increase its gain, but it will cause instability. Therefore, it has been repeatedly proposed * a variety of frequency compensation methods to achieve system stability. In the beginning, it was proposed to use an external capacitor to lower the main pole position and increase the phase margin. That is, the pole-zero compensation method, so a large-sized output capacitor is required to push the main pole to the low frequency to maintain stability. However, since the main pole is at the output point, the maximum load current value will affect its stability. Degree is limited. This also has the following disadvantages: 1. Since the main pole of such a circuit falls on the output point, a larger output capacitor is needed to stabilize the system, but the actual product is not easy to do this 5 200845546 • Inside the chip, so Will increase the difficulty of system integration. 2. In general, we want a larger system gain to improve the accuracy of the system. However, such circuits increase the gain, but reduce the stability of the system, thus causing a trade-off between accuracy and stability. . 3. The magnitude of the load current of such circuits is limited by the stability of the system. Because the larger the output current, the smaller the load resistance, the larger the main pole at the output point, and the worse the stability of the system. Therefore, in order to improve the above disadvantages, a low-dropout linear voltage regulator (shown in FIG. 1) using a nested Miller compensation has been proposed, and the low-dropout linear voltage regulator 1〇 includes an input terminal. VIN receives the input DC voltage, and has an output terminal VOUT that outputs a stable output voltage; a power transistor 13 and a first stage amplifier 11 and a second stage amplifier 12 connected in series; the source and input of the power transistor 13 The terminal VIN is connected, the drain thereof is connected to the output terminal VOUT, and the gate thereof is connected to the output terminal of the second stage amplifier 12. The inverting input terminal of the first stage amplifier 11 is input with a reference voltage signal by a reference voltage generator 14, and its non-inverting input terminal is connected to the first node 15' and its output terminal is connected to the input terminal of the second stage amplifier 12'. A first Miller compensation capacitor Cml is disposed on the feedback path between the output terminal and the drain of the # power transistor 13, and the output terminal of the second stage amplifier 12 and the non-polar feedback path of the power transistor 13 are disposed on the feedback path. A second Miller compensation capacitor Cm2 is provided. A feedback network 20 is connected between the drain of the power transistor 13 and the non-inverting input of the first stage amplifier 11. The feedback network 20 includes a resistor rfi and In RF2, the two resistors RF1, RFj· become a voltage divider, and the node 15 is formed between the two resistors rfi and RF2, and the non-inverting input terminal of the first stage amplifier 11 is connected to the node 15. The output terminal ν 〇υ τ of the low-dropout linear voltage regulator 10 is externally connected with an output capacitor CL and its parasitic resistance Resr. 200845546 This nested Miller compensated low-dropout linear voltage regulator uses the characteristics of pole splitting to change the main pole to the turn-off point of the first-stage amplifier 11. This method does not require a large The use of size output capacitor CL 'even zero output capacitor Cl can also make the system have good stability. 4 This is beneficial to the system of single chip (s〇c), and can reduce the use of external components and reduce the area of the board. .

凊Refer to the small signal model of the system shown in Figure 2, which contains two levels of gm]vs, gw% and a power transistor for the first stage amplification (four) and the second stage amplification (four). 13 output level, 1 in Rfi, heart 2 constitutes the feedback network, gm〗, gw, respectively, first, ^ two $ =,, the output level of the transduction ' ', R〇冰~& respectively... , and the output impedance and parasitic capacitance of the first stage amplifiers 11, 12, the output capacitance, Resr is the parasitic resistance of the output capacitor '~, ^ is the compensation capacitor for t Miller, Rwt (=Rl|ir°pII(Rfi+ Rfi)) where Rl>R〇P is the output impedance of the load impedance and the power galvanic body respectively. The small signal model of the formula: "Figure 2" can be derived from the system conversion equationΛ

c η ^ 'S —--^ __ mv^mJ mp ι+-

C〇utReSR

1 + -^-VP~3dB l + s ^out^esr + Sm2 + s "mT^QUr SmlSmp ( (1) where the DC gain is 4 and the main pole is p__3de C-mpRmR〇1R (damped by the push-down The coefficient is O2±V0UT f ζ' 2

V

Rf2

Rf2 ^OUT^ESR ~ Sml

SmlSi mp

Cm2Ca

UT (2) (3) (4) 7 200845546 However, from the above derivation, the damping coefficient ζ will change due to the difference between the output capacitance value and its parasitic resistance value resr. When the output capacitance value c〇 and its parasitic resistance value Resr are very In order to get a sufficient damping coefficient ζ and use a smaller Miller compensation capacitance value Cm2, the second-stage transduction gm2 must be reduced, so that the system feedback gain will be relatively small and the accuracy of the system will be reduced. A trade-off between the damping coefficient control ζ and the system loop gain is formed. SUMMARY OF THE INVENTION • The main purpose of the present invention is to use nested Miller compensation as a basic architecture, and to use the characteristics of pole-column to change the main pole to the output point of the first-stage amplifier. The use of size output capacitors, even zero output capacitors, can also make the system have a good stability advantage, k out in the feedback path of Miller Valley to add active resistors, thereby increasing the damping coefficient control, in response to large The use of the range output capacitor and its parasitic resistance further resolves the trade-off between the damping coefficient control and the system loop gain. Another object of the present invention is to provide a capacitor switching technique to reduce the Miller capacitance required for the entire system, thereby reducing the Miller capacitance required for the entire system, and further extending the frequency because the total capacitance is reduced. Wide and accelerate the settling time of the output voltage. The invention relates to a low-dropout linear voltage regulator, which comprises an input terminal receiving an input DC voltage, and a round output terminal outputting a stable output voltage; a power transistor having a source connected to the wheel-in terminal, and The pole is connected to the output terminal; a first stage amplifier whose inverting input terminal is input with a reference voltage signal by a reference voltage generator, and the non-inverting input terminal is connected to a section 8 200845546 point 'its wheel end and the power transistor a first Miller compensation capacitor is disposed between the drain electrodes; a second stage amplifier having an input terminal connected to the output end of the first stage amplifier, and an output terminal connected to the drain of the power transistor a two-miller compensation capacitor and an active resistor; and a feedback network connected between the drain of the power transistor and the non-inverting input of the first-stage amplifier. The feedback network is composed of two resistors. A voltage divider, and the two resistors form the node. The active resistor is connected to a transistor in the form of a diode. The present invention uses nested Miller compensation as a basic architecture, and utilizes the characteristics of pole-column to change the main pole to the output point of the first-stage amplifier. This method can eliminate the need for large-size output capacitors, and even zero-output capacitors can be used. This makes the system very stable, which is beneficial to the application of the system single chip, and reduces the use of external components and reduces the area of the board. Since the damping coefficient changes due to the difference between the output capacitor value and its parasitic resistance value, the damping coefficient is insufficient, which causes the frequency response to have a surge near the single gain frequency, which in turn causes the output voltage to respond to the load current step 2 The quasi-linear region will cause chopping to occur and slow down its % time. Therefore, the present invention adds f dynamic resistance to the feedback path of the Miller capacitor, thereby increasing the damping coefficient control to cope with the use of a wide range of output electric valleys and parasitic resistance thereof, and further solving the mutual relationship between the damping coefficient control and the system loop gain. The trade-off. The low-dropout linear voltage regulator of the present invention further includes a sharing circuit: the distributed capacitance circuit includes a sharing capacitor, the sharing capacitor privately detects the current on the power transistor, and switches the sharing capacitor respectively The first Miller compensation capacitor or the second Miller compensation capacitor is connected in parallel, thereby reducing the Miller capacitance value required for the entire system, and further accelerating the settling time of the output voltage of 200845546. The '鸪 sharing capacitor circuit includes a current sensing circuit for detecting current on the power transistor; a Schmitt trigger circuit that inputs the signal of the current sensing circuit and transmits the signal to the first The non-overlapping clock generates ι§ 'generating two non-overlapping clocks; and two are respectively subjected to the aforementioned two clocks, a switch and a second switch, wherein the first switch is located between the electric valley and the shared capacitor 'The first level of electricity

Capacity and the sharing of electricity H

To the 盥: When the transistor is operated in the triode area, 'the shared capacitance is switched to Ϊ the main-pole capacitance is connected in parallel'. The damper Miller compensation capacitance value is in the triode area. The sub-fourth: the dead force rate transistor operation is connected in parallel. The comparison with the first-Miller compensation capacitor ^ makes the system, =: the capacitance value to push the main pole to the low frequency, and when the first body is operated in the saturation region, the shared capacitance is switched to the control of increasing the damping coefficient. In addition to the 彳 电 电 奋 来电 晶体 晶体 晶体 晶体 晶体 晶体 晶体 晶体 晶体 晶体 晶体 晶体 晶体 晶体 晶体 晶体 晶体 晶体 晶体 晶体 晶体 晶体 晶体 晶体 晶体 晶体 晶体 晶体 晶体 晶体 晶体 晶体 晶体 晶体 晶体 晶体 晶体 晶体 晶体 晶体To increase the damping coefficient of the routing path, so when the heavy load ± phase: the value of the first Miller compensation capacitor back [embodiment] negative (10) bandwidth will be extended. In the detailed description of the present invention, the description will be made, but the description should be made with the following description, but the following description should not be construed as an example of the present invention. The embodiments are merely illustrative. 200845546 Please refer to "Figure 3" for a schematic diagram of the present invention for adding an active power pack to the feedback path of a Miller capacitor. Using a nested Miller compensation as the basic architecture of the low-dropout linear voltage regulator 1〇〇, the low-dropout linear voltage regulator is 100 including an input terminal vIN receiving input DC voltage, and an output terminal νουτ output is stable The output voltage. a power transistor 13A and a first-stage amplifier 110 connected in series with a second-stage amplifier 12A; the source of the power transistor 130 is connected to the input terminal Vin, and the drain thereof is connected to the output terminal ν〇υτ, The gate is connected to the output of the second stage amplifier 120; the inverting input of the first stage amplifier 110 is input by a reference voltage generator 140 to a reference voltage signal 'the non-inverting input is connected to a node 15A, and The output is connected to the input end of the second stage amplifier 12〇, and a first Miller compensation electric valley Cmi is disposed on the feedback path between the output end and the drain of the power transistor 130, and the first stage amplifier 120 is The output end is connected to the power transistor; a second Miller compensation capacitor is provided on the feedback path between the drains of the 30 (: ^2. A feedback network 200 is connected to the drain of the power transistor 130 and the first Between the non-inverting input terminals of the stage amplifier 11 ,, the feedback network 200 includes resistors Rpi and R η , and the two resistors rfi and r form a voltage divider, and the two resistors and R F2 form the node 150 . The non-inverting input of the first stage amplifier 110 is connected to the node 15 0. The output terminal vOUT of the low-voltage drop linear voltage regulator 1 并 is externally connected with an output capacitor C1 and its parasitic resistance Resr. The invention is characterized in that the output of the second stage amplifier 12 与 and the power transistor 130 And the second Miller compensation capacitor on the inter-electrode cm2 feedback path is provided with an active resistor 160 in series with the second Miller compensation capacitor, thereby increasing the damping coefficient control in response to a wide range of wheel-out capacitance cL and its parasitic resistance Resr The use of the damping coefficient ζ control and the system loop gain can be further solved. The active resistor 16 is connected to the transistor of the 200845546 diode form, because, by the formula (1) (2) ( 3) The derivation of (4) shows that the damping coefficient ζ will change due to the difference between the output capacitance value cOUT and its parasitic resistance value. When the output capacitance value cOUT and its parasitic resistance value Resr# are often small, in order to get an adequate Damping coefficient ζ and using a smaller Miller compensation capacitor value Cm2, the first stage of the transduction gm2 must be reduced, so the system feedback gain will be relatively small and reduce the accuracy of the system To form a mutual trade-off between damping control system loop gain ^. V

For the above reasons, we propose to add the active resistor 160 to the feedback path of the associated Miller capacitor. Please refer to the small signal model shown in "Fig. 4". The small signal model includes two gain stages gmlvs, gwV2 of the first stage amplifier 11 and the second stage amplifier 120, and an output stage of a power transistor. , where RF1 and 1^2 form a feedback network, gmi, g(10), § y, gmp are respectively 、1, second amplifier 11〇, 12〇, active resistance and output stage transduction 'R01, 1102 and CP1 CP2 is the output impedance and parasitic capacitance of the first-stage and second-stage amplifiers 110 and 120, respectively, c〇uT is the output capacitance, Resr is the parasitic resistance of the output capacitor, and cml and Cm2 are the first and second Miller compensation capacitors. ROUT (=Rl||r〇p|(Rfi+Rfi)) is the equivalent output turtle resistance' where Rl and R〇p are the load impedance and the output of the power transistor respectively A l + sCm2 V ^ma SmlSmp v ( \ 1+" , ^OUT^ESR J ( \ u 5 V P-3dB J ( η Γ λ 1 + 5 CoutResr + — + ~~— +52 _ , ^/»2 Sma ) / γ ^ml^OUT ^ SmzSmp J damping coefficient is ζ = $ (5) solved by pushing down

Sml

SmlSmp (6)

Therefore, the transconductance gma of the active resistor 160 can be designed to be small to increase the control of the damping coefficient of 12 200845546, so that the transconductance gm2 of the second-stage amplifier 120 does not change, so the system feedback gain is not affected and the system is lowered. Accuracy. Degree. Please refer to "Figure 5" again. Furthermore, in order to greatly reduce the use of the Miller compensation capacitance value, the present invention proposes a shared capacitance switching technique. Based on the stability test, when the external connection is light load, a larger Miller compensation capacitor value (Cwj is needed to push the main pole to the low frequency, so that the system has enough phase angle margin. When external For heavy load, a larger second Miller compensation capacitor value is needed to increase the control of the resistance factor. Therefore, the first and second Miller compensation capacitors are available for light and heavy loads. Different requirements, so the present invention further adds a shared capacitor circuit 17Ό in the circuit, the shared capacitor circuit 17 detects the current on the power transistor 130, so that a shared capacitor (^3 is switched by the first and the first The Miller compensation capacitor or the second Miller compensation capacitor is coupled to react to different loads, which reduces the Miller capacitance required for the entire system, and because of the reduction in total capacitance, it can further extend the bandwidth and accelerate the output voltage. Stabilization time. • The sharing capacitor switching technique is implemented by using a current sensing circuit 171 to detect the current on the power transistor 130 and The result drives a Schmitt Trigger circuit 172 and a non-〇verlapping clocks generator 173. Since the Schmitt trigger circuit 172 has a hysteresis (hysteresis), it avoids mismatch in the switching. And can accelerate the transient response; the non-overlapping clock generator circuit 173 can avoid generating two clocks % and less 2 overlaps to make the first Miller compensation capacitor Cw7 and the sharing capacitor Cw3, the second Miller The first switch S W1 and the 13 200845546 one open 2 SW2 between the compensation capacitor C w 2 and the sharing capacitor C w 3 are not turned on or off at the same time. When the load is light, the power transistor 13 〇 operates in the triode position. High potential and the first switch SW1 is turned on (the first center Miller is compensated to and the J pole is pushed to the low frequency, so that the system has sufficient phase angle value, although the load current continues to increase until the power transistor 13 () operates In full

^ ^ (Z7Tregion} ^ ^ ^ ^ ^ ^ ^ ^ 1 s wi r ^ pulse 2 is the zeta potential and the second switch SW2 is turned on), the shared capacitor is inserted into the parallel with the f-miller compensation capacitor ^, the line is large The Miller 贝 Ϊ Ϊ 来 来 增加 增加 增加 增加 增加 增加 增加 增加 增加 增加 增加 增加 增加 增加 增加 增加 增加 增加 增加 增加 增加 增加 增加 增加 增加 增加 增加 增加 增加 增加 增加 增加 增加 增加 增加 增加 增加The present invention can reduce the stability of different loads by using the shared capacitance (:: parallel to the first Miller compensation electric iCw / or the second Miller compensation capacitance Cw) to reduce the stability of the different loads. The Miller capacitance value, and because of the heart, is reduced, so it can further extend the bandwidth and accelerate the %=% of the output voltage. This method has been found to reduce the required capacitance of the whole system by about 40% after testing. It will not affect its stability. See also "Figures 6-1 to 6-3" and "Figures 7-1 to 7-3" for the test results of the shared capacitor switching technology and the startup shared capacitor switching technology. And use the same test environment for 1 microfarad and heart to think 1 ohm, (2) (: 〇 "is i microfarad and ^? is 0. 3, 1 person, (3) coc / r is zero The test results of the shared capacitor switching technique are not the "6th>β1 map" stabilization time is 8 microseconds, the "6th diagram" stabilization time is 7 microseconds, and the "heart 3 diagram" stabilization time is 200845546 ίο micro Second. The test results of the start sharing capacitor switching technology are respectively "第7-1图" The time is 6 microseconds, the stabilization time of "7-2" is 5 microseconds, and the stability time of "7-3" is 5 microseconds. From the above test results, the proposed shared capacitance switching technique is reduced in addition to the whole. The Miller capacitance value required by the system can further accelerate the settling time of the output voltage without affecting its stability. However, the above is only the preferred embodiment of the present invention, and the present invention cannot be limited thereto. The scope of the invention, that is, the simple equivalent changes and modifications made by the present invention in the scope of the invention and the scope of the invention are still within the scope of the invention.

15 200845546 _ [Simple description of the diagram] Figure 1 is a schematic diagram of a low-dropout linear voltage regulator using nested Miller compensation. Figure 2 is a small signal model of Figure 1. Fig. 3 is a schematic view of the present invention in which an active power pack is added to a feedback path of a Miller capacitor. Figure 4 is a small signal model of Figure 3. Fig. 5 is a schematic view of the present invention further incorporating a shared capacitor switching on the circuit of Fig. 3. 9 Figures 6-1 to 6-3, Figure 3 shows the results of the shared capacitor switching technique. Figures 7-1 through 7-3, Figure 5 shows the test results for starting the shared capacitor switching technique. [Main component symbol description] 10, 100: Low dropout linear voltage regulator 11, 110: First stage amplifier 12, 120: Second stage amplifier • 13, 130: Power transistor 14, 140: Reference voltage generator 15 150··Node 20, 200: feedback network 160: active resistor 170: shared capacitor circuit 171: current sensing circuit 172: Schmitt trigger circuit 173: non-overlapping clock generator 16 200845546 cml: first meter Le compensation capacitor cm2: second Miller compensation capacitor: sharing capacitor SW1: first switch SW2: second switch

17

Claims (1)

200845546 X. Patent application scope: 1. A low-dropout linear voltage regulator, comprising: an input terminal receiving an input DC voltage, and an output terminal outputting a stable output voltage; a power transistor, a source thereof The input end is connected, the drain is connected to the output end, a first stage amplifier, the inverting input end is input with a reference voltage signal by a reference voltage generator, and the non-inverting input end is connected to a node, and the output end thereof A first Miller compensation capacitor is disposed between the drains of the power transistor; a second stage amplifier having an input end connected to the output end of the first stage amplifier, and an output terminal connected in series with the drain of the power transistor a second Miller compensation capacitor and an active resistor; and a feedback network connected between the drain of the power transistor and the non-inverting input of the first stage amplifier, the feedback network is composed of two resistors A voltage divider is constructed 'and the two resistors form the node. 2. The low-dropout linear voltage regulator of claim 1, wherein the active resistor is connected to a transistor in the form of a diode. 3. The low dropout linear voltage regulator of claim 1, wherein the low dropout linear voltage regulator further comprises a shared capacitor circuit, the shared capacitor circuit comprising a shared capacitor, the shared capacitor circuit Detecting a current on the power transistor, and switching the shared capacitor to be in parallel with one of the first Miller compensation capacitor and the second Miller compensation capacitor, respectively. 4. The low-dropout linear voltage regulator according to claim 3, wherein the shared capacitor circuit comprises: 18 200845546 a current sensing circuit for detecting current on the power transistor; a Schmitt trigger circuit that connects the signal of the current sensing circuit and transmits the signal to a non-overlapping clock generator to generate two non-overlapping clocks; and the second is controlled by the two clocks respectively And a switch, wherein the first switch is located between the first Miller compensation capacitor and the shared capacitor, and the second switch is located between the second Miller compensation capacitor and the shared capacitor. 5. The low-dropout linear voltage regulator of claim 3, wherein when the power transistor is operated in a triode region, the shared capacitor is switched in parallel with the first Miller compensation capacitor. The large Miller compensates for the capacitance value to push the main pole to the low frequency. 6. The low dropout linear voltage regulator of claim 3, wherein when the power transistor is operated in a saturation region, the shared capacitor is switched in parallel with the second Miller compensation capacitor. The large Miller compensates for the capacitance value to increase the damping factor control. 19