TWI247240B - Extendable squarer and square operation method - Google Patents

Abstract

An extendable squarer applied for processing a square operation of an n bit data has a bit expanding circuit and a plurality of operation units. The bit expanding circuit has n-1 bit expanding output terminals applied for outputting a plurality of bit expanding data. The operation units receive a plurality of bit codes forming the n bit data respectively based on the weight of binary. In addition, except the operation unit receiving the MSB code, the rest of the operation units receive the corresponding bit expanding data output by the bit expanding circuit respectively. The present invention evaluates the square operation value of the n bit data based on the corresponding bit expanding data and bit code.

Description

I247^4fitwf.doc/006 IX. Description of the Invention: [Technical Field] The present invention relates to a square operator, and more particularly to an expandable square operator. [Prior Art] In a VLSI circuit, a communication system, or a radar system, it is often necessary to square the signal. In the earliest days, the squared transport in the system used multipliers, but for complex computing subsystems, thousands of systems may be required that do not meet manufacturing costs. In order to solve the above problems, some techniques and circuits for square operations have begun to develop. Fig. 1 is a flow chart showing a multiplication technique of B〇〇th. Please refer to Figure 卜 where y is the product of the product, X is the product term, and subscript i is the number of bits, which is a positive integer. Booth's multiplication technique checks 3 bits and skips 2 bits for each operation, so it overlaps one bit and produces a partial product of m/2 columns, as shown in Figure 1. . Fig. 2 is a partial product matrix of a general square operator: Please refer to Fig. 2's towel A for the bit code, and the subscript for the number of bits for the individual bit code. The partial product matrix in Fig. 2 represents the square operation of a 4-bit data (Α()ΑιΑ2Α3). In addition, conventional techniques for performing square operations are also known, including Booth encoding techniques. Taking the calculation of 8-bit data as an example, when an 8 1247 orphan '.doc/006 bit data is to be squared using Booth coding technology, the 8-bit data is first expressed as follows: #—卜27 +έ626 + ... + 6. 2 ° = 5326 + 5224 + pregnancy 22 + 5. 2 ° where b is the bit code of the 8-bit data, and the subscript is used to indicate the number of bits in which the individual bit code is located. In addition, β2, & and b are the operators obtained by Booth coding technology.

The system is as follows: I Figure 3 shows the product matrix of the 8-bit Booth folded part. According to Figure 3, we can express the square value of the 8-bit data using: (2B326 +25224 +2B{22)xB02° +B0 x2° + (2B324 +2B222)xB124 + Βλ xBx24 + (2B322)xB22s ^B2xB22s + B3xB3212 Then formulate the above formula into the following formula: (household. 23 + C0) + (6 23 + ς ) 24 + 〇 P2 23 + C2 ) 28 + C3 2 〗 2 where P The general formulas of c and c are as follows:

Ci^=BixBi / = 1,...j4 + 〜2,..· + υ〇4Α·+12. %) The shortcoming of the technique used to square the data is that the volume of the circuit surface system required by these technologies cannot be greatly limited. The calculator, the object of the present invention is to effectively reduce the area of the circuit by providing an expandable square operation. 1247 orphan 〇〇 / 〇〇 6 1247 orphan doc / 〇〇 6 kinds of square operation method, can be used to square a data. A further object of the present invention is to provide an expandable square operator operation for the above. The object of the present invention is to provide an expandable square operator which can be used to process the square operation of the -n bit data. "The positive integer is not a !! The X month includes a one-dimensional expansion circuit and several The calculation unit. On the bit expansion circuit, there are η] bit expansion output ends, which are respectively used for outputting the number of bit expansion data, wherein the content of the 扩充! bit expansion data is k=\ 7=2 Where k, bj, and bj+1 are the nth bit of the n-bit data, respectively, and the bit it code of the i+i bit, and k is a positive integer. In addition, the calculation unit is weighted according to the binary ( Weight) respectively corresponding to the bit code of the data received to form the η bit, and the input of the remaining computing unit except for the calculation of the bit code of the highest bit ^, respectively corresponding to the pure bit expansion circuit The bit expands the output end to respectively correspondingly receive the output bit expansion data. In addition, each calculation unit multiplies the corresponding bit expansion data by the bit it code, and then multiplies the square of 2 And adding the square value of the corresponding bit code to get In an embodiment of the present invention, the present invention further includes an addition unit 疋' for receiving the outputs of all the calculation units. The addition unit will respectively perform the following operations on the output of one calculation unit / =0 Si is the operator generated by the calculation unit that receives the i-th bit code, and ❿Cn i is the operator generated by the calculation unit that receives the bit code of the last bit 7L, which is equal to the bit of the highest bit doc/006. In the preferred case, the present invention also includes carry weights to generate all the bit codes. From another point of view, the present invention provides a square transport to calculate an n-bit data. The squared value 'and the n-bit data is composed of η: bit code, and η is a positive integer. The steps of the square operation method of the present invention are as follows. First, 'generate n-丨 bit expansion data , wherein the content of the i-th bit expansion data is λ-3 n-2 k=lj=2 and bn_, bj, and bj+l are the first 丨, j, and i+l bits of the n-bit data, respectively. Bit code, and i, j, and k are both positive integers. Then, except for the highest bit In addition to the bit code, each bit code is multiplied by one of the bit expansion data, and several calculated values are generated. Then each calculated value is multiplied by the square of 2, and then the corresponding bit is added. The operator obtains several operators by the square value of the code. Finally, these operators perform the following operations to obtain the square value of the bit data /=0 where A is the operator corresponding to the i-th bit code. And L is the operator of the highest bit, which is equal to the square of the bit code of the highest bit. In the embodiment of the present invention, the highest bit of the 11-bit data The code system represents: the number bit is used to determine whether the n-bit data is positive. When the n-bit material is negative, then all the bit expansion data are inverted and then operated. V, the above-mentioned several mathematical formulas provided by the present invention, such that the 12472240 13853 twf.doc/006 calculation unit obtains the relevant transport elements according to the bit code and the corresponding bit expansion data respectively, and further Calculate the squared value of the n-bit data. According to these equations, the circuit volume of the expandable square operator provided by the present invention can be effectively reduced, thereby reducing the hardware cost and volume of the overall system. The above and other objects, features, and advantages of the present invention will become more apparent and appreciated. [Embodiment] In order to enable the skilled person to understand the spirit of the present invention, a mathematical model of the square operation of 4-bit data and 8-bit data is first described. We first make a 4-bit data into the following expression: +b222 ^b{21 +b02° The bit code in the 4-bit data, and the subscript is used to represent the number of bits in the code. __ can be used to organize the square of the 4-bit data into the matrix in Figure 4, and the end of the figure + a four-bit second invention of the preferred embodiment - the operation matrix of the 兀^枓枓 枓 运.夂 夂 ',,, map? I: Yes, the matrix h (-2b32, 2b22, 2bi2i) xbQ2, bQxb〆彳 in the figure of Figure 4 + (~2ό322 +2ό221)χόι22 x^22 + (-2b32l)xb224 +b2xb224 .... (1) + b3xb326 Then classify the formula (1) into the following equation: where S and c can be expressed as follows: (2) doc/〇〇6 5 广(巧22+CV) ho, ···,. , = 〇"·., 2 - s,, P in the formula (2) is defined as: , = 〇, ···, 2: J, J will be. | The brackets are defined as ΒΕ, , you can change it.

Pi = BEi X b.......... — z ............-......(3) will be - we will talk about 8平方 The square operation of the data. Similarly, first expand the 8-bit 7〇 data into the following formula: B - ~672 + 0626 +6525 +6424 +6323 +6222 +^21 +Z>02° Then we will square the 8-bit it data to Figure 5 The matrix is shown. FIG. 5 illustrates an operational matrix of an 8-bit quadratic operation in accordance with a preferred embodiment of the present invention. Referring to Figure 5, we can also expand the air array in the following equation: ()) = (-26727 ten 26626 + 26525 + 23⁄424 + 2M3 + 26222 + 26, 21) X 6. 2% 6 x 6 2〇+ {-2b, 26 +2b625 +2b52A +2b423 +2b,22 +2b22l)xbx22 +blX bx 22° ° + (-267 25 + 265 24 + 23⁄4 23 + 26322 + 262 21) x 24 + x Z> 2 24 ' + {-2b, 24 -f 2*6 23 + 2Z?5 22 + 23⁄4 21) x 63 26 + 63 x 63 26 + (-26723 +2i622 +26521)x6428 +b4xb42s ^-(-2b722 +2b62l) Xb5210 +b5xb5210 + (-2b72l)xb62u+b6xb6212 + i7 xZ>7214 Then the above formula is also organized into: 50 + ^ 22 + 52 24 + 53 26 + 54 28 + 55 210 + 56 212 + C7 214 and S and C is still expressed as:

Sj:, Pj2l+Cf, 7 = 0,-..,6 C. = b; xb; where P is: ίο 12473⁄4^ oc/006 Pi =(-^26^+0625^/ = 0,... ,6

+6/+i2〇)x^ and defined

The part of the parentheses in Pi is BEi, and the same can be rewritten as the (3) @6 series of steps of the following method which does not follow a preferred embodiment of the present invention. The above-mentioned 4-bit data and 8-bit data: = the result of the square-way data are summarized, and the present invention proposes that the n-bit squared motion = method' is shown in Fig. 6. Referring to FIG. 6, according to the steps of this embodiment, Benleming can be used to process the square operation of the n-bit data. And the ordinary data can be expanded into the following formula: First, as described in step S61, generating n] bit expansion data be, and the i-bit expansion data BE can be expressed as follows: n-3 n -2 A wide · + ΣΣΜ ~ μ2 〇 k = \ y = 2 = nine 2 ~ 4 Λ _22 " -3- ' + ... + 622 Ά +12. / = Then, as described in step S620, multiplying each bit expansion data by the corresponding bit code to generate a plurality of calculated values, such as P of Table 8 of the above formula (3), and proceeding to step S630, Multiply each calculated value p by the square of 2 and then add the square of the corresponding bit code to obtain the operator s, as shown in the figure: ^^ = 22 + Cj) j 2 0"··, η - 2 c / H / = 〇, ·., -1 Finally, as described in step S640, the result of the square operation of the n-bit data based on all the operators s is: M) The above η bit data The highest bit code can be used as the $ yuan to determine the positive and negative of the η bit data. If the η bit 1247 is 〇^/006 negative value, then the above bit expansion data be must be inverted. Figure 7 is a block diagram showing the architecture of a bit-expandable square operator according to a preferred embodiment of the present invention. Referring to Figure 7, the expandable square operator in this embodiment is shown. It is designed according to the square operation method of Fig. 6. In Fig. 7, the 'bit expansion circuit 701 has η-ΐ bit expansion output terminals, which can be divided. The n-1 pen bit expansion data (BEg~BEn_2) is sent to the calculation unit (A〇~An_2). In addition, in the architecture of Fig. 7, the present invention includes a number of premature (Α〇Αη·1) ' It receives the n bit codes used to form the n-bit data respectively according to the weight of the carry. Referring to FIG. 7, in the embodiment, the present invention further includes the decoder 703 and Adding unit 705. The decoder 703 is coupled to the input unit of the computing unit (Α〇~An-ι) for generating n bit codes to the corresponding computing unit, and each computing unit is based on the input thereof. Data, an operator is generated to the addition unit 705 to perform square operation on the n-bit data. When the decoder 703 decodes an n-bit data into ^bit codes (bG~bn·!), these will be respectively The bit code (bG~U is sent to the calculation unit (Ag~An1). At this time, the bit expansion circuit 701 also generates the η·ι pen bit expansion data (BE()~Bu to the calculation unit (A〇~ An_2). Except for the unit #··· which receives the highest-order bit code, the remaining calculation units (aq~An_2) will As shown in steps S620 and S630 of FIG. 6, the operator (SG~Sn_2) is generated according to the corresponding bit extension data BEi and the bit code bi to the addition unit 705. The calculation unit An1 then receives the received bit code. After taking the square value of bn_!, the operator Cn" is also generated to the adding unit 705. The adding unit 7〇5 calculates the output according to the output of all the calculating units (A〇~Ay) as described in step S64. The square value of the bit data is 0 12 1247. doc/006 FIG. 8 is a block diagram showing the architecture of an i6-bit charging square operation according to an embodiment of the present invention. Referring to Fig. 8, in order to be able to process a large data operation with a smaller circuit area, the expandable square operator of the present invention can also adopt a modular technique. For example, the expandable square operator of Fig. 8^ also includes a bit expansion circuit 8〇, a decoder 803, and an addition unit 805. However, in particular, the computing unit therein is implemented by a computing module such as 810, and the working principle thereof can be referred to FIG. 6 and FIG. 7, and therefore will not be described again.

Although in Figure 8, the 16-bit scalable square operator is implemented as a modular technique, it is not limited to a 16-bit scalable square operator. Those skilled in the art will recognize that a 4-bit, 8-bit or other scalable expandable square operator can be implemented in the form of Figure 8, and the calculations contained in each of the operational modules are originally invented. No added 0

In summary, according to the scalable square operation H designed by the square operation method of the present invention, the η bit data can be squared. However, in the present invention, the η-bit data is directly halved, and the rules are summarized to design an expandable square operator. Therefore, the present invention can achieve a low hardware cost. In addition, the expandable square operator of the present invention can also be designed in a modular manner, which further reduces the area of the hardware, thereby reducing the hardware cost of the overall system. While the present invention has been described in its preferred embodiments, the present invention is not intended to limit the invention, and the present invention may be modified and modified without departing from the spirit and scope of the invention. The scope of protection is subject to the definition of the scope of the patent application. Sigh 13 1247 orphan doc/006 [Simple diagram of the diagram] Figure 1 is a flow chart showing the multiplication technique of Booth. Figure 2 is a partial product matrix of a general square operator. FIG. 3 is a diagram showing an 8-bit Booth folded partial product matrix. 4 is a diagram showing an operation matrix of a 4-bit data squaring operation in accordance with a preferred embodiment of the present invention. FIG. 5 illustrates an operational matrix of an 8-bit data squaring operation in accordance with a preferred embodiment of the present invention. 6 is a flow chart showing the steps of a square operation method in accordance with a preferred embodiment of the present invention. 7 is a block diagram showing the architecture of an n-bit scalable square operator in accordance with a preferred embodiment of the present invention. FIG. 8 is a block diagram showing the architecture of a 16-bit scalable square operator according to an embodiment of the invention. [Main component symbol description] 701, 801: bit extension circuit 703, 803: decoder 705, 805: addition unit 810: operation module S610, S620, S630, S640 · · square operation method step flow 14

Claims (1)

'.doc/006 I2472^Qwf· X. Patent application scope: L. An expandable square operator for processing the square operation of the material, and 4 is not (four) positive integer square operator including ·· t, charging With eight circuits 'with W bits to expand the output, := corresponds to output a large number of bits to expand the data, which is the first! The content of the unit 兀 expansion data is that the eight n-1 and bj+1 are the bit code of the n-th data and the (1)-bit, respectively, and the .... and, the positive/number η·1 and the respectively: The calculation unit is configured to receive a plurality of bits of the n-bit data according to a weight code of the binary: * In addition to the calculation unit that receives the bit code of the highest bit, the calculation unit The input is respectively corresponding to the output terminals of the bits for respectively receiving the bit expansion data, and the mothers are divided into a plurality of squares, and the corresponding bits are expanded and multiplied by a square of 2, and In addition, the corresponding + square value is used to obtain an operator. 瞀./· The expandable square operation described in item 1 of the patent application scope further includes an adding unit for receiving the calculation sheets. The pipe is rained out, and the outputs of the calculation units are respectively subjected to the following operations: n~2 +02(4) Σ\22, 15 where & is the operator generated by the calculation unit receiving the second bit code, and An operator generated by a computing unit that receives the highest-order bit code, which is specific to the highest bit The squared value of the meta-code. The expandable squared transport described in item 1 of the patent application scope further includes a decoder for generating the bit codes according to the binary weights. The expandable squared difference described in the scope of the patent is as follows, wherein the highest bit code of the n-bit data represents the symbol bit, which is used to determine whether the !! bit material is positive. The square operation method is used to calculate the square value of the 1-bit data, and the η-bit data is composed of η bit codes, where η is a positive integer, and the square operation method includes the following steps: = two bits of expansion data 'where the first bit expands the population = 1 Ο Ο " — 3 λ — 2 where bw'bj釭匕 +1 is the bit code of the 』... element, and... and , then; chest 2: take the bit of the bit outside the code 'each of these bit code points m should be multiplied (four) some bits to expand the data of the towel - a calculated value; 7 raw soil eve _ will each Multiplying a calculated value by the square of 2, plus the square of the corresponding bit weight to obtain a majority of the operators; The operator performs the following operations. The square of the previous data is different from the η bit element 16 doc/006 1247240.. The operator corresponding to the bit code of the bit, which is equal to the square value of the bit code of the highest bit. 6. The square operation method as described in claim 5, wherein the highest bit of the n-bit data The metacode system represents a symbol bit for determining whether the n-bit data is a positive value. 7. The square operation method according to claim 5, wherein when the n-bit data is negative, then Invert all of the bit expansion data before performing the operation. 17