TWI246130B - Stable package method for miniaturized transistor - Google Patents

Stable package method for miniaturized transistor Download PDF

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Publication number
TWI246130B
TWI246130B TW093124249A TW93124249A TWI246130B TW I246130 B TWI246130 B TW I246130B TW 093124249 A TW093124249 A TW 093124249A TW 93124249 A TW93124249 A TW 93124249A TW I246130 B TWI246130 B TW I246130B
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Taiwan
Prior art keywords
die
lead frame
resin layer
layer
package
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TW093124249A
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Chinese (zh)
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TW200426959A (en
Inventor
Jung-Shing Tz
Shr-Yi Jang
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Domintech Co Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L24/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/4826—Connecting between the body and an opposite side of the item with respect to the body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73215—Layer and wire connectors

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)

Abstract

A table package method for miniaturized transistor is provided. It comprises the following steps. (A) Wafer dicing: use wafer dicer to split the chips. (B) Combining screen: let the chip face that is intended to install the package resin layer be adhered to a screen, and each through hole of the screen corresponds to each chip. (C) Forming package resin layer: let the package resin pass the through hole of the screen to coat the designated side of each chip. Each chip bottom has a package resin structure. (D) Coating adhesive material layer: install an adhesive material layer on the bottom surface of the package resin layer. (E) Pressing/bonding lead frame: adhere the chip on the lead frame by the adhesive material layer. (F) Soldering and packaging: connect the signal terminals of the selected chip with the lead of the lead frame by metal wires. Then conduct package step of the metal wires. Therefore, the stable package method for miniaturized transistor is achieved.

Description

1246130 五、發明說明（1) 【發明所屬之技術領域】 本發明係有關一種穩定封裝之精小化電晶體製法，特 別係指一種可製成穩定封裝之精小化電晶體其封裝製造方 法設計者。 【先前技術】 按，傳統的電晶體結構係將晶粒置設於於一晶墊上， 並於晶粒之訊號接點與導線架引腳連接金屬線後，透過外 圍一層密封狀之封膠體封裝結構，以製成一電晶體，惟因 為此種晶圓封裝製程係使完成的電晶體體積過大，故不適 於現今電子產品精巧化之設計需求。其後改良的精小化電 晶體結構如第四圖所示，係將一晶粒1 0直接黏固於一導線 架2 0之引腳2 0 1上，期藉此獲得電晶體體積縮小之效果， 惟其製造程序上必需選定於各晶粒1 0之底面處，貼設有特 定尺寸並精準對應導線架2 0各引腳2 0 1之膠帶3 0，藉此利 用該膠帶3 0黏固該晶粒1 0位於導線架2 0上；然此種應用膠 帶3 0黏固晶粒1 0於導線架2 0上之製法，不僅在黏貼該膠帶 3 0前必須經過繁瑣的形裝、尺寸等裁切步驟，且不易將裁 切成細小狀態的膠帶3 0貼固於晶粒1 0選定位置，尤其該膠 帶3 0本身係為高貴的物品，經過上述廢料裁切、對準黏貼 等製程，將使封裝成本增加；另者，此種精小化晶圓封裝 技術應用，僅利用該膠帶3 0黏固晶粒1 0於導線架2 0上，則 將使晶粒1 0必需直接承受作用於導線架2 0之外界壓力，因 此容易造成該晶粒1 0毁損瑕疵。 【發明内容】1246130 V. Description of the invention (1) [Technical field to which the invention belongs] The present invention relates to a method for manufacturing a miniaturized transistor with a stable package, and particularly to a package manufacturing method design for a miniaturized transistor with a stable package. By. [Previous technology] According to the conventional transistor structure, the die is placed on a crystal pad, and after the signal contact of the die is connected to the lead wire of the lead frame, it is encapsulated through a layer of sealed gel on the periphery. Structure to make a transistor, but because this wafer packaging process makes the completed transistor too large, it is not suitable for today's sophisticated design of electronic products. Subsequently, the improved miniaturized transistor structure is shown in the fourth figure, and a crystal grain 10 is directly adhered to a lead 21 of a lead frame 20 in order to obtain a reduction in the size of the transistor. Effect, but in the manufacturing process, it must be selected at the bottom surface of each die 10, and a tape 3 0 of a specific size and accurately corresponding to each lead frame 2 0 2 0 1 is attached, thereby using the tape 3 0 to fix The die 10 is located on the lead frame 20; however, this method of applying the tape 30 to fix the die 10 on the lead frame 20 not only needs to be complicatedly shaped and sized before sticking the tape 30 Wait for the cutting step, and it is not easy to stick the tape 30 cut to a small state at the selected position of the crystal grain 10, especially the tape 30 itself is a noble article, and after the waste material cutting, alignment and pasting processes, etc. Will increase the packaging cost; In addition, the application of this miniaturized wafer packaging technology, using only the tape 30 to fix the die 10 on the lead frame 20, will make the die 10 must bear directly Acting on the outer pressure of the lead frame 20, it is easy to cause the grain 10 to be damaged. [Summary of the Invention]

第5頁 1246130 五、發明說明（2) 本發明主要目的，係在提供一種穩定封裝之精小化電 晶體製法，特別係指一種可製成穩定封裝之精小化電晶體 其封裝製造方法設計，藉此達成製造成本降低及電晶體結 構強度增進之效果。 依上述目的，本發明之封裝製造方法實施内容係包括 有下列步1驟（A)晶圓切割·運用晶圓切割機將各晶粒切割 分離；（B)結合網板：選用一板面設有數透孔之網板，令 預定設置封裝樹脂層之晶圓一面貼合於該網板，使該網板 上的各透孔對應於各晶粒；（C)成型封裝樹脂層：令封裝 樹脂透過網板之透孔塗置於各晶粒選定處，使晶粒底面具 有一層封裝樹脂層結構；（D)塗佈接著材料層：於該封裝 樹脂層底面設有一層接著材料層；（E)壓合導線架：將各 晶粒以其層接著材料層黏固於一具有複數引腳之導線架上 ;(F)焊線及封裝：選定晶粒之訊號接點連接金屬線至導 線架之引腳，並進行金屬線部位之封膠體封裝步驟，藉此 組成穩定封裝之精小化電晶體。 其次，本發明之封裝製造方法實施内容並可包括下列 步驟（a)結合網板：選用一板面設有數透孔之網板，令預 定設置封裝樹脂層之晶圓一面貼合於該網板，使該網板上 的各透孔對應於各晶粒；（b)成型封裝樹脂層：令封裝樹 脂透過網板之透孔塗置於各晶粒預定位置之選定處，使該 晶圓底面具有一層封裝樹脂層結構；（c)晶圓切割：運用 晶圓切割機將各晶粒及封裝樹脂層切割分離；（d)塗佈接 著材料層：於各該晶粒底部之封裝樹脂層底面設有一層接Page 5 1246130 5. Description of the invention (2) The main purpose of the present invention is to provide a stable packaged miniaturized transistor manufacturing method, especially a package manufacturing method design of a miniaturized transistor that can be made into a stable package. In order to achieve the effect of reducing manufacturing costs and increasing the strength of the transistor structure. According to the above purpose, the implementation content of the package manufacturing method of the present invention includes the following steps: (1) wafer dicing; using a wafer dicing machine to cut and separate each die; (B) combining a stencil: using a plate surface design A stencil with a few through holes, so that one side of the wafer on which the encapsulating resin layer is scheduled is attached to the stencil, so that each through hole on the stencil corresponds to each die; (C) Forming the encapsulating resin layer: making the encapsulating resin The through-holes of the screen are coated on the selected positions of the crystal grains so that the bottom surface of the crystal grains has a layer of encapsulating resin layer structure; (D) Coating and bonding material layer: a layer of bonding material is provided on the bottom surface of the encapsulating resin layer; ) Compression lead frame: each die is bonded to a lead frame with a plurality of pins with its layer and material layer; (F) bonding wire and package: the signal contact of the selected die connects the metal wire to the lead frame Pins, and the step of encapsulating the metal wire with a colloidal packaging step, thereby forming a stable miniaturized packaged transistor. Secondly, the implementation content of the packaging manufacturing method of the present invention may include the following steps: (a) Combining a stencil: a stencil with a number of through holes on its surface is selected, so that one side of a wafer on which a packaging resin layer is to be arranged is attached to the stencil So that each through hole on the screen corresponds to each die; (b) molding the encapsulation resin layer: the packaging resin is applied through the through holes of the screen to the selected position of the predetermined position of each die to make the bottom surface of the wafer Has a layer of encapsulating resin layer structure; (c) Wafer dicing: use a wafer dicing machine to cut and separate each die and the encapsulating resin layer; (d) Coating and bonding material layer: the bottom surface of the encapsulating resin layer at the bottom of each die With a floor connection

1246130 五、發明說明（3) 著材料層結構；（e )壓合導線架：將各晶粒以其一層接著 材料層黏固於一具有複數引腳之導線架上；（f )焊線及封 裝：選定晶粒之訊號接點連接金屬線至導線架之引腳，並 進行金屬線部位之封膠體封裝步驟，藉此組成本發明穩定 封裝之精小化電晶體。 【實施方式】 茲依附圖實施例將本發明之製造方法、步驟特徵及其 他之作用、目的詳細說明如下： 請參考第一圖所示，本發明所為『穩定封裝之精小化 電晶體製法』設計，其一較佳實施例係包括下列步驟： (A) 晶圓切割：係運用晶圓切割機將一片狀晶圓之各 晶粒切割分離，其中該片狀晶圓成型前之相關製程，係為 習知的技術領域範圍，故不另贅述； (B) 結合網板：選用一板面設有數透孔之網板，令預 定設置一封裝樹脂層之晶圓一面貼合於該網板上，使該網 板的各透孔對應於各晶粒選定位置； (C) 成型封裝樹脂層：令封裝樹脂透過網板之透孔置 設於各晶粒選定處，使一晶粒底面具有一層封裝樹脂層結 構，其t結合成型封裝樹脂層之方法包含可為網屏印刷法 (S c r e e η )、點膠法（D i s p e )及模型塑造法（Μ 〇 i d )等 ，並且可經過烘烤程序，使該封裝樹脂層迅速凝固； (D) 塗佈接著材料層：於該封裝樹脂層底面設有一層 接著材料層，其中結合接著材料層之方法包含可為網屏印 刷法（S c r e e η )及點膠法（D i s p e );1246130 V. Description of the invention (3) Material layer structure; (e) Compressed lead frame: each die is bonded to a lead frame with a plurality of pins with a layer and a material layer; (f) bonding wire and Packaging: The signal contacts of the selected die are used to connect the metal wires to the pins of the lead frame, and the step of encapsulating the metal wires is performed to form the miniaturized transistor of the stable package of the present invention. [Embodiment] The manufacturing method, step features, and other functions and purposes of the present invention will be described in detail according to the embodiments of the drawings as follows: Please refer to the first figure, the present invention is "the production method of miniaturized package for stable packaging" A preferred embodiment of the design includes the following steps: (A) Wafer dicing: a wafer dicing machine is used to cut and separate the individual dies of a piece of wafer, and the related process before the piece of wafer is formed This is the scope of the conventional technical field, so I won't go into details; (B) Combine the screen: select a screen with a number of through holes on the surface of the board, so that the side of the wafer intended to be provided with a packaging resin layer is attached to the screen. On the board, each through hole of the screen corresponds to the selected position of each die; (C) Molding the packaging resin layer: the packaging resin is placed at the selected position of each die through the through holes of the screen to make a bottom surface of a die It has a layer of encapsulating resin layer structure, and the method of t combining and forming the encapsulating resin layer includes screen printing method (Scree η), dispensing method (D ispe), and model molding method (MIMO), etc. Baking process to make the seal The resin layer solidifies quickly; (D) Coating and bonding material layer: a bonding material layer is provided on the bottom surface of the encapsulating resin layer, and the method of combining the bonding material layer includes screen printing method (Scree n) and dispensing method (D ispe);

第7頁 1246130 五、發明說明（4) 呈古(!)叙壓合導線架：將各晶粒以其接著材料層點固於一 數排列狀弓丨腳之導線架上，使該晶粒與各引腳 面士占者，並且可經過供烤程序，使該封裝樹脂層迅速凝固 (F)焊線及封裝：即選定該晶粒之訊號接點連 m泉架之引腳，並進行金屬線部位之封膠體封裝步驟 電4m j方；，即可組成-種穩定封裝之精小化 :ϊ 構如第三圖所示，係包括-晶粒 :有封装樹脂層2，於該封裝樹脂層2下面具有 :妾者材料層3，並藉該接著材料層3黏固於— 或矩陣排列狀引腳4 i之導線架4上 ：； 點及選定引腳41間連結有全屬綠R ^ i i 部位形成有局部封裝之封膠该金屬線5連結 惟’其中該⑹成型封裝樹脂層 =裝，層2黏固導線架4，是以，本發明？揭门;错 广Λ，Λ可Λ省後序的⑻塗佈接著材料層步驟，藉此在 加成型制封“刚製造程序[即可直接進行⑻壓合導 i:程二俾組ΐ穩定封裝之精小化電晶體結構。 下列步驟： 斤不，本發明另-實施例係包括 (a)結合網板：選用—板面設有數透孔 定=封裝樹脂層之晶圓—面貼合於該網板上，使該網板 的各透孔對應於該晶圓之各晶粒預定位置；Page 7 1246130 V. Description of the invention (4) The ancient (!) Narrated bonded lead frame: each crystal grain is fixed on the lead frame with a number of arches and legs with its subsequent material layers to make the crystal grain And each pin can be occupied by the owner, and the baking resin layer can be rapidly solidified through the baking process (F) bonding wire and packaging: that is, the signal contact of the die is connected to the pin of the m spring rack, and the The step of encapsulating the metal wire part with a gel encapsulation step is 4m square; that is, it can be composed-a kind of stable miniaturization of the package: ϊ The structure is shown in the third figure, which consists of-grain: there is an encapsulating resin layer 2 in the package The resin layer 2 has the following: a material layer 3, and the material layer 3 is adhered to the lead frame 4 of the matrix-shaped pins 4 i by: and the dots and the selected pins 41 are all green. The R ^ ii part is formed with a partially encapsulated sealant, and the metal wire 5 is connected, but the resin layer = packed, and the layer 2 is fixed to the lead frame 4. So, the present invention? Uncover the door; 错 Λ, Λ can save the subsequent ⑻ coating followed by the material layer step, so as to make the seal process in the "additional manufacturing process [you can directly carry out the 合 compression guide i: 程 二 俾 组 ΐ stability" The package miniaturizes the transistor structure. The following steps: No, another embodiment of the present invention includes (a) a combination screen: optional-a wafer with a number of through holes on the surface of the plate = a resin layer on the surface-surface bonding On the screen, make each through hole of the screen correspond to a predetermined position of each die of the wafer;

第8頁 1246130 五、發明說明（5) (b )成型封裝樹脂層：令封裝樹脂透過網板之透孔置 設於各晶粒選定處，使晶粒底面具有一層封裝樹脂層結構 ，其中結合成型封裝樹脂層之方法包含可為網屏印刷法（ Screen )、點膠法（D i s p e )及模型塑造法（Μ ο 1 d )等， 並且可經過烘烤程序，使該封裝樹脂層迅速凝固； (c) 晶圓切割：運用晶圓切割機將各晶粒及已經烘乾 成型之封裝樹脂層切割分離； (d) 塗佈接著材料層：於該封裝樹脂層底面設有一層 接著材料層，其中結合接著材料層之方法包含可為網屏印 刷法（S c r e e η )及點膠法（D i s p e ); (e )壓合導線架：將各晶粒以其接著材料層黏固於一 具有複數排列狀引腳之導線架上，使該晶粒與各引腳選定 面黏著，並且可經過烘烤程序，使該接著材料層迅速凝固 (f)焊線及封裝：亦即如上所述，選定該晶粒之訊號 接點連接金屬線至導線架之引腳，並進行金屬線部位之封 膠體封裝步驟； 藉此上述製造方法步驟，亦可組成如第三圖所示包括 有一晶粒1 、封裝樹脂層2 、接著材料層3 、導線架4 、 金屬線5及封膠體6之穩定封裝精小化電晶體。 運用本發明穩定封裝之精小化電晶體製法設計，由於 係可採以該成型封裝樹脂層及塗佈接著材料層方法，使所 述晶粒可黏固於一導線架上，其製造程序故可避免採用單 價高昂的習知膠帶3 0，並避免必須精準裁切該膠帶3 0尺寸Page 8 1246130 V. Description of the invention (5) (b) Molding the encapsulating resin layer: The encapsulating resin is placed through the through holes of the stencil at selected positions of each die, so that the bottom surface of the die has a layer of encapsulating resin layer structure, in which The method for forming the encapsulating resin layer includes screen printing method (Screen), dispensing method (D ispe), and model forming method (M ο 1 d), etc., and the encapsulating resin layer can be rapidly solidified through a baking process. ; (C) Wafer dicing: use a wafer dicing machine to cut and separate each die and the packaging resin layer that has been dried and formed; (d) Coating and bonding material layer: a bonding material layer is provided on the bottom surface of the packaging resin layer In which, the method of bonding the material layers includes screen printing (Scree η) and dispensing (D ispe); (e) press-bonded lead frame: each die is bonded to a bonding layer with a bonding material layer On a lead frame with a plurality of arranged pins, the die is adhered to the selected surface of each pin, and the bonding material layer can be rapidly solidified through a baking process (f) bonding wire and package: as described above , Select the signal contact of the chip The metal wire is connected to the lead of the lead frame, and the encapsulation step of the metal wire is performed. According to the above manufacturing method steps, it can also be composed as shown in the third figure, which includes a die 1, a packaging resin layer 2, and a material layer. 3. Stable package of lead frame 4, metal wire 5 and sealing compound 6, miniaturized transistor. The design of the miniaturized transistor manufacturing method using the stable package of the present invention is designed by using the method of forming and encapsulating the resin layer and coating the material layer, so that the crystal grains can be fixed on a lead frame. Can avoid the use of expensive conventional tape 30, and avoid the need to accurately cut the tape 30 size

第9頁 1246130 五、發明說明（6) 及形狀步驟，俾能有效的降低精小化電晶體之製造成本。 其次因本發明可簡易實施有一封裝樹脂層2位於晶粒1底 面，藉該封裝樹脂層2支撐晶粒1 ，並供塗設接著材料層 3使晶粒1可黏固於導線架4上，故能利用該封裝樹脂層 2保護晶粒1 ，避免外力作用於導線架4時，同時損及該 晶粒1 ，故能確保精小化電晶體之封裝品質。 綜上所述，本發明『穩定封裝之精小化電晶體製法』 設計，已確具實用性與發明性，手段之運用亦出於新穎無 疑，且功效與設計目的誠然符合，已稱合理進步至明。為 此，依法提出發明專利申請，惟懇請鈞局惠予詳審，並 _ 賜准專利為禱，至感德便。Page 9 1246130 V. Description of the invention (6) and shape steps can effectively reduce the manufacturing cost of miniaturized transistors. Secondly, because the present invention can be easily implemented, an encapsulating resin layer 2 is located on the bottom surface of the die 1. The encapsulating resin layer 2 supports the die 1 and is provided with a coating material layer 3 so that the die 1 can be fixed on the lead frame 4. Therefore, the die 1 can be protected by using the encapsulating resin layer 2 to prevent the die 1 from being damaged at the same time when an external force is applied to the lead frame 4, so that the packaging quality of the miniaturized transistor can be ensured. In summary, the design of the "minimized transistor manufacturing method for stable packaging" of the present invention is indeed practical and inventive. The use of the means is also novel and undoubted, and the efficacy and design purpose are indeed in line with each other, which has been called a reasonable progress. To Ming. To this end, an application for an invention patent was filed in accordance with the law, but the Bureau is kindly requested to review it in detail, and _ grant the patent as a prayer, to the utmost convenience.

第1〇頁 1246130 圖式簡單說明 【圖式簡單說明】 第一圖為本發明穩定封裝之精小化電晶體製法實施例系統 圖。 第二圖為本發明穩定封裝之精小化電晶體製法另一實施例 糸統圖。 第三圖為本發明穩定封裝之精小化電晶體示意圖。 第四圖為習知精小化電晶體之結構示意圖。 【主要元件符號說明】 (A) 晶圓切割， (B) 結合網板； (C) 成型封裝樹脂層； (D) 塗佈接著材料層； (E) 壓合導線架； (F )焊線及封裝； (a) 結合網板； (b) 成型封裝樹脂層； (c )晶圓切割， (d) 塗佈接著材料層； (e) 壓合導線架； (f )焊線及封裝；Page 10 1246130 Brief description of the drawings [Simplified description of the drawings] The first diagram is a system diagram of an embodiment of a stable and compact miniature transistor manufacturing method of the present invention. The second figure is a general view of another embodiment of a method for manufacturing a miniaturized transistor with stable packaging according to the present invention. The third figure is a schematic diagram of the miniaturized transistor of the stable package of the present invention. The fourth figure is a schematic diagram of a conventional miniaturized transistor. [Description of main component symbols] (A) Wafer dicing, (B) Bonding stencil; (C) Molded packaging resin layer; (D) Coating and bonding material layer; (E) Press-bonded lead frame; (F) Bonding wire And packaging; (a) bonded screen; (b) molding and packaging resin layer; (c) wafer dicing, (d) coating and bonding material layer; (e) laminated lead frame; (f) wire bonding and packaging;

12461301246130

第12頁Page 12

Claims (1)

1246130 六、申請專利範圍 丄、一種穩定封裝之精小化電晶體製法，係包括： 晶圓切割：將片狀晶圓之各晶粒切 結合網板：選用—板面設有數透孔之網^ ’人 定設置-封裝樹脂層之晶圓一面貼合於：： 該網板的各透孔對應於各晶粒選定位置； 使 成型封裝樹脂層：令封裝樹脂透過網 設於各晶粒選定處，使一 a 透孔置 唐緒構； t曰曰粒底面具有-層封農樹脂 壓合導線架：將晶粒以上述封裝樹脂 具有複數排列狀引腳之導線架上，使： 選定面黏著； 讯Η各弓丨腳 及封裝：選定該晶粒之訊號接 至導線架之引腳，並進行金屬 2 業，藉此可组成穩定封裝之精小化電晶2體料作 -種穩定封裝之精小化電晶體製法，係、包括. 亡網板：選用—板面設有數透孔之網板 疋汉置封裝樹脂層之晶圓一面貼合於該網板吏 該網板的各透孔對應於各晶粒選定位置；板上使 ，里封t树月日.令封裝樹 晶粒選定處，使-晶粒底面具有-層 切割分=^』將片狀晶圓之各晶粒及該封裝樹脂層 塗佈接著材料層：於該封裝樹脂層底面設有一層1246130 VI. Scope of patent application 丄, a stable packaged miniaturized transistor manufacturing method, including: Wafer dicing: cutting each die of a chip wafer and combining a stencil: optional-a net with several through holes on the surface ^ 'Man-made setting-the wafer of the encapsulating resin layer is attached on one side: each through hole of the screen corresponds to the selected position of each die; the forming of the encapsulating resin layer: the encapsulating resin is set through the net to be selected on each die A through hole is placed in the Tango structure; t said that the bottom surface of the grain has a layer of encapsulated agricultural resin compression lead frame: the die is on the lead frame with the above-mentioned encapsulating resin having a plurality of arranged pins, so that: the selected surface is adhered; Signal bows and packages: The signals of the die are selected to be connected to the pins of the lead frame, and the metal 2 industry is used to form a stable packaged miniaturized transistor 2 body as a stable package. Method for making miniaturized transistor, including and including. Dead stencils: optional-stencils with several through holes on the surface of the slab. One side of the wafer with the sealing resin layer is attached to the through holes of the stencil. Corresponds to the selected position of each die; ， 封 封 月 月 日. Make the package tree grains selected, so that-the bottom surface of the grains has-layer dicing = ^ "Coat each chip of the wafer and the packaging resin layer and then the material layer: There is a layer on the bottom surface of the encapsulating resin layer 第13頁 1246130 六、申請專利範圍Page 13 1246130 VI. Application scope 接著材料層； 壓合導線架：將晶粒以其接著材料層黏固於一具 有複數排列狀引腳之導線架上，使該晶粒與各引腳選 定面黏著； 焊線及封裝：選定該晶粒之訊號接點連接金屬線 至導線架之引腳，並進行金屬線部位之封膠體封裝作 業，藉此可組成穩定封裝之精小化電晶體。 3 4 如申請專利 製法，其中 塗佈接著材 著材料層， 如申請專利 化電晶體製 網屏印刷法 造法（Μ ο 1 d 如申請專利 化電晶體製 網屏印刷法 礼阳… θ取〜/|、月M、，藏晶j ，該成型封裝樹脂層之後，包括可實施_ 料層，而於該封裴樹脂層底面設有一層^ 並提供與導線架壓合黏固。 摩巳圍=1項或第2項所述穩定封裝之精^ 其中，該成型封裝樹脂層之方法包4 、 ） 點膠法（D i s p e )及模型塑 )0 範圍第2項或楚0 M 法，其 ，昂3項所述穩定封裝之精， ' ’該塗佈接著材料層之方法包4 Creen )及點膠法（Dispe )。Next, the material layer; Compression lead frame: the die is adhered to the lead frame with a plurality of arranged pins with its adhesive material layer, so that the die is adhered to the selected surface of each pin; bonding wire and package: selected The signal contact of the die is connected with the metal wire to the lead frame pin, and the encapsulation operation of the metal wire part is performed, thereby forming a stable and compact miniaturized transistor. 3 4 If a patent application method is used, in which the material layer is coated and adhered, such as the patented transistor screen manufacturing method (M ο 1 d) If the patented transistor screen manufacturing method is used, Li Yang ... θ 取~ / |, Month M, and Tibetan crystal j, after the molding and encapsulation of the resin layer, includes a material layer that can be implemented, and a layer ^ is provided on the bottom surface of the sealing resin layer, and it is provided with a lead frame for compression bonding. Envelope = item 1 or item 2 of the stable package ^ Among them, the method of molding and encapsulating the resin layer includes 4) Dispensing method (D ispe) and model plastic) 0 range item 2 or Chu 0 M method, Among them, the fineness of the stable package described in item 3, the method of coating and bonding the material layer includes 4 Creen) and Dispe method.
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