TWI245413B - Method for eliminating inverse narrow width effects in the fabrication of dram device - Google Patents

Abstract

The present invention provides a method for eliminating inverse narrow width effects in the fabrication of DRAM devices. A semiconductor substrate is provided having thereon a shallow trench. The shallow trench surrounds an active area. A non-doped silicate glass (NSG) layer is deposited to fill the shallow trench, and is then etched back to a depth of the shallow trench, thereby exposing a portion of the semiconductor substrate at an upper portion of the shallow trench. A doped dielectric layer is deposited over the remaining NSG layer to cover the exposed semiconductor substrate. A thermal process is then carried out to diffuse dopants of the doped dielectric layer out to the semiconductor substrate, thereby forming a doped region at the periphery of the active area.

Description

1245413-Case No. 92115612_year ^ _Θ_Amendment ____ ^ V. Description of the Invention (1) Field of the Invention The present invention relates to a semiconductor process, especially a dynamic random access memory (Dynamic Random Access Memory). (Referred to as DR AM) components, which can avoid the inverse narrow width effects of transistors. Prior art

With the development of various electronic products toward miniaturization, the design of dram components must also meet the requirements of high accumulation and high density. The trench capacitor DRAM device structure is one of the high-density dram structures widely used in the industry. The deep trench is carved in the semiconductor substrate and a trench capacitor is made in it, so the size of the memory cell can be effectively reduced and the chip space can be properly used. Please refer to FIG. 1 and FIG. 2, wherein FIG. 1 is a schematic diagram of the layout of the conventional trench capacitor dram unit 1, and FIG. 2 is a cross-sectional side view along the tangent line AA in FIG. 1. As shown in FIG. 1, the trench capacitor DRAM cell 1 includes a switching transistor 2, which is disposed on an active area (Acti ve Area, AA) 10, and is electrically connected to the switching transistor 2. Connected trench capacitor structure 3. The active region 10, such as a p-type silicon substrate, is isolated by a trench isolation (STI) region 20. The switching transistor 2 includes a polycrystalline silicon gate (Gate 12), an N-type doped source 110, and an N-type doped drain 102. The N-type doped source

1245413---_-Years Revision ^ V. Description of the invention (2) ~~~~~ 1, 〇1 and-and N-type doped drain 102 define a channel region 103 (as in the slanted region) , Which has a channel length L and a channel width w. The N-type doped source 1 of the switching transistor 2 is electrically connected to a bit line (not shown) through a contact hole 18, and the N-type doped drain i 02 of the switching transistor 2 is connected to The trench ^ capacitor structure 3 is electrically connected to a storage electrode (not shown) below. As shown in Figure 2 & 'there is still a gate layer 13 between the polycrystalline stone gate 12 and the active region 10. Because of the need for miniaturization of DRAM elements, the channel length L and channel width w of the above-mentioned trench capacitor DRAM unit 1 are now almost reduced to a size close to the nanometer level. As those skilled in the art know, the shortening of the length L and the head length L will cause a short channel effect. In this regard, many studies have proposed solutions for the short channel effect. However, for channel ditch caused by simultaneous reduction of channel width W = STI corner effect, or the so-called inverse narrow width effects, and the decrease in threshold voltage 'Vt' Secondly, the phenomenon of ° voltage leakage and sub-threshold voltage leakage is less man-made. These problems will seriously affect the performance when the device is close to the nanometer and meter level, and will become a bottleneck for further miniaturization of DRAM devices. SUMMARY OF THE INVENTION Accordingly, the main object of the present invention is to provide a method for solving the above problems. 1245413 May number 92115612, description of the invention (3) The year-month correction state becomes a bottom with half; the shallow bottom is formed; the dielectric bottom is formed; the first-line storage conductor pad passes through the at least the trench This layer, and the above-mentioned object, a method substrate for taking a memory element, has a layer, and the opening of the liner is engraved with a first conductive type and a shallow trench, preferably the same, and fills one of the predetermined depths. The dielectric layer is sacrificed and the dielectric layer is diffused by a diffuser to a semiconducting-conductive type doped region. The layer has a semiconducting timed shallow groove. The layer is covered with a process body and at least the body is defined. Deposit the shallow layer, and add the bottom and bottom to the trench. In the example, the following is included: exposed at the mouth to the non-doped part in the moving area, first exposed in the electrical layer, the active exposure. A series of steps semiconductor out of the semi-semiconductor deposition of the semi-conducting conductive half of the semi-conducting conductivity type region to provide a base-shaped conductor-based substrate without a doped layer to the bulk of the ion A conductive edge of the body is formed in order to allow your review committee to compete with each other. For the content, please refer to the characteristics of "Ming." However, the drawings are for reference only and ^ = detailed description and the present invention are limited. ° For the month and month, it is not for implementation. Refer to Figure 3 to Figure 8. The embodiment of Figure 3 is used to make trench capacitor DRAM cells: Zf is the same or similar element or area in accordance with the present invention. Schematic diagram of the cross section of the κ method, with a ~ using the same number. First, 1245413 _ case number 92115612_ year month __ "" No. 5. Description of the invention (4) As shown in Figure 3, a P-type semiconductor substrate is provided. At 100, a plurality of trench capacitor structures (not shown) have been completed thereon. The semiconductor substrate 100 has a pad oxide layer 41 and a pad nitride layer 42 on its surface. Then using yellow light and etching processes, using hafnium oxide layer 41 and a silicon nitride layer 42 as an etching mask, a plurality of trenches 30 'are etched on the surface of the semiconductor substrate 100 at the same time, and the active area is defined as shown in Figure 4. As shown, a non-doped silica glass (NSG) layer 52 is deposited on the semiconductor substrate 100 and fills the trenches 30. The NSG layer 52 can be fabricated in a conventional manner, such as a chemical vapor deposition (CVD) process. What needs to be pronounced is that the NSG layer 52 can also be made of other materials that are between the silicon nitride layer 42 and the substrate. ^ As shown in Figure 5, the NS ^ 52 of a predetermined thickness is then etched back to form a recessed notch 54 to expose the silicon-based active region 10 at the corner 30 of the trench 60. As shown in Figure 6, a boron-doped material layer 62, such as borosilicate glass (boro_siHcate-gUss, BSG), is deposited on the semiconductor substrate 100,

The boron-doped material layer 62 is in contact with the silicon substrate blue region 10 at the corner 30 of the trench. Diffuser ions in the material layer 62 are diffused outward by 1 groove = part

Page 10 1245413 Case No. 92115612 1 __ ^ Month day __ Amendment i. Description of the invention (5) The bottom active region 10, forming a P-type doped region 7 0, makes the p-type doped region 70 0 rotten A boron concentration greater than 10 in the active region. As shown in FIG. 8 ', the doped material layer 62 and the NSG layer 52 are then removed using a money-etching solution, such as a buffered oxide etcher (BOE). The next steps include the filling of the STI dielectric layer. The STI dielectric layer is chemically and mechanically polished, the pad oxide layer 41 and the pad nitride nitride layer 42 are removed, and the gate or word line is defined. The final result is shown in Figure 9 As shown, that is, a structure having a P-type doped region 70 at the corners of both sides adjacent to ST I in the width direction of the gate channel is completed.

Compared with the prior art, the present invention addresses the trench insulation corner effect (STI corner effect), or the so-called inverse narrow width effects and threshold voltage, caused by the simultaneous reduction of the channel width W. The phenomenon of sub-threshold voltage leakage caused by the drop in Vt) can be solved by using a transistor structure with a p-type doped region 70 at the corners of the gate channel width direction on both sides adjacent to ST I. Of it. The above advantages have shown that the present invention fully complies with the statutory requirements of industrial availability, novelty, and progress as stipulated by the Patent Law. The application was made in accordance with the Patent Law. Please check and approve the patent in this case. The above description is only a preferred embodiment of the present invention, and any equivalent changes and modifications made in accordance with the scope of the patent application of the present invention shall fall within the scope of the patent of the present invention.

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1245413 _Case No. 92115612_ Year Month Amendment __ Brief Description of Drawings, Simple Description of Drawings Figure 1 is a schematic diagram of the layout of a conventional trench capacitor DRAM cell. FIG. 2 is a cross-sectional side view taken along line A A ′ in FIG. 1. 3 to 9 are schematic cross-sectional views of a method for fabricating a trench capacitor DRAM device according to a preferred embodiment of the present invention. (Symbol description

1 trench capacitor DRAM unit 2 switching transistor 3 trench capacitor structure 10 active area 12 polycrystalline gate 13 gate insulation layer 18 contact hole 20 trench insulation area 30 trench 41 pad oxide layer 42 nitride layer 52 NSG layer 54 Depression notch 60 Trench corner 62 Doped material layer 70 P-type doped region 100 P-type semiconductor substrate 101 N-type doped source 102 N-type doped electrode 103 Channel region

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Claims (1)

1245413 Case No. 92115612 6. Application Patent Scope1. A method for making a dynamic random access memory device includes the following steps: 1. Providing half of the semiconductive opening to expose at least one shallow deposit through the opening; The degree is engraved as soon as no money is returned, thereby being exposed to the un-doped dielectric layer and the bottom; and the conductor substrate body-shaped semiconductor substrate etches the half-trench, and at the same time doping sacrifices does not change the impurity sacrificing part of the impurity sacrificing A layer of dielectric layer has a lining substrate; a conductive substrate defines a layer, and a layer is filled, and a stack of the shallow trench is deposited on the semiconductor substrate for a diffusion process, and the conductive substrate is diffused to the semi-conductive type dopant. Doped with the dielectric to the first conductivity type; layer, the pad layer has at least one, so that the active area in the semiconductor substrate is filled with the shallow trench; i a predetermined taste bottom in the shallow trench; doped The first conductive ions in the semiconductor base layer exposed among the first conductive ions are formed around the active area of the first conductive ions. A second area is opened. Ί Patent Patent Park Item 1 Production of said dynamic random access memory of: a semiconductor substrate having a conductivity type - the first and second doped regions heteroaryl ^ = disabilities have - a second doping concentration, and a brother through doping concentration greater than the first doping concentration. 3. The method of making 70 pieces as described in item 1 of the scope of patent application, wherein the first conductivity type is p-type sad random access memory Page 13 1245413 --- tS_92H56 ^ _ year, month, day, amendment 6 、 Scope of patent application / 4 · —The method for making a dynamic random access memory device as described in item 1 of the scope of patent application, wherein the liner layer contains There is a pad of oxide layer and a pad of silicon nitride layer. 5. The method for manufacturing a dynamic random access memory device as described in item 1 of the scope of the patent application, wherein the undoped sacrificial layer is a non-doped Si 1 icate Glass (NSG). Floor.乂 6. The method for making a dynamic random access memory element as described in the first item of the application scope, wherein the first conductive ion-doped system is boro-siiicate-glass (BSG) )Floor. Day 7 · Making private power as described in item 1 of the scope of patent application _ Bing Touch-a method of making random access memory elements from the horrible corpse of the Seven Soil Gan Shi, where the method is forming the The first step further includes the following steps: removing the dielectric layer; and removing the undoped sacrificial layer.