TWI244179B - Package structure of stacking devices with shielding and fabrication thereof - Google Patents

Package structure of stacking devices with shielding and fabrication thereof Download PDF

Info

Publication number
TWI244179B
TWI244179B TW093135582A TW93135582A TWI244179B TW I244179 B TWI244179 B TW I244179B TW 093135582 A TW093135582 A TW 093135582A TW 93135582 A TW93135582 A TW 93135582A TW I244179 B TWI244179 B TW I244179B
Authority
TW
Taiwan
Prior art keywords
conductive
semiconductor element
item
stacked package
scope
Prior art date
Application number
TW093135582A
Other languages
Chinese (zh)
Other versions
TW200618216A (en
Inventor
Jau-Shoung Chen
Hsiang-Chi Yeh
Chia-Chieh Hu
Original Assignee
Advanced Semiconductor Eng
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Advanced Semiconductor Eng filed Critical Advanced Semiconductor Eng
Priority to TW093135582A priority Critical patent/TWI244179B/en
Application granted granted Critical
Publication of TWI244179B publication Critical patent/TWI244179B/en
Publication of TW200618216A publication Critical patent/TW200618216A/en

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32135—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/32145—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors

Landscapes

  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)

Abstract

A package structure of stacking devices and the fabrication thereof are provided. A substrate includes a ground layer at least. One of two semiconductor devices is affixed to the substrate. There is shielding structure is interlaid between the two semiconductors and electrically connects the ground layer.

Description

^44179 九、發明說明： 【發明所屬之技術領域】 本發明係有關一種玱晶 的堆疊封裝結構。 $ $裝、，吉構，特別是一種具有屏蔽 【先前技術】 隨著電子難技_進步，麵愈多的電子元件被設計於一封裝 2叫到元件體積縮小化的目的。因此，若干元件以堆疊的方式 排列於封裝結射是解決體積辭段之—。 然而’對於高頻元件，例如軌元件而言，彼此之間會有干 擾的問題，因此於安排高頻元件喷_屏蔽設計來避免元件之間的 干擾。屏蔽設計-般最簡單的方式係期麵賊效應來達到阻絕電 磁干擾的問題。但是’對於目前的封裝製作來看，無法利用金屬屏蔽 效應來設計屏蔽伽，因此目前高頻元件_裝並不_堆叠的方袭 形式。 基於封裝結構縮小化與降低成本的寺量，堆叠的封裝結構仍_ 頻元件封裝必須發制方向之—。因此，如何讀低的成本將屏2 用設計於堆疊封裝結射是現今堆4縣技術努力的方向之— 1244179 【發明内容】 欲避免元件之間的干擾問題，於此 其形成方法，利用導電膠與連接導 有鑑於上述背景中， 提供一種堆疊封裝結構與 線介於堆疊元件之間。 封裝體積與成本，於itl ^種堆㈣裝結構與其形成方法，利科«與低以 缚形空白晶片可以提供導通與降低封裝體積的特點。 根據上述之目的，本發明之—實施例，提供一種堆疊全 裝結構與方法’提供-基板，其至少有—地線術。undlayel 於其中。兩半導體元件，其—被黏著固定於基板上，兩者之 間則存在-屏蔽結構(shielding咖伽代)並且與基板的地 線層有電性上的連I其中屏蔽結構至少由導電膠與導電錄 所組成。 【實施方式】 本發明之實施例用示意圖詳細描述如下，在詳述本發明之實施例 時，表示晶圓表面的部份會放大顯示並說明，然不應以此作為有限定 的認知。此外，在實際的晶圓表面與方法_，可以包含此結構令其他 必要的部分。 其次，當本發明之實施例圖式中的各元件或結構以單一元件或 1244179 結構描述制時’他x此作騎限定的認知，.下之說明未特別 強調數目上的限料’本發明之精神與細範财推及多數 結構並存的結構與方法上。 或 第-圖為本發明的-實施例所應用之―封裳元件的立體示意圖。 於本實施例中，高頻IC(圖上未示），例如低功耗無線電收發器的特殊 應用 IC(Application Specific Integrated Circuit ; ASIC)，以四邊扁平無 接腳(Quad Flat No Lead，QFN)封裝方式封裝成為一半導體元件5，其 具有若干周圍末端接墊分布於半導體元件5 的四周邊緣與一暴露出的晶粒接塾16(exp〇sed die pad)位於半導體元件 5之表面中央範圍。然本發明之實施例並不限於此種封裝元件，其他 的封裝形式，例如岸面柵格陣列(Land LGA)元件或晶粒 (die)，亦可應用於本發明之精神。 第一 A至第二E圖為根據本發明之一實施例之堆疊封裝結構的剖 面示意圖。參照第二A圖，一基板10之表面10a上分布若干導電接 墊12與一黏著層14，半導體元件5固定於黏著層14上。再者，一導 電結構20連接每一周圍末端接墊18與鄰近的一導電接墊12。於一實 施例中’基板10為一具有線路層或電源層(p0wer layei·)與地線層(获〇1111(1 layer)的一多層板(圖上未示）。導電接塾12，例如銅接墊或金接塾，以 適當的方法，例如電鍍的方式，形成於基板10之外層上。其中至少 一導電接墊12連接至基板1〇中的地線層。黏著層14，例如一絕緣環 1244179 氣黏著層，用轉半導體元件5固定於表面10a上。導電結構2〇，例 如以打線方式形成的金線，負t半導體元件5與基板ig之間的電性 連接。 參照第二B圖，依序放置一導電膠22(c〇nductive叫叫與一薄 型晶片24(mirror chip)於半導體元件5之晶粒接墊i6上。於一實 施例中’導電膠22，例如-導電銀膠，包含顆粒細小的導電粒子， 例如銀/銀飽合金分布於其中，具有導電與黏著的功用。 薄型晶片24， 例如-空白無線路或元件的晶片，可以—般方式薄形化至⑽微米厚 度’具有承載的功能。本發明之精神，利用導電膠22與薄型晶片料 取代-般的金屬# ’形錢續的賤結構，_達到堆疊結構薄型化 的優點。 參照第二c圖，另-導電結構26通過薄型晶片24之上方，兩 端與表面IGa上之兩接轉i2a ；}：目連接。於—實施例中，導電結構 26 ’例如一金線’利用打線的方式固定於接地墊12&上，接地墊12& 係與基板10中的地線層(圖上未示)有電性上的連接。 參照第二D圖，另一導電膠28形成於薄型晶片24上且將導電 結構26 E]定於導電膠28巾，並且另一半導體元件3〇固定於導電膠 28上。於-實施例中’導電膠28與導電膠22的功能相同，具有導 電與黏著的功能，因此導電膠28的材料可與導電膠22相同或類似。 1244179 僅連接一接地墊12a，導電結構26之另一端則埋入導電膠28中， 如此仍可達到金屬屏蔽的效應。可以理解的，導電結構26亦可固定 於導電膠22中。 根據上述，本發明之一實施例提供一種具有屏蔽結構的堆疊 封裝結構與其製作方法。提供一基板，其上具有至少一接地 墊。一第一半導體元件固定於基板上，一第二半導體元件則 位於第一半導體元件上。一導電膠結構固定並黏著於第一半 導體7L件與第二半導體元件之間。一第一導電結構固定於導 電膠結構中並且與接地墊有電性上的連接。一空白晶片固定 於導電膠結構中並且位於第一半導體元件與第二半導體元件 之間。 以上所述之實施例僅係為說明本發明之技術思想及特點，其目的 在使熟習此項技藝之人士能夠瞭解本發明之内容並據以實施，當不能 、之限疋本發明之專利範圍，即大凡依本發明所揭示之精神所作之均 等變化或修飾，仍應涵蓋在本發明之專利範圍内。 【圖式簡單說明】 第圖為本發明的-實施例所應用之一封裝元件的立體示意圖。 第-A至第二E_根據本發明之—實補之堆疊封裝結構的剖面八 意圖。 〇不 1244179 第三圖為本發明之另一實施例，說明另一屏蔽結構的剖面示意圖。 【主要元件符號說明】 5 半導體元件 10 基板 10a,b 表面 12 導電接墊 12a接地墊 14 黏著層 16 晶粒接塾 18 周圍末端接墊 20 導電結構 22 導電膠 24 薄型晶片 26 導電結構 28 導電膠 30 半導體元件 32 導電接墊 34 導電結構 36 封膠結構 38 導電球 12^ 44179 IX. Description of the invention: [Technical field to which the invention belongs] The present invention relates to a stacked package structure of crystal. $ $ Package, Gigabyte, especially one with shielding [Previous technology] With the advancement of electronic technology, more and more electronic components are designed in a package 2 to reduce the volume of components. Therefore, arranging several components in the package in a stacked manner is one of the solution volume phrases. However, for high-frequency components, such as rail components, there is a problem of interference with each other. Therefore, a high-frequency component spray-shield design is arranged to avoid interference between components. Shield design-the simplest way is to prevent the electromagnetic interference by using the surface thief effect. However, for the current package production, the shielding effect cannot be designed by using the metal shielding effect. Therefore, the current high-frequency components are not mounted in a stacked form. Based on the shrinking of the packaging structure and the reduction of cost, the stacked packaging structure is still in the direction of frequency component packaging. Therefore, how to read the low cost to use the screen 2 in a stacked package design is the direction of the current four-county technical efforts — 1244179 [Summary of the Invention] To avoid the problem of interference between components, the formation method here uses conductive In view of the above background, a glue and a connection guide provide a stacked package structure and a wire interposed between the stacked elements. Packaging volume and cost, in terms of itl stack mounting structure and its forming method, Ricoh «and low-blank blank chip can provide the characteristics of conduction and reduce packaging volume. According to the above-mentioned object, an embodiment of the present invention provides a stacked full structure and method'providing-substrate, which at least has -grounding. undlayel in it. Two semiconductor components, which are adhered and fixed on the substrate, are in between-a shielding structure (shielding) and are electrically connected to the ground layer of the substrate. The shielding structure is at least made of conductive adhesive and Composed of conductive records. [Embodiment] The embodiment of the present invention is described in detail with a schematic diagram as follows. When the embodiment of the present invention is described in detail, the part showing the surface of the wafer will be enlarged and explained, but it should not be used as a limited recognition. In addition, the actual wafer surface and method can include other necessary parts of this structure. Secondly, when each element or structure in the embodiment of the present invention is described by a single element or a 1244179 structure description, 'he x this is a limited cognition, the following description does not particularly emphasize the number of material restrictions' The spirit and fine Fancai push on the structure and method that coexist with most structures. Or Figure-is a schematic perspective view of a Fengshang element applied to an embodiment of the present invention. In this embodiment, a high-frequency IC (not shown in the figure), such as an Application Specific Integrated Circuit (ASIC) for a low-power radio transceiver, has a quad flat no lead (QFN). The package is packaged into a semiconductor device 5, which has a plurality of peripheral end pads distributed on the peripheral edges of the semiconductor device 5 and an exposed die pad 16 located at the center of the surface of the semiconductor device 5. However, the embodiment of the present invention is not limited to such a packaged component, and other packaging forms, such as a land grid array (Land LGA) element or a die, can also be applied to the spirit of the present invention. The first A to the second E are schematic cross-sectional views of a stacked package structure according to an embodiment of the present invention. Referring to FIG. 2A, a plurality of conductive pads 12 and an adhesive layer 14 are distributed on the surface 10a of a substrate 10, and the semiconductor element 5 is fixed on the adhesive layer 14. Furthermore, a conductive structure 20 connects each peripheral end pad 18 to an adjacent conductive pad 12. In one embodiment, the 'substrate 10 is a multilayer board (not shown in the figure) with a circuit layer or a power layer (p0wer layei) and a ground layer (not shown). The conductive connection 12, For example, copper pads or gold pads are formed on the outer layer of the substrate 10 by a suitable method, such as electroplating. At least one conductive pad 12 is connected to the ground layer in the substrate 10. The adhesive layer 14, such as An insulating ring 1244179 is a gas-adhesive layer, and is fixed on the surface 10a by the semiconductor element 5. The conductive structure 20, for example, a gold wire formed by wire bonding, is electrically connected between the semiconductor element 5 and the substrate ig. In Figure 2B, a conductive adhesive 22 (conductor called and a thin chip 24 (mirror chip) is placed on the die pad i6 of the semiconductor element 5. In one embodiment, the conductive adhesive 22, for example- Conductive silver glue contains small conductive particles, such as silver / silver-saturated alloys, which have the function of conductivity and adhesion. Thin wafers 24, such as wafers for blank wireless circuits or components, can be thinned to ⑽Micron thickness' has the function of carrying. This In the spirit of the invention, the conductive glue 22 and the thin wafer material are used instead of the metal-like base structure to achieve the advantages of thinning the stacked structure. Referring to the second figure c, the conductive structure 26 passes the thin wafer 24 Above, the two ends are connected to the two on the surface IGa, i2a;}: mesh connection. In the embodiment, the conductive structure 26, such as a gold wire, is fixed to the ground pad 12 & It is electrically connected to the ground layer (not shown) in the substrate 10. Referring to the second diagram D, another conductive adhesive 28 is formed on the thin wafer 24 and the conductive structure 26 E] is determined to be conductive. Adhesive 28, and another semiconductor element 30 is fixed on the conductive adhesive 28. In the embodiment, 'the conductive adhesive 28 has the same function as the conductive adhesive 22, and has the function of conducting and adhering, so the material of the conductive adhesive 28 can be combined with The conductive adhesive 22 is the same or similar. 1244179 is only connected to a ground pad 12a, and the other end of the conductive structure 26 is buried in the conductive adhesive 28, so that the effect of metal shielding can still be achieved. It can be understood that the conductive structure 26 can also be fixed to the conductive胶 22。 According to the above An embodiment of the present invention provides a stacked package structure with a shielding structure and a manufacturing method thereof. A substrate is provided with at least one ground pad thereon. A first semiconductor element is fixed on the substrate, and a second semiconductor element is located on the first On the semiconductor element, a conductive adhesive structure is fixed and adhered between the first semiconductor 7L and the second semiconductor element. A first conductive structure is fixed in the conductive adhesive structure and is electrically connected to the ground pad. A blank chip It is fixed in the conductive adhesive structure and located between the first semiconductor element and the second semiconductor element. The embodiments described above are only for explaining the technical idea and characteristics of the present invention, and the purpose is to enable those skilled in the art to understand The content of the present invention is also implemented according to it. When it is impossible, the scope of the patent of the present invention, that is, all equal changes or modifications made according to the spirit disclosed by the present invention, should still be covered by the patent scope of the present invention. [Brief description of the drawings] FIG. 1 is a schematic perspective view of a package component applied to an embodiment of the present invention. Sections -A to E_ According to the present invention-the cross-section of the stacked package structure according to the present invention. 〇 不 1244179 The third figure is another schematic view of another embodiment of the present invention, illustrating a schematic cross-sectional view of another shielding structure. [Symbol description of main components] 5 Semiconductor element 10 Substrate 10a, b Surface 12 Conductive pad 12a Ground pad 14 Adhesive layer 16 Die pad 18 Surrounding pad 20 Conductive structure 22 Conductive glue 24 Thin wafer 26 Conductive structure 28 Conductive glue 30 Semiconductor element 32 Conductive pad 34 Conductive structure 36 Seal structure 38 Conductive ball 12

Claims (1)

1244179 十、申請專利範圍： i一種堆疊封裝結構，包含： 一基板與至少一地線層（ground layer)於該基板之中； 一第一半導體元件固定於該基板上； 一屏蔽結構(shielding structure)固定於該第一半導體 凡件上並且與該地線層有電性上的連接；及 一第二半導體元件固定於該屏蔽結構上。 2·如申請專利範圍第1項所述之堆疊封裝結構，其中該屏蔽 結構包含·· 一導電膠結構黏著該苐一半導體元件與該第二半導體元 一導電結構岐於該導電膠結構中並且與該地線層有 性上的連接；及1244179 10. Scope of patent application: i. A stacked package structure comprising: a substrate and at least one ground layer in the substrate; a first semiconductor element fixed on the substrate; a shielding structure ) Is fixed on the first semiconductor element and is electrically connected to the ground layer; and a second semiconductor element is fixed on the shielding structure. 2. The stacked package structure described in item 1 of the scope of the patent application, wherein the shielding structure includes a conductive adhesive structure that adheres the first semiconductor element and the second semiconductor element to a conductive structure that is in the conductive adhesive structure and Sexually connected to the ground plane; and 元件與該第二半導體元件之間。Between the element and the second semiconductor element. 一半導體元件與該第二半導體元件。 •半裒結構，其中該導電 第二導電銀膠分別鄰近該第 13 1244179 4·如申請專鄉㈣3項所述之堆疊封裝結構，其_該空白 曰曰片介於該第一導電銀膠與該第二導電銀膠。 5·如申請專利範圍第2項所述之堆疊封裝結構，其中該導電 結構包含一金線。 6·如申請專利範圍帛！項所述之堆疊封裝結構，其中該基板 之一表面上具有至少一接地墊與該地線層有電性上的連接。 •如申明專利範圍第6項所述之堆疊封裝結構，其中該屏蔽 結構包含： —導電膠結構黏著該第一半導體元件與該第二半導體元 件； 一第-導電結構固定於該導電膠結構中並且經由該接地 墊與該地線層有電性上的連接；及 -空白晶片固定於該導電膠結構中並介於該第一半導體鲁 元件與該第二半導體元件之間。 8·如申請專利範圍第7項所述之堆疊封裝結構，其巾該導電 膠結構包含-第-導電銀膠與―第二導電銀膠分別鄰近該第 -半導體元件與該第二半導體元件’並且該空白晶片位於該 第一導電銀膠與該第二導電銀膠之間。 1244179 9·如申請專利範圍第7項所述之堆疊封裝結構，其中該第— V電結構包含一金線。 10.如申請專利編7項所述之堆疊封裳結構，其中該表 面更包含-導電連接塾電性連接至該基板中。 11.如申請專利範圍帛1G項所述之堆疊封裝結構，更包含 第-導電結構電性連接該導電連接塾與該第—半導體元件。 =如申請專利範㈣1G項所述之堆疊封裝結構，更包含一 第-導電結構電性連接該導電連接_該第二半導體元件。 如申請專利範㈣i項所述之堆疊封裝結構，其中該第 一半導體元件無第二半導體元件核—包含-封裝元 π靖寻利範圍第 $尸/1述之堆疊封裝結構，其令該 裝疋件具—接地結構並與該第-導電結構電性連接 ’其中該第 粒(die)。 15·如申請專㈣㈣i項所叙堆疊封裝結構 一半導體元件與該第二半導體元件之任—包含一 E 16·如中請專利範圍第！項所述之堆疊封裝結構，更 絕緣黏著層位於該第_半導體元件與《板之間。 15 1244179 17·如申請專利範圍第1項所述之堆疊封裝結構，更包含一 封膠材料覆蓋該基板、該第—半導體元件、該屏蔽結構及該 第一半導體元件上。 18.如申請專利範圍第17項所述之堆疊封裝結構，更包含複 數個導電球分布於該基板上並暴露於該封膠材料外。 it 一種具有屏蔽結構的堆疊封裝結構，包含： 基板與至少一接地墊(gr〇Und pad)於該基板之一第一 表面； 一第一半導體元件固定於該苐一表面上； 一第二半導體元件位於該第一半導體元件上； 一導電膠結構ϋ定並介於該第—半導體元件與該第二半 導體元件之間； 一第一導電結_定於該導電膠結構中並且與該接地塾 有電性上的連接；及 一空白晶片固定㈣導電膠結構t並且位於該第一半導 體元件與該第二半導體元件之間。 16 1244179 專利範圍第.19項所述之具有屏蔽結構的堆叠封裝 I、中_-半導體元件與該第二半導體元件之任— s —封裝元件。 匕 21·如申請專利範圍第2〇項所述之 裝处槿百屏敝、纟。構的堆疊封 裝、，，。構’其中该封裝元件具一接地結構並與該 電性連接。 “構 士如中請專·圍第19項所叙具有屏㈣構的堆疊封 裝、“籌，其中該第一半導體元件與該第二半導體元件之任— 包含一晶粒(die)。 23. 如申請專利範圍第19項所述之具有屏蔽結構的堆叠封 裝結構’其中該導電膠結構包含一第一導電銀膠與—第：導 電銀膠分別鄰近該第—半導體元件與該第二半導體元件y: 且该空白晶片位於該第—導電銀膠與該第二導電銀膠之間。： 24. 如巾請專利範圍帛19項所述之具有屏蔽結構的堆叠封 裴結構，其中該第一導電結構包含一金線。 且 25. 如巾請專利範圍帛19項所述之具有屏蔽結構的堆叠封 裝、’°構，更包含一第二導電結構電性連接該第—表面之 電連接墊與該第一半導體元件。 導 17 a^44179 請專·_19賴狀具有减結構的堆疊封 衣、、、〇構，更句合一坌一 第一導電結構電性連接該第一表 電連接塾與該第二半導體元件。 之ν 如巾4專㈣圍第19項所述之具有屏蔽結構的堆疊封 二°構’更包含—絕緣黏著層位於該第-半導體元件與該第 一表面之間。 28社如巾請專利範圍第19項所述之具有屏蔽結構的堆疊封 、、°構’更包含—封膠材料覆蓋該基板、該S —半導體元件、 遠導電膠結構、該第―導電結構、該空白晶片及該第二半導 體元件上。 29·如申請專利範圍第28項所述之具有屏蔽結構的堆疊封 裝結構，更包含複數個導電球分布於該基板上並暴露於該封 膠材料外。 3〇·如申請專利範圍第19項所述之具有屏蔽結構的堆疊封 装結構’更包含複數個導電球分布於該基板之一第二表面上。 31·一種形成具有屏蔽之堆疊封裝結構的方法，包含： 提供一基板與至少一地線層於該基板之中； 18 1244179 固定—第—半導體元件於該基板之-表面上； 形成-屏蔽結構於該第—半導體科上並且電性連接至 該地線層，·及 固疋-苐二半導體元件於該屏蔽結構上。 32.如中請專利範圍第31項所述之形成具有屏蔽之堆疊封 裝結構的方法，其中形成該屏蔽結構之步驟包含·· 形成-第-導膠於該第_半導體元件上； 放置空白晶片於該第一導電銀膠上； 放置一導電線於該空白晶片 乂成第一導電銀膠於該空 上並連接至該地線層；及 白晶片上並固定該導電線。 ㈣的:Γ:Γ31項所述之形成軸 法，八中形成該屏蔽結構之步驟包含·· I成-第-導電銀膝於該第_半導體元件上； 連接一導電線至第-導電銀膠與該地線層； 置1白晶片於該第一導電銀膠上；及 圯成-第二導電銀膠於該空白晶片上。 34·如申請專利範圍第33 默結構的方、‘ # "形成具有屏蔽之堆疊封 毒的方法，其中於形成該第，轉於該第—半導體 19 1244179 元件上之步驟後，且於連接該導電線至該第—導電銀膠料 地線層之步驟前，更包含固化該第—導電銀膠。 x 35·如申請專利範圍帛3ι項所述之形 ::結構的方法’更包含覆蓋-封膠材料覆蓋該基:之= +導體科、該屏蔽結構及該第二铸體元件上。 裝結構的 面 Γ,.·,如巾請專利範圍第31項所述之形成具有屏蔽之堆叠封 方法，更包含形成複數個導電球於該基板之另一表 請專利範圍第31項所述之形成具有屏蔽之堆 ::的方法’更包含形成一導電結構電性連接該 奴π件與該基板。 千導 m中請專利範圍第31項所述之㈣Μ屏蔽之_ 裝、.。構的方法，更包含形成一導電 體元件與該基板。 以顧Μ二半導 31項所述之形成 裝-構的方法’其巾固定該[切ς封 ㈣之任-步驟包含提供—封裝元件。…第—+導體 1244179 40.如申請專利範圍第31項所述之形成具有屏蔽之堆疊封裝結構的方 法，其中固定該第一半導體元件與該第二半導體元件之任一步驟包含 提供一晶粒。A semiconductor element and the second semiconductor element. • Semi-condensed structure, in which the conductive second conductive silver glue is adjacent to the 13th 1244179, respectively. 4 · The stacked package structure described in the application No. 3 item, where the blank sheet is between the first conductive silver glue and The second conductive silver paste. 5. The stacked package structure described in item 2 of the scope of patent application, wherein the conductive structure includes a gold wire. 6 · If the scope of patent application is 帛! The stacked package structure described in the item, wherein at least one ground pad on one surface of the substrate is electrically connected to the ground layer. • The stacked package structure described in claim 6 of the patent scope, wherein the shielding structure includes:-a conductive adhesive structure adhering the first semiconductor element and the second semiconductor element;-a first conductive structure fixed in the conductive adhesive structure And is electrically connected to the ground layer through the ground pad; and-a blank chip is fixed in the conductive adhesive structure and interposed between the first semiconductor element and the second semiconductor element. 8. The stacked package structure described in item 7 of the scope of the patent application, wherein the conductive adhesive structure includes a first conductive silver adhesive and a second conductive silver adhesive adjacent to the first semiconductor component and the second semiconductor component, respectively. And the blank wafer is located between the first conductive silver glue and the second conductive silver glue. 1244179 9. The stacked package structure described in item 7 of the scope of patent application, wherein the -V electrical structure includes a gold wire. 10. The stacked seal structure according to item 7 of the patent application, wherein the surface further comprises a conductive connection and an electrical connection to the substrate. 11. The stacked package structure described in the scope of application patent (1G), further comprising a first-conductive structure electrically connecting the conductive connection and the first semiconductor element. = The stacked package structure described in item 1G of the patent application, further comprising a first-conductive structure electrically connecting the conductive connection_the second semiconductor element. The stacked package structure described in the patent application item ㈣i, wherein the first semiconductor element does not have a second semiconductor element core—including the packaged package structure described in the package element π. The component has a ground structure and is electrically connected to the first conductive structure, where the first die is. 15 · Stacked package structure described in item i of the application—a semiconductor device and the second semiconductor device—including an E 16 · Please refer to the patent scope! In the stacked package structure described in the item, the insulating adhesive layer is located between the semiconductor device and the board. 15 1244179 17. The stacked package structure described in item 1 of the scope of patent application, further comprising a sealing material covering the substrate, the first semiconductor element, the shielding structure, and the first semiconductor element. 18. The stacked package structure described in item 17 of the scope of patent application, further comprising a plurality of conductive balls distributed on the substrate and exposed to the sealing material. it A stacked package structure with a shielding structure, comprising: a substrate and at least one ground pad on a first surface of the substrate; a first semiconductor element fixed on the first surface; a second semiconductor The element is located on the first semiconductor element; a conductive glue structure is defined and interposed between the first semiconductor element and the second semiconductor element; a first conductive junction is determined in the conductive glue structure and connected to the ground; There is an electrical connection; and a blank chip fixes the conductive adhesive structure t and is located between the first semiconductor element and the second semiconductor element. 16 1244179 A stacked package with a shielding structure described in item No. .19 of the patent scope. Any of the middle semiconductor component and the second semiconductor component—s—package component. Dagger 21. As described in item 20 of the scope of the patent application, the place is covered with hibiscus and cymbals. Structured stacking package ,,,,. Structure, wherein the package element has a ground structure and is electrically connected to the package element. "The constructor as described in item 19, a stacked package with a screen structure as described in item 19", wherein any one of the first semiconductor element and the second semiconductor element-includes a die. 23. The stacked package structure with a shield structure according to item 19 of the scope of the patent application, wherein the conductive adhesive structure includes a first conductive silver adhesive and a first conductive silver adhesive adjacent to the first semiconductor element and the second Semiconductor element y: and the blank wafer is located between the first conductive silver paste and the second conductive silver paste. : 24. The stacked seal structure having a shielding structure as described in item 19 of the patent scope, wherein the first conductive structure includes a gold wire. And 25. For example, the stacked package with a shielding structure described in item 19 of the patent application, and a '° structure, further includes a second conductive structure electrically connecting the first surface electrical connection pad and the first semiconductor element. Guide 17 a ^ 44179 Please special. _19 Lai-like stacked jackets with reduced structure, structure, and structure, a combination of a first conductive structure to electrically connect the first watch electrical connection and the second semiconductor element . Ν The stacked package with a shielding structure as described in item 19 of item 4 is further comprised of an insulating adhesive layer between the first semiconductor element and the first surface. For example, the 28 company claims a stacked seal with a shielding structure as described in item 19 of the patent scope. The structure also includes a sealing material covering the substrate, the S-semiconductor element, a remote conductive adhesive structure, and the first conductive structure. , The blank wafer and the second semiconductor element. 29. The stacked package structure with a shielding structure as described in item 28 of the scope of the patent application, further comprising a plurality of conductive balls distributed on the substrate and exposed to the sealing material. 30. The stacked package structure with a shield structure according to item 19 of the scope of the patent application, further comprising a plurality of conductive balls distributed on one of the second surfaces of the substrate. 31. A method of forming a stacked package structure with a shield, comprising: providing a substrate and at least one ground layer in the substrate; 18 1244179 fixing a first semiconductor element on a surface of the substrate; forming a shielding structure It is on the first semiconductor branch and is electrically connected to the ground layer, and the solid-state semiconductor device is on the shielding structure. 32. The method for forming a stacked package structure with a shield as described in item 31 of the Chinese Patent Application, wherein the step of forming the shield structure includes forming a -th-conductive paste on the _th semiconductor element; placing a blank wafer On the first conductive silver glue; placing a conductive wire on the blank wafer to form a first conductive silver glue on the space and connecting to the ground layer; and on the white wafer and fixing the conductive wire. ㈣: Γ: The formation axis method described in Γ31, the steps of forming the shielding structure in the eighth step include: I-th-conductive silver knee on the _ semiconductor component; connecting a conductive wire to the-conductive silver Glue and the ground layer; placing a white wafer on the first conductive silver glue; and forming a second conductive silver glue on the blank wafer. 34. For example, the method of forming the 33rd silent structure in the scope of the patent application, "# " Method of forming a stacking and sealing with a shield, wherein after forming the step, transfer to the step on the-semiconductor 19 1244179 element, and connect Before the step of conducting the conductive wire to the ground layer of the first conductive silver compound, the method further includes curing the first conductive silver compound. x 35. The method of the form :: structure described in the scope of patent application 帛 3ι: further includes covering-sealing material to cover the base: + = conductor, the shielding structure, and the second casting element. The surface of the mounting structure Γ, .., as described in the method of forming a stacked seal with a shield as described in item 31 of the patent, and further includes forming a plurality of conductive balls on the substrate. The method of forming a shielded stack :: further includes forming a conductive structure to electrically connect the slave component to the substrate. In the guide m, please use the MM shield as described in item 31 of the patent scope. The method further includes forming a conductive element and the substrate. According to the method for forming a device described in Item 31 of the second semiconductor, the method of fixing the [cutting, sealing, and enclosing any of the steps-providing-encapsulating the components. … Th— + conductor 1244179 40. The method for forming a stacked package structure with shielding as described in item 31 of the scope of patent application, wherein any step of fixing the first semiconductor element and the second semiconductor element includes providing a die . 21twenty one
TW093135582A 2004-11-19 2004-11-19 Package structure of stacking devices with shielding and fabrication thereof TWI244179B (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
TW093135582A TWI244179B (en) 2004-11-19 2004-11-19 Package structure of stacking devices with shielding and fabrication thereof

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
TW093135582A TWI244179B (en) 2004-11-19 2004-11-19 Package structure of stacking devices with shielding and fabrication thereof

Publications (2)

Publication Number Publication Date
TWI244179B true TWI244179B (en) 2005-11-21
TW200618216A TW200618216A (en) 2006-06-01

Family

ID=37154720

Family Applications (1)

Application Number Title Priority Date Filing Date
TW093135582A TWI244179B (en) 2004-11-19 2004-11-19 Package structure of stacking devices with shielding and fabrication thereof

Country Status (1)

Country Link
TW (1) TWI244179B (en)

Also Published As

Publication number Publication date
TW200618216A (en) 2006-06-01

Similar Documents

Publication Publication Date Title
TW510034B (en) Ball grid array semiconductor package
US11222852B2 (en) Method for fabricating electronic package
TWI282153B (en) Stacked-type semiconductor device
JP4058642B2 (en) Semiconductor device
TWI281236B (en) A package structure with a plurality of chips stacked each other
TW201739031A (en) Electronic package and the manufacture thereof
US10643974B2 (en) Electronic package with conductive pillars
KR20140057979A (en) Semiconductor package and method of manufacturing the semiconductor package
JPH05211275A (en) Semiconductor device and manufacture thereof
TW200913194A (en) Semiconductor package and manufacturing method thereof
TW200532823A (en) Circuit device
TW200908268A (en) Packaging substrate structure with capacitor embedded therein and method for fabricating the same
US7157292B2 (en) Leadframe for a multi-chip package and method for manufacturing the same
TW200822336A (en) Stacked type chip package, chip package and process thereof
US7101733B2 (en) Leadframe with a chip pad for two-sided stacking and method for manufacturing the same
JPS6042620B2 (en) Semiconductor device encapsulation
TW200824067A (en) Stacked chip package structure and fabricating method thereof
US7649746B2 (en) Semiconductor device with inductor
TWI244179B (en) Package structure of stacking devices with shielding and fabrication thereof
TW201208035A (en) Multi-chip stacked assembly with ground connection of EMI shielding
US6437984B1 (en) Thermally enhanced chip scale package
TWI243436B (en) Semiconductor package and fabrication method of the same
JPH08274214A (en) Semiconductor device
TW201214650A (en) Chip package having fully covering shield connected to GND ball
US8410598B2 (en) Semiconductor package and method of manufacturing the same