1244146 九、發明說明： 【發明所屬之技術領域】 本發明係關於一種具有堆疊式晶片封裝單元之封裝 件及其製法，尤指一種對晶片與基板先行封裝形成一已測 。式栅格陣列封裝單元（Land Grid Array，LGA)的具有堆疊式 晶片封裝單元之封裝件及其製法。 【先前技術】 現今電子產品正朝向多功能且輕便之方向發展，以滿 足消費者需求，故而習知的單晶片半導體產品已難符市場# 之趨向；而為實現半導體產品更輕、薄、短、小且兼具多 功能之發展方向’能整合複數個晶片於一體的多晶片模組 (Multi Chip Module，MCM )封裝件顯然已逐漸成為市場 之主流。 例如，美國專利第6,555,9〇2號案係提出一種多晶片 模組封裝件，如第1圖所示，該封裝件1係包括-基板 101、兩堆疊晶片1〇3、105、設置於該兩晶片1〇3、1〇5間 之支撐部107、以及用以包覆該晶片103、105的封裝膠體·1244146 IX. Description of the invention: [Technical field to which the invention belongs] The present invention relates to a package with a stacked chip packaging unit and a method for manufacturing the same, and more particularly, to a method of first packaging a wafer and a substrate to form a measured one. Package with Land Grid Array (LGA) package with stacked chip packaging units and manufacturing method thereof. [Previous technology] Today's electronic products are developing in a multi-functional and lightweight direction to meet consumer needs, so the conventional single-chip semiconductor products have been difficult to meet the trend of the market #; and in order to achieve semiconductor products lighter, thinner, shorter Multi-chip module (Multi Chip Module (MCM)) package capable of integrating multiple chips into one has obviously become the mainstream of the market. For example, U.S. Patent No. 6,555,920 proposes a multi-chip module package. As shown in FIG. 1, the package 1 includes a substrate 101, two stacked wafers 103, 105, and The support 107 between the two wafers 103 and 105, and the encapsulation gel for covering the wafers 103 and 105.
Ut。該兩晶片103、105係藉該支撐部107而相互堆疊，· 且糟多數銲線109而電性連接至該基板1G1，而該基板1〇1 係藉其背面植設之多數銲球ln將晶片ig3、ig5之訊號傳 輸至外界it而形成-多晶片模組球栅陣列<Ut. The two wafers 103 and 105 are stacked on each other by the support portion 107, and most of the bonding wires 109 are electrically connected to the substrate 1G1, and the substrate 101 is formed by a plurality of solder balls ln planted on its back surface. The signals of the chips ig3 and ig5 are transmitted to the outside it-a multi-chip module ball grid array <
Array，BGA)封裝件 j。 該模組封農件"系以堆疊晶片之方式，增加晶 片之數里’亚利用基板101多層的佈線整合電路功能，提 17846 5 1244146 供足夠多之輸人輸出端（I/Q)’以提升封裝件之功能與電 惟，使用基板雖具有佈線上之優點，卻亦 問題；此因基板之製造成本極高，往往約伯整體封裝^ 本之60〇/〇以上’亦將大幅提高產品之價格；同時，若堆最 式晶片中有任—晶片失效’整個封料即失效， = 形成基板成本上的大幅浪費。 〜有鑑於此，許多電子裝置為考量成本上之需求，例如 靜態隨機記憶體（static random access mem〇ry，SRam ) 等產品，即採用生産技術相對成熟且成本較為低廉之導線 架作為晶片之承載件，而以薄型尺寸封裝（ThinSmaU OWLine Package，TS0P )技術解決此一問題；例如美國專 利第5,283,717號案所提出之封裝件，即係將承載有晶片 ^基板置於導線架上，如第2圖所示，該封裝件2係包括 一晶片201、一基板203、複數個銲線205、一導電跡線層 2〇7、一晶片座209、複數個導腳211及一封裝膠體213，· 其中，δ亥晶片201係黏置於該基板2〇3上，以透過銲線2〇5 電性連接至該基板203表面之導電跡線層2〇7，並以該晶 片座209承載該基板203，復以銲線2〇5電性連接該基板 203之導電跡線層2〇7與周圍之對應導腳211，最後，再以 一封裝膠體213包覆該晶片座2〇9、基板2〇3、晶片2〇1、 與部分導腳2 11。 此一封裝件係利用基板203與導線架之整合，而可解 決傳統tsop技術中僅具有導線架之單層（1_layer)佈線缺 6 17846 1244146 ，’進而可藉該基板2G3上的多層佈線彈性 刀 s〇P封裝件中導腳數量有限之問題 士 善習知 圖之美國專利第6,555,9〇2號案，此^件：較於第！ 加佈線’再利用成本低廉之導線架f曰衣件係糟由基板 裝置，復可避免因美柘2fn而、酋 曰日片2〇1與外界 是T避免因基板加而導致生產成 響良解決前述一 203不Γ 裝件中諸如晶片201失效或基板 不良、紐路等電性連接問題均需於^ ^ 後，方能經〇/S測試發現，故^ =裝製程 =件之基板203與晶片座2〇9間亦存 遇之時，因膠體模流於上、下模具内所遭 為-二::=均產生_蝴。此些均 因此，如何開發一種封裝件及其製法，以 ，由測試確定晶片之良率，同時復兼顧晶片之積;^ 性、與整體成本’確為目前半導體封裝業亟需解 【發明内容】 址广；上述4知技術之缺點，本發明之主要目的在於提 供-種可於封裝前經測試碟定晶片良率的 封裝單元之封裝件及其製法。 'a曰片 本叙明之另一目的在於提供一種低成本的具有堆疊 式晶片封裝單元之封裝件及其製法。 7 17846 1244146 狀單-明之又：目的在於提供—種藉由定位部固定封 衣二：有：疊式晶片封裝單元之封裝件及其製法。 產生氣㈣Γ右一目的在於提供—種可避免模流不均而 ==疊式晶片封裝單元之封裝件及其製法。 為達别述及其他目的’本發明 單:之封裝件，其包括:―測試合格』 匕设邊二匕日日片之弟—封裝 ;，具有複數個導腳，且該複數個導腳係圍置出 域，以將該封裝單元定位於該容 用以連接該第-封裝件至該導線架之導：:::第 =^體’用以包覆該第—封裝件、部分導線架及該導 板、複數個電性:接 基板上且包覆該些晶片之第 ς體曰1以及形成於該ί 係具有複數個導腳；將該封衣y導線架， 出之容置區域位於該些導腳所圍置 線架之導腳，·以及連接該封裝單元與該導 覆該^裝單元、該導線架及部分導電=件第一封裝膠體包 前述之定位部主要係用 定位而使該封裝單元均勾：::：该封裝單元’同時藉其 不均之問題；而該定^ 下模具内，避免模流 H 糸可為該導線架之内導腳向下延 17846 1244146 伸亚低於該導線架平面所形成的階梯狀下沉定位腳；亦可 為該導線架導腳側之分叉定位腳；且如該導線架具有晶片Array (BGA) package j. The module package " is a method of stacking wafers to increase the number of wafers. 'Asia utilizes the multi-layer wiring of the substrate 101 to integrate circuit functions, providing 17846 5 1244146 for enough input / output (I / Q)' In order to improve the function and electricity of the package, although the use of the substrate has the advantages of wiring, it is also a problem; because of the extremely high manufacturing cost of the substrate, Job ’s overall package is often more than 60/0%. The price of the product; at the same time, if there is any task in the stack-type wafer-wafer failure 'the entire encapsulation will fail, = a significant waste of substrate cost. In view of this, many electronic devices consider cost requirements, such as static random access memory (SRam) and other products, that is, the use of relatively mature production technology and relatively low cost lead frame as the carrier of the chip Thin SmaU OWLine Package (TS0P) technology solves this problem; for example, the package proposed in US Pat. No. 5,283,717 is to place a wafer bearing a substrate on a lead frame, as in the second example. As shown in the figure, the package 2 includes a wafer 201, a substrate 203, a plurality of bonding wires 205, a conductive trace layer 207, a wafer holder 209, a plurality of guide pins 211, and a packaging gel 213, · Among them, the δ-Hai wafer 201 is adhered to the substrate 203 so as to be electrically connected to the conductive trace layer 207 on the surface of the substrate 203 through the bonding wire 205, and the substrate 209 is used to carry the substrate. 203. The conductive trace layer 207 of the substrate 203 is electrically connected to the surrounding corresponding guide pins 211 with bonding wires 205. Finally, the chip holder 209 and the substrate 2 are covered with a packaging gel 213. 〇3, wafer 201, and some guides 211. This package uses the integration of the substrate 203 and the lead frame, and can solve the lack of single-layer (1_layer) wiring with only the lead frame in the traditional tsop technology. 6 17846 1244146, and then can use the multilayer wiring elastic knife on the substrate 2G3 The problem of the limited number of guide pins in the SOP package is US Patent No. 6,555,920, which is a good example. This piece: Compared with the first! Add wiring and reuse the low-cost lead frame f. The clothing is connected to the substrate. It can avoid the US 2fn, the Japanese film 021 and the outside world T to avoid the production of good results due to the addition of the substrate. Solving the electrical connection problems such as the failure of the wafer 201 or the defective substrate, and the circuit of the 203 non-Γ assembly mentioned above need to be detected by 〇 / S test after ^ ^, so ^ = assembly process = substrate 203 of the component At the same time as the wafer holder 209, the colloidal mold flowed into the upper and lower molds was -2 :: = both produced _ butterfly. Therefore, how to develop a package and its manufacturing method to determine the yield of the wafer by testing, while taking into account the product of the wafer; the nature and the overall cost are indeed the urgent needs of the semiconductor packaging industry. 】 Wide address; the shortcomings of the above 4 known technologies, the main purpose of the present invention is to provide a package unit and its manufacturing method of a packaging unit that can determine the wafer yield before testing. Another object of this description is to provide a low-cost package with a stacked chip packaging unit and a method for manufacturing the same. 7 17846 1244146 List-Mingzhi: The purpose is to provide-a kind of fixing the seal by the positioning part 2: There is: the package of the stacked chip packaging unit and its manufacturing method. The purpose of generating gas ㈣Γ is to provide a package that can avoid uneven mold flow and == stacked chip packaging unit and its manufacturing method. For the purpose of mentioning other purposes, the package of the present invention includes: ―Passed the test‖, the younger brother of the Japanese film and the package—the package; has a plurality of guide pins, and the plurality of guide pins are Enclose the area to position the packaging unit in the container to connect the-package to the lead frame: ::: 第 = ^ 体 'is used to cover the-package, part of the lead frame And the guide plate, a plurality of electrical properties: the first body 1 connected to the substrate and covering the wafers, and formed on the frame with a plurality of guide pins; the coating y lead frame, the accommodation area The guide pins located on the wire frame surrounded by the guide pins, and connect the packaging unit with the guide cover, the mounting unit, the lead frame, and some conductive parts. The aforementioned positioning part of the first package gel pack is mainly used for positioning. And make the packaging unit :::: The packaging unit 'also borrows the problem of unevenness; and in the fixed mold, to avoid the mold flow H 糸 can be extended downward for the inner guide leg of the lead frame 17846 1244146 Shenya is lower than the stepped sinker positioning foot formed by the plane of the lead frame; it can also be the side of the lead frame of the lead frame Bifurcated positioning pin; and as the lead frame having a wafer
座’則亦可由該導線架之内導腳直接作為定位部，、發二曰 位之功能。 X 因此，藉由前述之封裝單元，即可測試該封裝單元内 之所有晶片功能，以保證封裝後之晶片均為已知合格晶片 J Kn0wn-Good Die，KGD )，從而可提高封裝件之良;了且 该封裝單元係具有基板之佈線功效，可增加線路佈局的彈 性，而且復可藉導線架而降低生産成本。此外，該封裝件鲁 ，可藉由凹下（Down-Set)内導腳定位部之設計而定位該封 裝單元，並兼顧模流不均等良率問題，充分解決了習知技 術之缺點。 【實施方式】 · 以下係藉由特定的具體實施例説明本發明之實施方 式，熟悉此技藝之人士可由本説明書所揭示之内容輕易地 瞭解本發明之其他優點與功效。本發明亦可藉由其他不同 的具體實例加以施行或應用’本説明書中的各項細節亦可鲁 基於不同觀點與應用，在不丨孛離本發明之精神下進行各種. 修飾與變更。 請參閱第3圖，係為本發明之具有堆疊式晶片封裝單 儿之封裝件的較佳實施例剖視圖，該封裝件3係包括一測 試合格之銲墊柵格陣列（Land Grid Array，LGA)型封裝 單tl 301，其係包括一基板3〇3、複數個電性連接至該基板 303之堆疊式晶片305、以及形成於該基板303上且包覆該 9 17846 1244146 些晶片305夕# 之弟一封裝膠體307 •太者 片奶而藉銲線連接至’本^例係以兩堆疊晶· 據設計決定曰曰月之齡曰^板03為例’實際製程中可根-覆晶方連接至基板303之方式，例如以 具有複數個導二述之封裝單元则係接置於- 3〇9向内延伸之端部係可作為一定 ？ *腳· 位部311係圍置出一容 。 _數個定 谷直（he域313，以將該封梦罝 · 定位於該容置區域313中· 又早兀301 、 匕A 中，其中，該定位部31 架之内導腳309向下延伸而采成你μ 糸4導線· 狀下沉（D_set)定位腳曰該導線架平面之階梯·The seat 'can also be used as the positioning part directly by the inner guide leg of the lead frame, and the function of the second position. X Therefore, by using the aforementioned packaging unit, all chip functions in the packaging unit can be tested to ensure that the packaged wafers are all known qualified wafers (J Kn0wn-Good Die, KGD), which can improve the quality of the package. In addition, the packaging unit has the wiring effect of the substrate, which can increase the flexibility of the circuit layout, and can reduce the production cost by using the lead frame. In addition, the package can locate the packaging unit by designing the inner guide pin positioning portion of the down-set, and takes into account the problem of uneven yield of mold flow, which fully solves the disadvantages of the conventional technology. [Embodiment] · The following is a description of specific embodiments of the present invention. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific examples. The details in this description can also be based on different viewpoints and applications, and various modifications and changes can be made without departing from the spirit of the present invention. Please refer to FIG. 3, which is a cross-sectional view of a preferred embodiment of a package with a stacked wafer package unit according to the present invention. The package 3 includes a tested and qualified Land Grid Array (LGA). The package package tl 301 includes a substrate 303, a plurality of stacked wafers 305 electrically connected to the substrate 303, and a plurality of stacked wafers 305 formed on the substrate 303 and covering the 9 17846 1244146 wafers 305 Xi #. Diyi encapsulated colloid 307 • Too much milk is connected to 'this example is based on two stacked crystals. According to the design decision, the age of the moon is called ^ board 03 as an example.' The actual process can be root-covered crystal square How to connect to the substrate 303, for example, a package unit with a plurality of introductions is connected to the end portion extending inward of -309 can be regarded as certain? * Foot and seat 311 surrounds the room. _ Several Dinggu straight (he field 313 to locate the nightmare in the accommodating area 313, and also in the early 301, dagger A, where the inner guide leg 309 of the positioning portion 31 is downward Extend and adopt your μ 糸 4 lead · D_set positioning feet are the steps on the plane of the lead frame ·
、UWn Set)疋位腳，且該容晋庶R 恰等於該封裝單元301之尺寸；同時，使;一係 或銲錫315連接於該定位部311上 ‘ =與該導線架之導腳•並將該封裝= 二f:: 至该導腳309上；此外，該封裝件3復包括一用= 料單元如、部分導線架及該導電黏著 ^ 第二封裝膠體317。 ^ ^的 ★本發明之具堆疊式晶片封裝單元之封料製法，係可·· 如第4A至4D圖所示，首先，如第4A圖所示，將一日片. 彻接置於基板403,透過銲線4〇5電性連接該晶片二 與該基板4G3之導電跡線層4G7;再藉—支撐部彻堆疊 另-晶片411於該晶片401之上，而同樣以銲線々η電性 連接該晶片川與該基板403之導電跡線層4〇7;々复以第 -封裝膠體415包覆該基板403及其上之晶片術川， 而形成- LGA封裝單元417。此時’即可藉由該基板4〇3 17846 10 1244146 底面之導電墊419 (Land)對該些晶片進行老化測試（Burn, UWn Set), and the capacity R is equal to the size of the packaging unit 301; at the same time, a series or solder 315 is connected to the positioning portion 311 '= and the lead of the lead frame The package = two f :: to the guide pin 309; In addition, the package 3 includes a material unit such as a part of the lead frame and the conductive adhesive ^ the second package gel 317. ^ ^ Of the present invention, the method for manufacturing a sealing material with a stacked chip packaging unit, as shown in Figs. 4A to 4D, first, as shown in Fig. 4A, a one-day piece. Completely placed on the substrate 403, electrically connect the second chip and the conductive trace layer 4G7 of the substrate 4G3 through the bonding wire 405; and then borrow-the support portion to completely stack another-the chip 411 on the wafer 401, and also use the bonding wire 々η The conductive trace layer 407 of the wafer and the substrate 403 is electrically connected; the substrate 403 and the wafer on the substrate 403 are covered with a first-package gel 415 to form an LGA package unit 417. At this time, the wafers can be subjected to burn-in test by using the conductive pad 419 (Land) on the bottom surface of the substrate 403 17846 10 1244146 (Burn
In)及功能測試（Functi〇nTest，F/T)，俾於測試合格後方 進入下'步驟。 如第4B圖所示，將前述製得之LGA型封裝單元417 置於導線架421之内導腳423末端定位部427所圍置出之 容置區域4 2 5中，該導線架4 2!係為一無晶片座式導線架， 而該些定位部427係該導線架421之内導腳423向下延伸 而形成低於该導線架421平面之階梯狀下沉（D〇wn ） 定位腳’以固定該LGA型封裝單元417。該封裝單元4i7 之基板403係朝下，以利用一導電黏著劑429電性連接該 型。封裝單元417與該導線架421之内導腳423,並將 該封裝單元417銲接於該些内導腳423上，以整合基板4们 與導線架421。 均所引起的填充氣洞 此時，藉由該導電黏著劑或銲錫429，將可增強嗜美 板403與導線架421間的連接強度，以改善脫層i導H 件斷裂所造成之斷路問題；同時，由於該導線架42ι之内 ‘腳423所圍置出的容置區域425係低於該導線架切平 面口此-亥LGA型封裝單疋417將可於後續模壓製程中均 勻佔據模具上、下模穴内之空間，而可避免產生因模流不 第4C圖係該LGA型封裳單元417黏置於該導線架 421之上視圖，由圖示可見得該内導腳423之彎折位置， 以藉此彎折形成-下沉定位部，俾使該些内導腳似向下 延伸至該LGA型封裝單元417之下，而可藉末端之定位部 17846 11 1244146 載該lga型封裝單元417，並藉該導 ，，連接定位；同時，該些定位部427所圍置二 區域425尺寸係與該LGA型 之效果。 生釕衷早兀417相同，以達定位 =所：出之製法係再如第4〇圖所示進行封膠 417一加裝膠雜431包覆該LGA型封裝單元 ^¥沭木421、及該些導電黏著劑或銲錫429， 如前述第3圖所示之具有堆疊式晶片封裝單元之封裳件成 =:由於該導線架421之内導腳423所圍置出 域425係低於該導線冑似之平面，故而該LGA型封裝單 兀417將得以均勾佔據該導線架平面之上下空間 於模塵製程中1LGA型封裝單元417於模具之上P =所佔據之高度極為相近’從而可避免產生模流、 —前述之結構與製法均係針對本發明之較佳實施例進 行説明’惟本法明之設計並非僅限於此，例如，言亥⑽型 二元二7與該些内導腳423之電性連接方式亦非僅限( 於則述之犯例，該定位部427之構成亦可採用其他方式。 以下係為本發明之其他實施例’惟與前述實施例相同之處 將不再贅述。 第5圖係本發明第二實施例之剖視圖，該封裝件之，士 :冓與前述較佳實施例之結構相似，其不同處在於，該封裳° 早兀501與導線架5〇3之連接方式係採銲線（In) and function test (FunctiOnTest, F / T), after the test is qualified, proceed to the next step. As shown in FIG. 4B, the LGA-type packaging unit 417 prepared as described above is placed in the accommodating area 4 2 5 surrounded by the end positioning portion 427 of the guide pin 423 in the lead frame 421, and the lead frame 4 2! It is a chipless lead frame, and the positioning portions 427 are the inner guide pins 423 of the lead frame 421 extending downward to form a stepped sinker (D0wn) positioning leg lower than the plane of the lead frame 421. 'To fix the LGA-type package unit 417. The substrate 403 of the packaging unit 4i7 faces downward, so as to be electrically connected to the type by using a conductive adhesive 429. The packaging unit 417 and the inner guide pins 423 of the lead frame 421 are soldered to the inner guide pins 423 to integrate the substrate 4 and the lead frame 421. At this time, the filled air holes caused by this can be enhanced by the conductive adhesive or solder 429 to improve the strength of the connection between the psychrophilic board 403 and the lead frame 421 to improve the disconnection problem caused by the delamination of the H-guide. ; At the same time, because the accommodation area 425 enclosed by the 'foot 423' within the lead frame 42m is lower than the cut plane of the lead frame, the LGA-type package single 疋 417 can evenly occupy the mold in the subsequent molding process. The space in the upper and lower mold cavities can be avoided due to the mold flow. Figure 4C is the view of the LGA sealing skirt unit 417 glued on the lead frame 421. The bend of the inner guide leg 423 can be seen from the illustration. Folded position to form a sinking positioning portion by this bending, so that the inner guide legs seem to extend downward below the LGA type packaging unit 417, and the lga type can be carried by the positioning portion 17846 11 1244146 at the end The packaging unit 417 is connected to the positioning by the guide; at the same time, the size of the two areas 425 surrounded by the positioning portions 427 is the same as that of the LGA type. The raw ruthenium is the same as the old 417, so that the positioning is equal to the place: The production method is as shown in Figure 40, and then the sealing 417 is installed, and the plastic 431 is added to cover the LGA type packaging unit ^ ¥ 沭 木 421, and The conductive adhesive or solder 429, as shown in the aforementioned FIG. 3, has a sealed package with a stacked chip packaging unit =: Because the area 425 surrounded by the inner guide pins 423 of the lead frame 421 is lower than that The wire looks like a plane, so the LGA-type packaging unit 417 will be able to evenly occupy the space above and below the plane of the lead frame. In the mold dust process, the 1LGA-type packaging unit 417 is above the mold. P = the height occupied is very similar. Mould flow can be avoided. The aforementioned structure and manufacturing method are described for the preferred embodiment of the present invention. 'However, the design of this method is not limited to this. For example, the Yanhai type binary 2 7 and these internal guides The electrical connection mode of the pin 423 is not limited to the above-mentioned cases. The positioning portion 427 can also adopt other methods. The following are other embodiments of the present invention, but the same points as the previous embodiments will Figure 5 is a sectional view of the second embodiment of the present invention Ten billions a similar structure of the aforementioned preferred embodiment, which is different from that, the blocked early Wu-chang ° and 501 of the connection frame 5〇3 conductor lines taken bonding wire (:, of the package, disabilities
Bonding )方式；此時，該LGA型封裝單元％ i之基板面 17846 12 1244146 朝上’而透過該基板面上之導電塾505與銲線連接，俾 藉°玄^ 線電性連接該封|單元5gi與導線架5G3;同時， 乂封二^元5〇1亦係放置於該導線架503之容置區域507 内，亚藉該導線架503之定位部509固定其位置。 立本兔明之封裝件結構亦可如第6圖所示之第三實施例 ^視圖’本實施例所使用之導線架係為具有晶片座_之 V線架601 ’該導線架6〇1之導腳6〇3並未向内彎折，而 ，直接在該導線架6〇1平面内圍置出一容置區域祕，俾 定位該，震單元6〇7,且該容置區域605之尺寸係與該LGA 31封裝單元607大小相同；同時，該導線架6〇1之晶片座 =9係用以承載該LGA型封裝單元術，且該lga型封裝 早兀6〇7係以銲線電性連接至該導線#⑷之導腳㈣， 與前述第二實施例相似，該LGA型封裝單元6〇7之基板面 係朝士，並藉其導電墊611與該銲線連接。 。前述各實施例之定位部均係利用内導腳之末端彎折 ^直接形成，惟本發明之定位部並非僅限於此；設計導線 架時’亦可將定位部與内導腳分開；例如第7八圖所示之 本發明第四實施例，該導線架7〇1之内導腳7〇3係均向下 L伸而低於该導線架7()1平面，以形成階梯狀之内導腳 作為電性連接之用，此時，該些導腳7〇3雖然亦圍置 出承載區域705，然由於該承載區域7〇5之尺寸仍大於 該LGA型封裝單元7〇7，故而並不具有定位之作用。本實 鼽例之定位係藉由該導線架7〇1内導腳側邊的分叉定 位腳709，以單獨作爲定位部，該些定位腳彻係於導線 17846 13 1244146 型=面内圍置出-容置區域711，其尺寸係等於該⑽ 元7〇7之大小；此時，該LGA型封農單元7〇7 係糟由该些分叉定位腳709而定位於該容置區域爪中， 並藉由該些内導腳服與導電黏著劑713進行電性傳輸。 第7B圖所不係為前述第四實施例中封裝單元7〇7設 置於導線架701之上視圖，可由圖示見得該内導腳7〇3: 曾折位置’該些内導腳7G3傳、向下延伸至該LGA型封裝單 7凡〇771'之下’而可藉該内導腳7。3電性連接至該封裝單元 — 上之導電黏著劑713 ;因此，若與前述第4C圖之 貫施例比較，可更清楚見得本實施例階梯狀内導腳期之 写折部係較第4C圖為長，故其所圍置出的承載區域期 面積亦較大’而不具妓位作用；本實施例之封裝單元7〇7 係猎該些分叉定位腳709所圍置出之容置區域Η〗尺寸， 而定位該LGA型封裝單元7〇7，以達固定之效果。 第7C圖係為-内導腳期及其側之分又定位腳谢 之立體示意圖’更有助於瞭解兩者之位置關係，·在導線架 701平面内’該導線帛7〇1之内導腳期係低於該平面，丨 以承載並電性連接封裝單元斯；該内導腳期側邊則形 成一分叉定位腳709’其係位於導線架7〇1的同一平面， 並與該内導腳703具有一長度差。 綜上所述，本發明之設計確可進行各種等效變化，導 線架定位部的不同設計、封裝單元於導線架的不同連接方 式，在不悖本發明精神之前提下，確能靈活達成本發明。 此外’前述各實施例係均以封裝單元内承載兩堆疊晶 17846 14 1244146 片為例，惟本發明之且田 非僅限於此，並他多1 式晶片封裝單元之封裝件並 夕日日片之堆叠設計亦均適用於本發明。 將曰二〖生=可知本發明之設計確具有多種功效，既可 計==至可佈線之基板上，而提升其佈線上之設 再為提古之縣板整合於導線架上，降低整體成本； 再為“良率之目的，亦w 片及基板進行封裝而形成 接，基板後，對该曰曰 片，避免製程上之浪費.此夕公兀，並藉此預先測試晶 彎折成形之優點，定位今封^亦可利用該導線架導腳易 兼顧模勹夕a X 裝早兀，並調整其位置關係而 兼顧杈4勻之功效，“提供— 體封裝件。 且间口口貝的丰導 上述實施例僅例示性説明本發明之 用於限制本發明。任何熟習此項技藝之人士均^不^ =明下」！上述實施例進行修飾與改^ 所列。」之柄利保護範圍’應如後述之申請專利範圍 【圖式簡單説明】 醤 第1圖係美國專利第6,555,902號 剖視圖； < 訂展件 第2圖係美國專利第5,283,717號案所揭 剖視圖； >了展件 f3圖係本發明之具有堆疊式晶片封裝單元 較佳實施例之剖視圖； 衣件 第4A至4D本發明之具有堆疊式晶片封裝單元、另 可衣 17846 15 1244146 件較佳實施例之製法流程圖； 第5圖係本發明之具有 之第二實施例剖視圖；“丄崎早元之封装件 …第=圖係本發明之具有堆疊式晶片封襄單元之封 之第二貫施例剖視圖； 第Μ圖係本發明之具有堆疊式晶片封 件之第四實施例剖視圖； 之封裒 件之^ 7Β-圖係本發明之具有堆疊式晶片封裝單元之封裝 件之第四貫施例上視圖；以及 第7C圖係第7Β圖所示之實施例之 位腳之立體圖。 久八刀又疋 主要元件符號說明】 1 封裝件 103、 1〇5晶片 109 銲線 113 封裝膠體 201 晶片 205 鲜線 209 晶片座 3 封裝件 303 基板 307 第一封裝 311 定位部 315 導電黏著 101 107 111 2 203 207 211 301 305 膠體 309 313 劑/銲錫 317 基板 支撐部 銲球 封裝件 基板 導電跡線層 導線架 封裝單元 晶片 導腳 容置區域 第二封裝膠體Bonding) method; at this time, the substrate surface of the LGA-type packaging unit% i is 17846 12 1244146 facing up, and is connected to the bonding wire through the conductive 塾 505 on the substrate surface, and the seal is electrically connected through the ° xuan line. The unit 5gi and the lead frame 5G3; at the same time, the sealed second element 501 is also placed in the accommodation area 507 of the lead frame 503, and its position is fixed by the positioning portion 509 of the lead frame 503. The structure of the package of Libentuming can also be shown in the third embodiment shown in FIG. 6 ^ View 'The lead frame used in this embodiment is a V wire frame 601 with a wafer holder _' the lead frame 601 The guide leg 603 is not bent inward, and a housing area is directly enclosed in the plane of the lead frame 601, and the positioning unit 6007 is located, and the housing area 605 The size is the same as the size of the LGA 31 package unit 607. At the same time, the chip holder of the lead frame 601 = 9 is used to carry the LGA type packaging unit technology, and the lga type package 609 is soldered. Electrically connected to the guide pin 导线 of the wire # ⑷, similar to the second embodiment described above, the substrate surface of the LGA-type packaging unit 607 is facing the driver, and is connected to the bonding wire through its conductive pad 611. . The positioning portions of the foregoing embodiments are directly formed by bending the ends of the inner guide legs, but the positioning portions of the present invention are not limited to this; when designing the lead frame, the positioning portions can also be separated from the inner guide legs; The fourth embodiment of the present invention shown in FIG. 7 shows that the inner guide pins 703 of the lead frame 700 extend downward L and are lower than the plane of the lead frame 7 () 1 to form a stepped inner portion. The guide pins are used for electrical connection. At this time, although the guide pins 703 also surround the load-bearing area 705, the size of the load-bearing area 705 is still larger than that of the LGA-type packaging unit 707. Does not have a positioning effect. The positioning of this example is based on the bifurcated positioning legs 709 on the side of the inner guide leg of the lead frame 701, and it is used as the positioning part alone. These positioning legs are completely tied to the lead 17846 13 1244146 type. The size of the exit-receiving area 711 is equal to the size of the unit 707. At this time, the LGA-type farmer unit 707 is positioned in the accommodating area by the branch positioning feet 709. In addition, electrical transmission is performed through the inner guide feet and the conductive adhesive 713. FIG. 7B is not a view of the packaging unit 707 provided on the lead frame 701 in the fourth embodiment, and the inner guide pins 703 can be seen from the illustration: the positions of the inner guide pins 7G3 have been folded. It can be extended to the bottom of the LGA-type package sheet 7771 ′, and can be electrically connected to the packaging unit — the conductive adhesive 713 on the inner lead pin 7.3; Comparing the conventional examples in Figure 4C, it can be clearly seen that the folding section of the stepped inner guide leg period in this embodiment is longer than that in Figure 4C, so the area of the bearing area surrounded by it is also large. ' There is no prostitute effect; the packaging unit 707 in this embodiment hunts for the size of the accommodating area surrounded by the branch positioning feet 709, and positions the LGA-type packaging unit 707 to achieve a fixed effect. Figure 7C is a three-dimensional schematic diagram of the inner guide leg period and its side positioning and positioning of the foot. It is more helpful to understand the positional relationship between the two. In the lead frame 701 plane, the wire is within 701. The lead pin period is lower than the plane, and carries and electrically connects the packaging unit; the inner lead pin side forms a branch positioning pin 709 ', which is located on the same plane of the lead frame 701, and The inner guide leg 703 has a length difference. In summary, the design of the present invention can indeed make various equivalent changes. The different designs of the lead frame positioning portion and the different connection methods of the packaging unit to the lead frame can be flexibly achieved without raising the spirit of the present invention. invention. In addition, the foregoing embodiments are based on the example of carrying two stacked crystals in the packaging unit 17846 14 1244146, but the present invention is not limited to this, and the package of the type 1 chip packaging unit and the day and night chips Stack designs are also applicable to the present invention. It will be known that the design of the present invention does have a variety of effects. It can be counted == to the wiringable substrate, and the wiring design is improved, and the ancient county board is integrated on the lead frame, which reduces the overall Cost; for the purpose of "yield," the wafer and the substrate are packaged to form a connection. After the substrate, the wafer is used to avoid waste in the manufacturing process. Now, it is public and this is used to test the crystal bending forming in advance. Advantages, positioning this seal ^ can also use the lead frame guide feet easy to take into account the mold X ax early installation, and adjust its positional relationship while taking into account the effects of the uniformity, "provided-body package. In addition, the above-mentioned embodiments merely illustrate the present invention for limiting the present invention. Anyone who is familiar with this skill ^ no ^ = Ming "! The above embodiments are modified and listed. "The scope of protection of the handle" should be the scope of the patent application as described later. [Simplified illustration of the drawing] 醤 Figure 1 is a cross-sectional view of US Patent No. 6,555,902; < Ordered Part 2 is a cross-sectional view disclosed in US Patent No. 5,283,717. ; ≫ The drawing f3 is a cross-sectional view of a preferred embodiment of the present invention with a stacked chip packaging unit; clothing pieces 4A to 4D of the present invention have a stacked chip packaging unit, and can be worn 17846 15 1244146 The manufacturing method flow chart of the embodiment; FIG. 5 is a cross-sectional view of the second embodiment of the present invention; “the package of Sakizaki Hatsumoto ... The second diagram is the second of the seal of the present invention with a stacked wafer sealing unit Sectional view of the embodiment; FIG. M is a cross-sectional view of a fourth embodiment of the present invention with a stacked wafer package; 7B- FIG. Is a fourth of the package of the present invention with a stacked wafer packaging unit The top view of the embodiment; and FIG. 7C is a perspective view of the position feet of the embodiment shown in FIG. 7B. Jiubadao and the main component symbol description] 1 package 103, 105 chip 109 bonding wire 113 seal Colloid 201 Wafer 205 Fresh line 209 Wafer holder 3 Package 303 Substrate 307 First package 311 Positioning part 315 Conductive adhesive 101 107 111 2 203 207 211 301 305 Colloid 309 313 Agent / solder 317 Substrate support part Solder ball package Substrate conductive trace Wire layer lead frame packaging unit, chip lead pin receiving area, second packaging gel
17846 16 1244146 401 晶片 403 基板 405 銲線 407 導電跡線層 409 支撐部 411 晶片 413 銲線 415 第二封裝膠體 417 封裝單元 419 導電墊 421 導線架 423 内導腳 425 容置區域 427 定位部 429 導電黏著劑/銲錫 431 第二封裝膠體 501 基板 503 導線架 505 導電墊 507 容置區域 509 定位部 601 導線架 603 内導腳 605 容置區域 607 基板 609 晶片座 611 導電墊 701 導線架 703 内導腳 705 承載區域 707 封裝單元 709 分叉定位腳 711 容置區域 713 導電黏著劑/銲錫 17 1784617846 16 1244146 401 Wafer 403 Substrate 405 Welding wire 407 Conductive trace layer 409 Supporting part 411 Wafer 413 Welding wire 415 Second package gel 417 Packaging unit 419 Conductive pad 421 Lead frame 423 Inner guide pin 425 Receiving area 427 Positioning part 429 Conductive Adhesive / solder 431 Second package gel 501 Substrate 503 Lead frame 505 Conductive pad 507 Receiving area 509 Positioning section 601 Lead frame 603 Inner guide pin 605 Receiving area 607 Substrate 609 Wafer holder 611 Conductive pad 701 Lead frame 703 Inner guide pin 705 Loading area 707 Packaging unit 709 Bifurcated positioning pin 711 Receiving area 713 Conductive adhesive / solder 17 17846