TWI244121B - Chemical shrink process applied in the method of manufacturing micro-nanometer circuit - Google Patents

Chemical shrink process applied in the method of manufacturing micro-nanometer circuit Download PDF

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Publication number
TWI244121B
TWI244121B TW93134047A TW93134047A TWI244121B TW I244121 B TWI244121 B TW I244121B TW 93134047 A TW93134047 A TW 93134047A TW 93134047 A TW93134047 A TW 93134047A TW I244121 B TWI244121 B TW I244121B
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Taiwan
Prior art keywords
chemical
metal layer
nanometer
circuits
circuit
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TW93134047A
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Chinese (zh)
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TW200616033A (en
Inventor
Yung-Chiang Ting
Sliyi-Long Shy
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Far East College
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Publication of TW200616033A publication Critical patent/TW200616033A/en

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Abstract

This invention relates to a chemical shrinking process applied in the method of manufacturing micro-nanometer circuit, which overcomes the size limit of exposure wavelength by combing the chemical shrinking process to produce circuits with sizes smaller than the exposure wavelength, wherein after the process of deposition, image developing and plasma etching, the chemical shrinking agent is applied to the metal-wire circuit to enable it to shrink to the size smaller than exposure wavelength, which produces micro-nanometer circuits.

Description

1244121 五、發明說明(1) 【發明所屬之技術領域】 本發明係關於一種化學微縮製程應用於微奈米線路製 造之方法,尤指一利用化學微縮方式予以解決微奈米線路 製造成型上受限於光束波長之缺失者。 【先前技術】 按,在傳統之微影製程中主要係包括塗底、光阻塗 佈、預烤、曝光、曝後處理、顯影以及硬烤等數個步驟, 其中,尤其在曝光這個過程中,對於整個元件尺寸扮演著 相當重要的地位,其主要係採用光罩予以曝光顯影,藉以 將光罩上之圖案移轉到光阻層上,接著利用蝕刻技術將部 份未被光阻保護的金屬層(一般為氮化矽層)加以除去,留 下的就是所需要的線路圖部份;然而,現有微奈米製造利 用鉻膜光罩及光學曝光產生線路,只能產生大於曝光波長 的線路,小於曝光波長的線路製作需要用到複雜昂貴的相 移光罩及光學近接效應修正;然而,相移光罩之製作上由 於尺寸十分精密,其成本售價相當的高,使得該種製作小 於曝光光束波長的線路,其製造成本極高。 【發明内容】 本發明之主要目的即在於提供一種化學微縮製程應用 於微奈米線路製造之方法,其主要係配合化學微縮製程予 以克服曝光波長之尺寸限制,俾以製造出小於曝光波長之 線路尺寸者。 而本發明之製造方法主要係在於基底層與光阻層間成 型一金屬層,並利用電漿蝕刻方式先行去除不需要之金屬1244121 V. Description of the invention (1) [Technical field to which the invention belongs] The present invention relates to a method for applying a chemical microfabrication process to the manufacture of micronano circuits. Limited to the lack of beam wavelength. [Previous technology] According to the traditional lithography process, it mainly includes several steps such as coating, photoresist coating, pre-baking, exposure, post-exposure processing, development, and hard baking. Among them, especially in the process of exposure It plays a very important role for the entire component size. It mainly uses a photomask for exposure and development, so that the pattern on the photomask is transferred to the photoresist layer, and then the part that is not protected by photoresist is etched using etching technology. The metal layer (usually a silicon nitride layer) is removed, and what is left is the required part of the circuit diagram; however, the existing micro-nanometer manufacturing uses a chromium film mask and optical exposure to generate the circuit, which can only produce a wavelength greater than the exposure wavelength. Circuits, the production of circuits smaller than the exposure wavelength requires the use of complex and expensive phase shift masks and optical proximity effect correction; however, the phase shift masks are manufactured with very precise dimensions and their cost is quite high, making this kind of production Lines smaller than the wavelength of the exposure beam are extremely expensive to manufacture. [Summary of the Invention] The main purpose of the present invention is to provide a method for applying chemical microfabrication process to micron nanometer circuit manufacturing, which is mainly used in conjunction with the chemical microfabrication process to overcome the size limitation of the exposure wavelength, so as to manufacture circuits smaller than the exposure wavelength. Sizer. The manufacturing method of the present invention is mainly formed by forming a metal layer between the base layer and the photoresist layer, and using plasma etching to remove unnecessary metals first.

1244121 五、發明說明(2) 層及光阻層,再藉由化學微縮製程針對將該已蝕刻後之金 屬層再一次進行微縮,俾以產生微奈米線路者。 【實施方式】 如第一圖所示,本發明之微奈米線路製作步驟如下: (a )化學沈積: 在基底層(1 )上利用加熱、吸附或是化學反應擴散 在基底層(1)表面產生一金屬層(2),再於金屬層(2)表面 鍵上一層光阻層(3)。 (b)顯影: 利用曝光光源將光罩上之圖形轉移顯影於光阻層 (3A)上,而留下所需的光阻層(3A)圖案部份。 (c )電漿蝕刻: 將未被光阻層(3 A )保護到的金屬層(2 )利用電漿蝕 刻去除,僅留下與光阻層(3A)圖案相同之金屬層(2A)。 (d )化學微縮: 將上述半成品浸泡於化學微縮劑内,或以化學微 縮劑塗覆於金屬層(2 A)上,而所採用之化學微縮劑,例 如:(NH4)CE(N03)6HND03,其主要是利用殘留於阻劑中的 光酸分子,來催化化學微縮劑之交鏈反應,以使金屬層 (2 B)得以微縮至小於曝光波長之尺寸;如第二圖所示,其 係舉鉻質之金屬層為例,經實驗證明,該鉻質金屬浸泡在 化學微縮劑中,約1 0秒鐘之作用時間即可蝕刻2 0奈米的深 度,而在2 0秒鐘内,蝕刻到4 0奈米深度,如此一來,即可 藉由控制浸泡之時間予以決定金屬層(2 B)之微縮深度。1244121 V. Description of the invention (2) The layer and the photoresist layer are further reduced by the chemical microfabrication process to the etched metal layer to produce micronano circuits. [Embodiment] As shown in the first figure, the micronano circuit manufacturing steps of the present invention are as follows: (a) Chemical deposition: The substrate (1) is diffused in the substrate (1) by heating, adsorption or chemical reaction. A metal layer (2) is generated on the surface, and a photoresist layer (3) is bonded to the surface of the metal layer (2). (b) Development: Use the exposure light source to transfer and develop the pattern on the photomask onto the photoresist layer (3A), leaving the required pattern portion of the photoresist layer (3A). (c) Plasma etching: The metal layer (2) not protected by the photoresist layer (3A) is removed by plasma etching, leaving only the metal layer (2A) with the same pattern as the photoresist layer (3A). (d) Chemical microfabrication: The semi-finished product is immersed in a chemical microfabricating agent, or is coated on the metal layer (2A) with a chemical microfabricating agent. , Which mainly uses the photoacid molecules remaining in the resist to catalyze the cross-linking reaction of the chemical micronizing agent, so that the metal layer (2 B) can be reduced to a size smaller than the exposure wavelength; as shown in the second figure, its Take the chrome metal layer as an example. It has been experimentally proven that the chrome metal is immersed in a chemical micronizing agent and can be etched to a depth of 20 nanometers in about 10 seconds, and within 20 seconds Etching to a depth of 40 nanometers, so that the shrinkage depth of the metal layer (2 B) can be determined by controlling the immersion time.

1244121 五、發明說明(3) (e )移除光阻: 利用化學劑清洗將光阻層(3 A )移除後,再利用烘 烤程序使該經化學微縮後之金屬層(2 B)予以定型,而該定 型後之金屬層(2 B )即為微奈米線路。 經由上述(a )〜(e )製作步驟,將可有效克服曝光波長 之限制,使金屬層(2 B )得以加工至比曝光波長更小之尺 寸;例如,使用0 · 4 3 6微米波長之紫外線光曝光顯影後, 配合化學微縮製程使用,將可製作出0 · 2 5微米的金屬線路 者。 綜上所述,本發明所提供之化學微縮製程應用於微奈 米線路製造之方法,其藉由化學微縮劑予以製作小於波長 之線路,可有效降低製造成本,誠已合乎發明相關要件, 爰依法提出申請。1244121 V. Description of the invention (3) (e) Removal of photoresist: After removing the photoresist layer (3 A) by chemical cleaning, the baking process is used to make the chemically reduced metal layer (2 B) It is shaped, and the shaped metal layer (2 B) is a micro-nano line. Through the above (a) ~ (e) manufacturing steps, the limitation of the exposure wavelength can be effectively overcome, so that the metal layer (2B) can be processed to a size smaller than the exposure wavelength; for example, using a wavelength of 0. 4 3 6 microns After exposure to ultraviolet light and development, it can be used in combination with a chemical microfabrication process to produce a metal circuit of 0. 25 microns. In summary, the chemical microfabrication process provided by the present invention is applied to a method for manufacturing micron nanometer circuits. The use of chemical micronizing agents to make circuits smaller than the wavelength can effectively reduce the manufacturing cost. It is in line with the relevant requirements of the invention. Apply according to law.

12441211244121

Claims (1)

1244121 六、申請專利範圍 一種化學微縮製程應用於微奈米線路製造之方法,其 係在基底層與光阻層間成型金屬層,並利用電漿蝕刻先行 去除不需要之金屬層,再利用化學微縮製程針對將該金屬 層進行微縮,俾以產生微奈米線路者。1244121 6. Scope of patent application A method of applying chemical microfabrication to micron nano-circuit manufacturing, which involves forming a metal layer between a base layer and a photoresist layer, and then removing unnecessary metal layers by plasma etching, and then using chemical microfabrication The manufacturing process is directed to shrinking the metal layer to produce micronano circuits.
TW93134047A 2004-11-09 2004-11-09 Chemical shrink process applied in the method of manufacturing micro-nanometer circuit TWI244121B (en)

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Application Number Priority Date Filing Date Title
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TWI244121B true TWI244121B (en) 2005-11-21
TW200616033A TW200616033A (en) 2006-05-16

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