TWI243450B - Non-volatile memory and fabrication thereof - Google Patents

Abstract

A non-volatile memory structure and a fabricating method thereof are described. In the method, a mask layer is formed on a substrate, and a trench is formed in the mask layer and the substrate. A tunnel dielectric layer is formed in the trench, and then a floating gate is formed in the trench. The mask layer is removed. A high-voltage doped region is formed in the substrate on one side of the floating gate to serve as a first source/drain region and a control gate simultaneously, and then a second source/drain region is formed in the substrate on the other side of the floating gate.

Description

1243450 V. Description of the invention (1) This specification refers to the structure of a semiconductor device and its manufacturing method, and the structure and the structure of a nonvolatile memory (n 〇η-v ο 1 ati 1 emem 〇ry) and Its manufacturing method. I Pre-technology 沔 Supply ϊ: Programmable and erasable non-volatile memory has no electricity data, fast access speed, light weight and large capacity, access devices, and special concerns2, so it has gradually become a portable memory medium Mainstream product i: / 二 f "The basic structure of non-volatile memory includes a floating gate and a control gate. Two optional gates can be set next to the floating gate to form a -blade armor p 1 gate) structure, which is used to To prevent problems caused by over_erase. Figure 6 shows the structure of a non-volatile memory that can be electrically programmed and erased, such as the gate 602. Erfu 606 on the surface of the substrate 600, thermal oxidation layer 604 on the top and side walls of Gudian 拎 2, and the spacers. :: pressure doping = 608, two choices, and two sources " and electrode The area nr / by ^ Γ doped region 608 is located in the base: 60 between the two floating gates 602 and overlaps with the bottom portion of the two floating gates 602 to serve as both; and the polar orbit region / Control gate. The selection gate 610 is located on the outer side of the floating room 602 and is thermally oxidized 6 Q 4 is the rear strip β Λ β of the gas worm, * 7? / ^ F 8 1 9 al ^ B 永 J 6 The 0 6 is separated from the 泮 gate 6 0 2, and the source /, and pole 612 are located in the base 6 0 0 outside the selection gate 61 0. Although there are many applications of the above structure, please refer to Figure 6 Because it doubles as the brake „+ > _ / The following question I. Enjoy f series? w * The closed 1 μM doped region 608 only overlaps with the bottom of a question 602 'so the extremely light ratio (Gate 11907twf.ptd page 5 1243450 V. Description of the invention (2) Coupllng Katl0, GCR) is very low, making the writing and erasing voltage to carry out 'not conducive to the reduction of the device. In addition, the height of both 602 and 610 is very large, so the next choice is to close the second question = ㈣ is more difficult. In addition, the high-voltage region of the heart must have a sufficiently low resistance, but its depth must not be too large to avoid punch-thorough leakage, so the wide production reduction space of the high-voltage doped region 608 is very small. , Is not conducive to the reduction of components. According to the invention of the internal structure, the present invention proposes a method for forming non-volatile memory, in which a part of the floating gate is embedded in the substrate, so that the N voltage impurity region can be related to the side of the floating gate. adjacent. The steps of a method for manufacturing a non-volatile memory according to the present invention are as follows. First, a mask layer is formed on the substrate, a trench is formed in the mask layer and the substrate, and then a tunneling dielectric layer is formed in the trench. A gate is then formed in the trench, and the cover layer is removed. After that, a voltage-doped region is formed in the substrate on one side of the floating gate, which simultaneously serves as a first source / drain region and a second source / drain region is formed in a substrate controlled on the other side of the floating gate. . On the other side of the Zheyang gate, a selective gate can be formed, which is located between the floating gate and the second source / drain region, and there is a gate dielectric layer between the gate and the base. In another method for manufacturing a non-volatile memory according to the present invention, the high-voltage two-hybrid region is formed in a base between a floating gate, and is used by the two-memory cell. In addition, a selection gate is formed on the outside of each floating gate, and a source / drain region is formed on the outside of each selection gate. The "outside"

1243450 V. Description of the invention (3) side "is the part facing the area between two floating gates across the floating gate ', and the area between the two floating gates is" inside ". In another aspect, a non-volatile memory of the present invention includes a substrate, a sub-gate, a high-voltage doped region that serves as a first source / drain region and a control gate, and a second source / drain region. . Among them, there is a trench on the substrate, and the surface of the trench includes a dental tunnel dielectric layer. A floating gate system fills the ditch and protrudes above the ditch. The same-voltage doped region is located in a base of the floating space, and the second source / inverted region is located on the bottom side of the base 'on the other side of the floating closure. = ^ On the other side of the gate, a selective gate can be configured, which is located between the floating gate and the second source / drain region, and has a gate dielectric layer spaced from the substrate. In another non-volatile memory structure of the present invention, a high voltage is doped into the substrate between the 5 5 position and the 2ϊ gate, and is shared by the two memory cells. k, there is a selection gate on the outside of each floating gate, and there is a source / drain region on the outside of each selection gate. In order to control the buried coupling etching, there is a high fear of shrinking. In order to make it easier to understand, in the non-volatile memory structure of the present invention, the voltage doping region in the south of the gate can be connected to the side of the floating gate. The edges overlap, so the GCR will be greatly improved. In addition, since one part of the floating gate is at the bottom, the Gan gate is lowered by one or two degrees, so the subsequent selection of the gate is easy. Furthermore, since the bottom of the floating gate is deeply penetrated into the substrate, the through-tap region can be formed deeper to reduce the resistance without the need for a gate pass. Therefore, the width of the high-voltage doped region can be obtained, which is beneficial to the reduction of the device. Let the present invention: ^ v, +, fan, and other purposes, features, and advantages be clearer, and the preferred embodiment will be described in detail, and will be described in detail with the accompanying drawings.

1243450 V. Description of the invention (4) The description is as follows: Figures 1 to 5 show the non-J process sectional view of the preferred embodiment of the present invention 'wherein Figure 5 shows the corresponding non-volatile memory = refer to Figure i' first A pad oxygen i 〇2 = Nitride nitride hard cover curtain layer i 〇4 is formed in sequence on the base Q, wherein the substrate] 〇〇 is, for example, a p-type doped base f, and the nitrided nitride hard cover curtain layer 104 The formation method is, for example, a low chemical vapor deposition method (LPCVD). Next, a pair of trenches 106 is formed in the nitride base material m. The steps include a photolithography process and a subsequent anisotropic etching process. , /,, Refer to Figure 2, and then the base in the trench 106]

Ltrb! (Rnel, 0Xlde layer) 108 Emulsification method. Then take a conductor layer, for example, a channel: 1.6 'to use as the floating room 110, and then perform a full groove to form a middle step on the top of the floating gate 110, and use JL to form π, > The thin thermal emulsion layer 1 1 2 is violated, and the shape of the top edge of the Yangyang gate 110 will be described later. The power of this shape in the shape of a large moon Please refer to Figure 3, and then go to 气 气 # Between the substrate 100, and: " its: J is exposed two floating, and then, the ion implantation 116 grass_curtain ": if it is a photoresist layer. The common source / drain region is used for the control gate and the hood to the temple: sjiyi cell is shown to remove the hood curtain layer 1 1 4. Then proceed to page 8 ^ 9〇twtw.ptd 1243450, description of the invention (5) Fire to repair the lattice structure damaged by ion implantation, and at the same time extend the range of the high voltage doped region 1 1 8 to part of the floating Under the gate 丨 丨 〇. Refer to FIG. 4, and then form a 0N gap wall composed of a silicon oxide layer 120 and a silicon nitride layer 12 on the exposed side walls of each floating gate. The formation method includes sequentially forming a conformal oxide. The silicon layer and the conformal silicon nitride layer (not shown), and then the conformal silicon nitride layer and the conformal silicon oxide layer are anisotropically etched to form the shape of the partition wall. Then, a conformal oxide silicon layer 1 24 is formed on the substrate 100 as an isolation layer between the floating gate 1 and the selective gate to be formed later (Figure 5), and As the gate dielectric layer (FIG. 5) of the selection gate 128, please refer to FIG. 5. Part of the silicon oxide layer 124, the silicon oxide layer 12 and the siliconized silicon layer 122 are combined to form a 0N0 spacer 126. Has a good effect of preventing leakage. After that, a selection gate 1 2 8 is formed on the outside of the floating gate 丨 丨 〇, which is a part of the floating gate 丨 丨 〇, and the thermal oxidation layer 丨 2 and the top of the floating gate 丨 〇, to The spacer wall 126 is separated from the wall of the floating gate 110, and the gate dielectric layer 124 is separated from the substrate 00. Then, in each one, the non-volatile of the preferred embodiment is completed. # # # # ^ ^ # ^ ^ ^, 1 o Here, the structure includes a substrate 100, two floating gates 110, and a high-electricity doped region. m. The selection gate 128 and the two sources, the drain region is electrically connected to the trench 106, and the surface is provided with a dielectric dielectric. The basement 10 of the Second Middle School fills the trench 106 and protrudes above the trench 106. . On the top of the 20 there is a thermal oxide layer ⑴, whose shape is such that the floating room 11

1243450

5. Description of the invention (6) The top edge of the invention is pointed, and the side wall has a 0N0 gap wall 126. The high-voltage doped region 1 1 8 is located in the substrate 100 between the two floating gates 1 1 0, and the two selection gates 1 2 8 are located outside the two floating gates 1 1 0, respectively. 2 8 is separated from the top of the corresponding floating gate 1 1 0 by a thermal oxide layer 1 1 2, separated from the side wall of the floating gate 110 by a 0N0 partition wall 126, and separated from the substrate by a gate dielectric layer 1 2 7 1 000 apart. The two source / drain regions 130 are respectively located in the base 1 100 of the two alternatives 1 110. A

In addition, the operation method of the non-volatile memory of the preferred embodiment of the present invention is exemplified as follows. Please refer to Figure 5. If you want to write to the memory cell on the left, you must apply enough voltage on the left selection gate 1 2 8 to open the channel below it.

Apply a low voltage (usually 0v) to the left source / drain region, and simultaneously apply a high voltage to the high voltage doped region 1 1 8 to induce a slightly lower voltage on the floating gate 丨 丨 〇 Voltage, thereby attracting hot electrons into the floating gate 丨 丨 〇, as shown by the arrow. Conversely, if you want to erase the memory cells on the left, you must apply a positive voltage to the left selection " select gate 1 28, and at the same time apply a negative voltage to the high voltage doped region 丨 丨 8, you can now A tip discharge effect is induced at the left corner of the top of the gate 1 丨, and the electrons in the floating gate 11 〇 are discharged to the selection gate 28, as shown by an arrow e. Because the tip discharge effect occurs at the sharp corner of the top of the floating gate 110, the positive voltage applied to the selection gate 1 28 can be lower than that required for general non-memory erasing operations. As described above, referring to FIG. 5, in the non-volatile memory structure of the preferred embodiment of the present invention, the high voltage doping region 118 as a control idle not only overlaps the bottom of the floating idle, but also passes through the media at the same time. Electrical layer 108 and floating gate 11 0 0 0, phase f 10, so its gate coupling ratio (GCR) can greatly improve

1243450 V. Description of the invention (7) High. In addition, since a part of the floating gate 110 is buried in the substrate 100, the height thereof is reduced, so it is easier to select the definition of the gate 1 28 in the subsequent etching. Furthermore, since the bottom of the floating gate 110 is deep into the substrate 100, the high-voltage doped region 1 18 can be formed deeper to reduce resistance without having to worry about the problem of breakdown leakage. Therefore, the width of the high-voltage doped region 118 can be reduced, which is beneficial to the reduction of the device. Although the present invention has been disclosed as above with preferred embodiments, it is not intended to limit the present invention. Any person skilled in the art can make various modifications and retouches without departing from the spirit and scope of the present invention. Therefore, the present invention The scope of protection shall be determined by the scope of the attached patent application.

11907twf.ptd Page 11 1243450 Brief Description of Drawings Figure 5 shows a cross-sectional view of a non-volatile memory manufacturing process according to a preferred embodiment of the present invention, and Figure 5 shows the corresponding structure of the non-volatile memory. FIG. 6 is a structural cross-sectional view of a conventional non-volatile memory cell. Schematic description 100 substrate 102 pad oxide layer 104 silicon nitride hard mask layer 106 trench 1 渠 8 tunnel oxide layer 110 floating gate 112 oxide layer 114 mask layer 116 ion implantation 118 high voltage doped region 120 silicon oxide Layer 122 silicon nitride layer 124 silicon oxide layer 126 ΝΟ spacer wall 128 select gate 130 source / drain 600 substrate 602 floating gate 604 thermal oxide layer 606 spacer wall

11907twf.ptd Page 12 1243450

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Claims (1)

1243450 VI. Application Patent Scope 1. A method for manufacturing non-volatile memory, comprising: forming a mask layer on a substrate; forming a trench in the mask layer and the substrate; forming a tunnel in the trench A dielectric layer; forming a floating gate in the trench; removing the mask layer; forming a high-voltage doped region in the substrate on one side of the floating gate, the high-voltage doped region acting as a first A source / drain region and a control gate; and forming a second source / drain region in the substrate on the other side of the floating gate. 2. The method for manufacturing a non-volatile memory according to item 1 of the scope of patent application, further comprising: forming a gate dielectric layer on the substrate; and forming a selective gate on the other side of the floating gate, the A selection gate is located between the second source / drain region and the floating gate, and is separated from the substrate by the gate dielectric layer. 3. The method for manufacturing a non-volatile memory according to item 2 of the scope of the patent application, wherein the floating gate is a doped silicon layer; and the method further comprises: performing the floating gate after forming the floating gate in the trench. A thermal oxidation step to form a thermal oxidation layer on top of the floating gate, the shape of the thermal oxidation layer is such that the top edge of the floating gate is pointed; and 11907twf.ptd Page 14 1243450 6. Scope of patent application After removing the cover layer, a gap wall is formed on the exposed side wall of the floating gate, wherein the selection gate covers at least part of the floating gate, and the selection The gate is separated from the top of the floating gate by the thermal oxide layer, and is separated from the side wall of the floating gate by the gap wall. 4. The method for manufacturing a non-volatile memory according to item 3 of the scope of patent application, wherein the spacer comprises a 0N0 spacer. 5. The method for manufacturing a non-volatile memory according to item 4 of the scope of patent application, wherein the method for forming the ONO gap wall comprises: forming an ON gap wall on the exposed side wall of the floating gate; and on the substrate A conformal silicon oxide layer is formed, a part of the silicon oxide layer and the 0N gap wall are combined to form the 0N0 gap wall, and the other part of the silicon oxide layer serves as the gate dielectric layer of the floating gate. 6. The method for manufacturing a non-volatile memory according to item 1 of the scope of patent application, wherein the depth of the high-voltage doped region is at the bottom of the floating gate. 7. The method for manufacturing a non-volatile memory according to item 6 of the scope of patent application, wherein the high-voltage doped region further extends below a portion of the floating gate. 8. The method for manufacturing a non-volatile memory according to item 1 of the scope of patent application, wherein the floating gate system fills the trench. 9. A method for manufacturing non-volatile memory, comprising: forming a mask layer on a substrate; forming a pair of trenches in the mask layer and the substrate; forming a through dielectric layer on the surface of each trench; 11907twf.ptd Page 15 1243450 6. The scope of the patent application forms a floating gate in each ditch; removes the cover layer; forms a gap on the exposed side wall of the floating gate; between the pair of ditches A south-voltage doped region is formed in the substrate. The high-voltage doped region simultaneously serves as a common source / drain region and a control gate. A gate dielectric layer is formed on the substrate. Outside of each floating gate A selection gate is formed, the selection gate is separated from the substrate by the gate dielectric layer; and a source / drain region is formed in the substrate outside each selection gate. 10. The method for manufacturing a non-volatile memory according to item 9 of the scope of the patent application, wherein each floating gate is a doped silicon layer; and the method further comprises: forming a floating in each trench After the gate, a thermal oxidation step is performed to form a thermal oxidation layer on the top of each floating gate. The shape of the thermal oxidation layer is such that the top edge of the floating gate is pointed, and the selective gate covers at least part of the The floating gate is separated from the top of the floating gate by the thermal oxide layer, and is separated from the side wall of the floating gate by the partition wall. 11. The method for manufacturing a non-volatile memory according to item 9 of the scope of the patent application, wherein each spacer comprises a 0N0 spacer. 1 2. The method for manufacturing a non-volatile memory according to item 11 of the scope of patent application, wherein the method for forming the ONO spacer comprises: forming an ON spacer on the exposed side wall of each floating gate; and H907twf.ptd Page 16 1243450 6. The scope of the patent application forms a conformal silicon oxide layer on the substrate, part of the silicon oxide layer and the 0N gap wall combine to form the 0N0 gap wall, and the other part of the oxide The silicon layer serves as the gate dielectric layer of the floating gate. 1 3. The method for manufacturing a non-volatile memory according to item 9 of the scope of patent application, wherein the depth of the high-voltage doped region is at the bottom of the floating gate. 1 4. The method for manufacturing a non-volatile memory according to item 13 of the scope of the patent application, wherein the high-voltage doped region further extends below a portion of the floating gate. 1 5. The method for manufacturing non-volatile memory according to item 9 of the scope of patent application, wherein each floating gate system fills the corresponding trench. 16. A kind of non-volatile memory, comprising: a substrate with a trench thereon, the trench having a tunneling dielectric layer on the surface; a floating gate that fills the trench and protrudes above the trench; A high-voltage doped region in the substrate on one side of the floating gate, the high-voltage doped region acting as a first source / drain region and a control gate at the same time; and a second source / drain region, In the substrate on the other side of the floating gate, the non-volatile memory according to item 16 of the patent application scope, further comprising: a gate dielectric layer on the substrate; a selective gate , Located on the other side of the floating gate and between the floating gate and the second source / drain region, the selection gate is based on the gate dielectric layer and the 11907twf.ptd Page 17 1243450 The substrates are separated. The non-sexual memory described in item 17 of the Chinese patent application, its side wall has a doped silicon layer, and there is a known i-wall on the top of the member side, where the heat The shape of the oxide layer is the second layer, and the Qiong edge is pointed; and you make the oceanic gate layer and the floating layer covered by iiid separated by the orbital oxide wall. The top of the cabinet is separated from each other, and the non-volatile memory according to item 18 in the partition wall and the floating space = Zhong ^ ^ ^^^, which includes 20 L including an ONQ partition wall. The medium and high voltage doping \ patent deafness has enclosed the non-volatile memory described in item 16 with a depth of 21 〃 doped & and the bottom of the floating gate. In the non-volatile memory described in item 20 of the high voltage range, the surface area of the non-volatile memory extends further below a part of the floating gate. I. Non-volatile memory, including ...-Cardiac layer, there are-pairs of ditches on the base, where each-the surface of the ditch is on top, and its system fills the pair of ditches and highlights the pair of ditches i In the second middle school, a side wall of a floating gate has a gap; a doping region of the same voltage is located in the substrate between the two floating gates. And a control gate; one $ # 阁 'is located on the outside of the two floating gates, each of which has an oxide layer between the base and the base; and 11907twf.ptd page 18 1243450 6. Application scope of patent two sources / Drain region, which is located in the base outside the two selection gates, and its body recalls the hair # ut— as described in item 2 2 of the Fan Li special application, such as the Sino-Angular Oxygen Hotness has a marginal edge ΚΓ β— TIT, TSTI, and BglfJ layer, floating crystals should be added, so that the gate layer of the doped system is shaped, the floating oxygen is heated, and the floating system should be connected with the wall gap. The gates should be juxtaposed with each other, and the floating part should cover the gates on top of it. Overlay the floating gate to the gate and the zeolite layer and select and combine it with oxygen; the gate on the side of the partition ΓΠΤ is placed on its body and remembers itself _ »-= 口 发 £ # kf of the item 2 2 Li Zhuan is invited as described in its body recalling the post # tp. The size of the wall 22 and the gap between the two sides are as follows: ο1 Please include ^ 1 wall-gap 25. The bottom gate of the hidden gate I is floating. The floating gate is floating one by one. The heart is divided into 5 and 2 degrees. ^ Ffi-deep i extended U zone ^ 1 — It — mixed with " " mixed with white pressure ^ ¾ ^ ¾ ^ ul ^ \ H High 26High Hai Hai = 口 = 口中 中 11907twf.ptd Page 19