TWI242264B - Nonvolatile memories with a floating gate having an upward protrusion - Google Patents

Abstract

In a nonvolatile memory cell, the floating gate (160) has an upward protruding portion. This portion can be formed as a spacer over a sidewall of the select gate (140). The spacer can be formed from a layer (160.2) deposited after the layer (160.1) which provides a lower portion of the floating gate. Alternatively, the upward protruding portion and the lower portion can be formed from the same layers or sub-layers all of which are presented in both portions. The control gate (170) can be defined without photolithography. Other embodiments are also provided.

Description

'1242264 2 ------------------ V. Description of the invention (1) Technical field to which the invention belongs The present invention relates to a floating gate having an upward protrusion structure ( fi〇at ing gates) nonvolatile memories. In the prior art, a nonvolatile memory cell having a conductive floating gate is operated by changing or sensing a charge on the floating gate. Change or detect the charge on the floating gate by inducing voltage on the floating gate. The voltage is induced by capacitive coupling between the floating gate and other gates (eg, control gate). In order to reduce the operating voltage of non-volatile memory cells (〇peratng voltages), it is very desirable to improve the gate coupling rati0 (where the gate coupling ratio is the capacitance between the two gates). The ratio of the total capacitance plus the floating gate. The first figure shows a flash memory cell as explained in U.S. Patent No. 6,057,575, issued on May 2, 2000. The cell is formed in and over a semiconductor substrate 12 (semiconductor substrate). Sincon dioxide 130 is thermally grown on the substrate 120. A select gate 14 is formed on the silicon dioxide 130. The dioxide dioxide 150 advances on the area 12 of the substrate that is not covered by the selected gate.

1242264 V. Description of the invention (2)? Thermal growth. ΟΝΟΙ 54 (a kind of sandwich structure, which sequentially includes a layer of oxygen, fossil, silicon nitride, and silicon dioxide) is formed on the selection gate 140. Floating gates 610 are formed on dielectric layers 510 and 154 (dielectric layers). A part of the floating gate 160 is located on the selection gate 14. The 0N0 layer 164 is formed on the floating gate and the selection gate. The control gate 1 70 is formed on 0 Ν 01 6 4. The control gate is located on the floating gate 16 and the select gate 140. The source and drain regions 174 and 178 of the N + type are formed on the substrate 120. Because the floating gates 160 and the control gates 170 extend over the selected gates, the capacitance between the floating gates and the control gates will still increase without increasing the corresponding cell area. The increase in capacitance is based on two reasons. The horizontal part of the floating gate and the control gate are on the selection gate, and the vertical part is the side wall extending along the selection gate. — In order to reduce the array of memory cells and increase the packing density of the memory, it is desirable to use self-aligned processes to make memory, in which self-alignment is not very private. The effect of text page light process (phOtoHthography). The first picture shows a memory unit made by a self-aligned process, in which the floating

1242264 V. Description of the invention (3) The left and right edges of the yellow moving idler 1 60 and the control gate 1 70 are defined by β light masks. Isahaya Summary of the Invention This section summarizes some of the features of the invention. Other explanations. The invention is defined within the scope of the patent application, while invention 1 is cited by the description of the invention. In some embodiments of the present invention, the floating gate is formed from two conductive layers. The second conductor layer provides an upward protrusive structure connected to the selective gate. The second layer is formed after the first conductor layer. The upward protrusion structure covers the sidewall of the selection gate like a spacer. In other embodiments, the upward structure and the lower part of the floating gate are formed together on the same layer or the same type of multiple layers. In some embodiments of the present invention, the control gate is formed from the control gate layer. The control gate layer is deposited on the floating inter-electrode layer and the selection gate. The control gate layer protrudes above the selection gate. Prominence was developed to define the control gate in a non-yellow light self-aligned manner.

Page 7 1242264 V. Description of the invention (4) The width of the selective gate is smaller than that of the selective gate ’but the control is ::: The characteristics of the invention will be described later. The present invention is an exemplary embodiment defined in the application. This section describes examples, but the present invention is not limited to each of the examples. The present invention is not limited by special materials, process steps, or dimendons. The invention is defined in the patent application. A second figure (A) shows a cross section of a memory cell in one embodiment of the present invention. The floating gate is formed from two layers 16 ·· and 160 · 2 'η and 1 j are first formed by 16 2 · and are etched to provide a space on the sidewall of the selected gate 1 40. In some embodiments, the 60 · 2 layer is anisotropically etched without a photoresist on the body unit. θ ° We sometimes consider the combination of 160.1 layers and 160.2 layers as 160 layers. 16〇1 1242264 '--------- V. Description of the invention (5) ----- The layer and the 160. 2 layer can be regarded as a sub-layer of the 160 layer / dielectric) 164 isolates the floating gate from the control gate 70. The second figure (b) shows the cross section of the memory cell, and the dielectric layer 164 is removed to emphasize the control gate 17 and the interval 丨Overlapping ㈧ "^ 叩) D1 Heavy—Dou will increase the gate coupling ratio. If the thickness of the control gate 170 is increased or the total thickness of the structure of the selection gate 1 * 〇 at the top of the selection gate and the dielectric layer 810 is increased, the overlap ^ will increase. The gate lightening ratio does not increase with the increase in memory cells. In the second graph (A) and the second graph (B), the overlap D1 is larger than the thickness Thcg 'of the control gate 170 because of the inclined shape of the surface of the spacer 160.2. In some embodiments, the overlap D1 is at least 0.08 // m. The second image (C) is a bird's-eye view of a gate 14 and a floating gate interval ι 60 · 2. The width of the selected gate is expressed in Ws. The distance from 160.2 to the selection gate 14o is marked by Df s. As shown in the second figure (a), the right corner of the top of the interval 160.2 is directly above the left edge of the selection gate 1 4〇. So D f s is zero. In some embodiments, D f s is greater than zero. In other embodiments,

Df s is between zero and Ws. The second image (D) shows the horizontal section in the second image (A) with reference to the line 2D-2D. In this section, the distance dfs between the interval 丨 0.2 and the selection gate 140 is determined according to the thickness of the dielectric layers 1010 and 1030. The dielectric layers loio and 1 030 cover (〇ver iay) in the selection. Gate 丨 4o sidewall. Will explain later

1242264

Formation of meso-layer methods. In some embodiments, Dfs is smaller than IVs in the cross section, just like any horizontal cross section formed by a plane passing through the selection gate 14 and the interval 16.2. In one embodiment, the smallest feature size is 0.18 to " 1, that is, Ws is 0.18 // m, and Dfs is between 0 and 250 A. However, the present invention is not limited to the aforementioned sizes and relative relationships. In the second picture (A), the control gate 170 is located on a part 2 16 0 · 1 of the floating gate, but the top of the control gate 丨 7 〇 is lower than the interval 丨 6 〇 2 Tip ^ In other embodiments, the tip of the control gate 170 and the tip of the interval 160 · 2 are at the same height, or the tip of the control gate 170 is higher than the tip of the interval 1-60 · 2. Furthermore, in the second figure (A), the top of the interval 160.2 is higher than the selection question 140, but in other embodiments, the interval 16o is equal to or lower than the selection gate 14o. Focusing on the flash memory arrangement of the first picture (A) and the third picture (B), an exemplary manufacturing process will be illustrated. The third image (A) shows a bird-enemy map of some features of the memory column f. (3) The third figure (B) shows more features of the left and right figures. The "thinking unit" consists of 16 0 · 1 layer and 1 6 0. 2 layer / Yu Mo pole 160, control Gate 17 and select gate 14. The floating gate, control, and selection gates are insulated from each other and are insulated from the semiconductor substrate j 20 (eg, monocrystalline stone). Each control gate is a part of the control gate line trol gate 1 ine), wherein the control gate line is also arranged across the memory along the γ direction with the HQ: No 'control gate line. In some real yoke examples, the 'Υ direction is a column direction, and each control gate line 丨 讪 provides each

r1242264 ‘fifth, the description of the invention (7) the control gate of the memory cell on a row. The different control gate lines 7 () may or may not be tied together in the circuit. The floating gate is located at the control pole. The position of each floating gate is shown on the cross section of the third figure (A). The parent gate 140 is a seiect gate line $-part of which is also indicated by 丨 4 〇 , Select the gate line along the Y direction; arrange across the memory. The base isolation region (field isolation region) 220 (field isolation region) extends in the χ direction. In some embodiments, the x direction is a row direction or a bit line (b i 11 i ne) direction. Each 220 region is arranged across all A memory body units. Each of the selection gate lines 170 and each of the control gate lines 170 are staggered with each other in the 220 area. The following figure explains the vertical section of the intermediate structure during the memory production process, that is, the third plan (a) shows the cross-sectional plan view, which consists of χ-χ, line, Υ1-γι, line, and γ2_γ2, frame Constituted. The X-X 'line passes through the X direction between the substrate isolation regions 22o. γι_γι, the line passes through the Υ direction via the selection gate line 140. γ2-γ2, the line passes through the control gate line 170 and passes through the Υ direction. In one of the embodiments, the memory is made as explained later. The substrate isolation region 220 is formed in the p-type substrate 120 by using a shallow trench isolation technique. More specifically, as shown in the fourth figure (γbγι, cross section), a silicon dioxide layer 410 (pad oxide layer) is formed on the substrate 120 by using thermal oxidation or other techniques. Next, a silicon nitride layer (silicon nitride) 42.

Page 11 Ί242264 V. Description of the invention (8) ___ Deposited on the silicon dioxide layer 410. Next, in the silicon nitride reed process and photoresist mask (Yanshu | in yellow), the pattern is developed and the isolation trench 2 20τ is defined. ^ 7, the opening part of the Shi Xi layer 420, the shoe engraved with the Shi Xi layer 4 i0m = formed into an isolation trench 220T. Each isolation trench 22 0T is arranged across the memory in all directions. In the process of X f, the vertical edge of the siliconized silicon layer is etched to a relative groove 22〇τ with the wet rice of a certain remaining time. As shown in the fifth figure (Y1_Y1, section). After this step, the dioxygen layer 410 is also recessed relative to the trench 2201>. In the future, a thin layer of silicon dioxide is thermally grown on the edge of the exposed silicon isolation trench 22oT. Next, a high "water lgh densi" Piasma} technique is used to deposit a silicon dioxide layer 220 · 2. = The silicon oxide layer 22〇 · 2 fills the trench and covers the silicon nitride layer first. Evening layer 220 · 2 is chemically and mechanically polished.

mechanical poi lshing). The entire polishing process stops on the silicon nitride layer 42 and provides a flat surface. In the pattern below and in the third (A) and third (B) drawings, the two layers 220.1 and 22 0.2 will be represented by the same layer 22 °.

Page 12 1242264

The amount is equal to the stone oxide layer 410 and the nitride stone layer 420 centigrade sores ^ ^ _ ^ Δ 7 Degree of 娵: The dog out of the oxide stone layer 2 2 0 is higher than the base part is represented by 2 2 0 ρ. ~ In a moment (for example, a solution of scale acid), the nitrided stone 2 2 0 will not be engraved too much by the last name, and the fossil evening layer 4 2 0, as shown in the sixth figure, with a wet I insect but relatively speaking, dioxin 1-Υ 1 'Section. A dopant is implanted into the substrate 120 to protect the N-type region 604 under the memory arrangement. In addition, the impurities are implanted into the base along the memory to form the N-type area of the surface of the inscription base 120 down to the area 604 (Go to the bottle, two mountains,, upper 丨., Eighteen, no ^ (Not shown in the figure). These implants, for memory alignment, produced a completely isolated p-well 120W. The area 604 is not shown in the subsequent figures. Oxide oxide 2 2 0 is assigned to an afterglow method. (As shown in the seventh figure, section Υ1-ΥΓ) This etching method contains a component of lateral etching, so that the sidewall of the silicon dioxide 22 is etched laterally and recessed by the active areas 710 (active areas). The active area is the area on the substrate that does not include the trench. The etching method can be an isotropic wet etching method. Such an etching method can improve the capacitive coupling between the floating gate and the control gate. Also mentioned in U.S. Patent Application No. 10 / 262,785 (application dated October 1, 2002). 'Some 220P of the dioxide dioxide 220 is not completely etched, but continues on top of the substrate 1 2 0 The surface protrudes. In a 〇 · 8 # m process (minimum line

Page 13 1242264

Selective power: In exposed areas, the dioxide dioxide 130 is thermally grown to provide a dielectric material between the select transistors. In one sub ^^, the thickness of silicon dioxide 130 is 120 A. Generally, the thickness of silicon dioxide is determined according to the maximum pressure that the silicon dioxide 130 is designed to withstand the operation of the memory. As shown in the eighth figure (γ 1-γ 1, cross section), a conductive polysilicon layer 140 is formed on the entire structure by a conformai deposition process. The equiangular deposition process is, for example, low pressure chemical vapor deposition (° P). Polycrystalline stone 1 40 covers the space between 2 2 0 P of the protruding structure of the stone dioxide in the memory arrangement area. The top surface of the polycrystalline silicon is flat because the polycrystalline silicon deposited on the side walls of the protruding structure 2 20P will touch each other. Non-conformal deposition processes, whether known or to be invented, can be used. If the top surface of the polycrystalline silicon 1 40 is not flat, I believe that the top surface of the polycrystalline silicon 1 40 can use some 1242264-Drawing V. Description of the invention (11) Known manufacturing methods (such as chemical mechanical polishing, or coating layers) On the polycrystalline silicon 140, and then at the same etch rate at the same time, the silicon and the photoresist are removed until the photoresist is removed) to achieve planarization. The bottom surface of the 22 Shi Xi 140 is not flat. When the surface is up and down on the silicon dioxide protruding structure 220P. In an example, the final thickness of polycrystalline silicon 1 40 in the active region (K 06 // m.), And silicon nitride 810 is deposited on polycrystalline silicon 14, for example, by means of compressive chemical vapor deposition, and In one example, the thickness is 15,000 A. If it is high, before the silicon nitride is deposited, a pad of silicon dioxide can be formed on the polycrystalline " Shi Xi ^ 140 (not shown). In the process of etching the polysilicon i7 of the control gate, the pad silicon dioxide layer provides additional protection for the selected gate, of which 170 will be explained later in connection with the twenty-first figure. In some examples only The top surfaces of polycrystalline silicon 140 and (or) silicon nitride 8 are not flat.-A layer of photoresist is coated on the surface of the wafer (not shown). The photoresist is developed and f * selected Gate line 14Q. See the third view (A) and also the left view shown in the ninth figure. Each selected gate line 1 40 extends in the Y direction and passes through the entire memory array. Memory array pair definition The alignment deviation (111 丨 3 & 141111 ^ 111 :) of the mask of the line 140 and the isolation trench 220 is not sensitive (as shown in the fourth figure), Page 15 * 1242264 V. Explanation of the invention (12) Except for the memory arrangement boundary. Nitride stone 8 1 0 passes through the opening of the photoresist. The photoresist is removed and the polycrystalline silicon exposed by nitriding cutting 8 1 0 Broken 1 40 is also engraved by money. The key point is to select the gate line 140. (In another embodiment, it is used to define the process of nitride nitride 810, photoresist etching of polycrystalline silicon 1 40 All of them are removed.) As shown in the tenth figure (X-X 'section), the structure is oxidized to grow one, and silicon 1010 is on the sidewall of the select gate line 140. Then, + ^ on, one Oxygen I without a mask over the memory array, deposit a thin, isotropic fossil evening layer 1030 and make it anisotropic. After that, a gap has been formed. ^ Includes ^ Select gate line 1 40. The silicon nitride 81 〇 and the side wall dioxide} are located on the side wall of the structure. The silicon nitride spacer is formed in H. Tuari ^ Xi λα 〇 0, Patent 6, 3 55, 524 (Announcement on March 12, 2002 & date. There is a US description, and the present invention is incorporated by reference. The silicon etching removes silicon dioxide (as in A picture, X-X, cross-section to achieve the desired thickness, for example, a general (b 1 anket) exposed part of the dioxide 1 30. The dioxide dioxide is grown on the substrate 12 by thermal oxidation. Such as 90 A 〇

: 1242264 V. Description of the invention (13) ^ ^ The top surface of layer 1 is at least equal to the top surface of silicon nitride 8 1 0. In particular, · 16 1 · · crystalline silicon contains a region 1 6 0 T between the selection gates 1 4 0. The region 16 0 D is at least as high as the top surface of the silicon nitride 8 1 0. The 160 · 1 layer is planarized by a chemical mechanical polishing method using a nitride layer of 810 as a stop layer or other processes. See figure twelve (X-X, section). The top surface of the polycrystalline stone Xi 16 1 · 1 becomes quite flat as the top surface of the nitride stone Xi 8 1 0. The chemical mechanical polishing process and the use of slurry are known to allow to avoid dishing on the top surface of the polycrystalline stone layer.钃 Polycrystalline silicon 16 0 · 1 is etched. The 16 0 · 1 layer is not masked in the memory arrangement area. #Thirteenth figure (A) (X-X, section) and thirteenth figure (B) (Y2-Y2 'section). When the silicon dioxide 220 in the trench becomes exposed, the narration is terminated. Implement an appropriate excessive engraving (〇 v r e t c h) to completely remove polycrystalline silicon 16 0 · 1 on the top surface of silicon dioxide 2 2 0. In some embodiments, the polysilicon 160 · 1 has a median thickness between 80 0 A and 1 200 A. Optionally, the silicon dioxide 220 is etched on a time basis so that the top surface of the monolithic oxide 2 2 0 is retracted below the surface of the polycrystalline silicon 16 0 · 1. See figure 14 (Y2-Y2, section). Such etching improves the capacitive coupling between the floating gate and the control gate. See the aforementioned U.S. Patent 6,355,524. In the embodiment of the fourteenth figure, silicon dioxide 2 2 0 continues to protrude on the top surface of the substrate 1 2 0. As shown in 220P, there is about 0.06 // m to 0.10 #

Page 17 1242264 V. Description of the invention (14) m. In other embodiments, the silicon dioxide 2 2 0 does not protrude on the substrate after etching. A second polycrystalline silicon 16 0 · 2 (fifteenth figure) is deposited on the structure. This conductive layer is doped during the deposition process or after the deposition, like the conductive type of the 1601 layer. Polycrystalline silicon 1 60 · 2 is isotropic. An exemplary deposition method is L P C V D. An exemplary thickness is 12 00 A. In the case where there is no mask on the memory array, the polycrystalline silicon 6 2 · 2 is anisotropically etched to form a polycrystalline silicon space 160.2 A on the sidewall of the dielectric layer 1 30. See Figure 16 (Α) (χ_χ, section) and Figure 16 (B) (macro view.). The horizontal etch rate may or may not be equal to zero, but it is less than the vertical etch rate. The end point of the etching is the exit of the silicon oxide 810 and / or the silicon dioxide 220 in the trench. In order to combine the aforementioned etching of the silicon oxide 220 associated with the fourteenth figure (the top surface of the silicon dioxide 22o is returned to the polycrystalline silicon 16 = etching below the surface), the polycrystalline silicon 160 may also be formed At an interval of 160 · 2B (sixteenth & brother ten-picture ⑻) on the side wall of the polycrystalline silicon 1 60 0 · 1 near the active area of the sin, column 0 comes up with a light-shielding shield cover! 5 27 pictures ( A) Top view) Formed in the memory bank: at m: ° .2. Figure 17 shows the position of the relative prime mask at 150 °. The mask is patterned with photoresist features. Each has a photoresistor 15 of this characteristic. 〇 extends on the active area of the trench 220. This 1242264 V. Description of the invention (15) shows the position of the future source line region 178 (source line region) and the two control gate lines between the adjacent selection gate lines 140. The edge of the mask extending in the χ direction is placed on the groove 2 2 0 T. The edge of the mask extending in the γ direction can be placed anywhere above the selection gate line 1 40. Therefore, all the edges of the mask openings in the memory array region are placed above the selection gate line 140 and / or the trench 220T. 'In the area exposed by the photoresist 1500, the polycrystalline layers 602 · 2 and wo ·} were etched away. The structure of the result is shown in Figure 17 (B). Polycrystalline silicon 610 · i and 160 · 2 are removed from the adjacent select gate lines 140 on the future bit line area (bitHne) region 174. Silicon oxide 150 becomes exposed in these areas. In the future source line area 178 and the area controlling the position of the gate line 170, polycrystalline silicon 160.1 is not etched. Part of the polysilicon spacer 16 2A was removed from the isolation trench 22 0T. The remaining portions of the interval 60 · 2A are each formed so as to protrude above the floating gate for one memory cell on the side wall of the gate line 140. … Here the tenth photoresist 1 500 covers the interval ⑽

Response interval If the mask is shifted from 1500 to the γ direction, the interval 丨 2B will not be compatible as long as they are protected by the mask. The interval 160.2B will be toward the center of the d. The length in the direction 160 · 2 ^ γ of 1 compartment will remain unchanged. It is believed that the offset of 160. 2B will not have a significant effect on the electrical properties of the memory cell.

Page 19 1242264 V. Description of the Invention (16) Impact. The following illustration of the interval 160 · 2A will simply be labeled 160 · 2. The ONO layer 164 (eighteenth figure, X-X, section) is formed on the structure. A control gate polycrystalline silicon layer 170 is deposited on ONI 64 and is intermixed during or after deposition. The top surface of polycrystalline silicon 1 70 is not flat. The i 70 layer has a protruding portion 1 + 70 · 1 on each selection gate line 14o. The protruding part 17 · 1 will be used to define the control and floating gates without additional reliance on the yellow light alignment step. As shown in the eighteenth figure, caves 17oc are formed in the 170th floor between the protruding portions 170 · 1. As shown in Figure 19 (χ — χ, profile), these caves are filled with a material 1710. In one embodiment, the material 1710 is formed on the polycrystalline silicon 170 and the two-gas over-exposed polycrystalline silicon 170 which has a flat top surface.

Polycrystalline silicon 1 70 is engraved without masking relative to selective engraving (see Figure 20 (χ-X 'section)) $ 段 #lithopolysilicone engraved with edge damage 170 ″, and in the structure The top face creates a cave 1 8 1 0. Compared to silicon oxide ^ 〇, here ^ In these holes, polycrystalline silicon 17Mi is recessed. In the only example of the tenth figure of each ΠΜΠ 1β / 1 „〇 Shimu Gedi, the etching exposes 0 N 0 1 6 4 ′ and following the performance-paragraph Japan pH # rsi r π, ^ 奴Daytime return (recess) at Ονο 164

Page 20 '1242264

Polycrystalline silicon top surface underneath. However, this etching step is not necessary. The polycrystalline stone engraving can be stopped before the exposure of ONO 1 64, or the etching can be stopped when the ONO layer becomes exposed. If 〇Νι64 is exposed, on the side of the selected gate 140, the width of the polycrystalline silicon in the cave 1810 and the width of the 70 will be defined by the self-alignment method that will be explained next. width. In some embodiments, the minimum thickness of polycrystalline silicon 170 (at the bottom of cave 1810) is 0.18 // m, and the width ¥ 1 is less than 018 / zm. In the twentieth figure, the top surface of the polycrystalline silicon 170 is trapped in the cave 1810. In other embodiments, the polycrystalline silicon 170 has a flat top surface throughout the memory arrangement area. A material for protection is deposited in the cave 1810 to protect the polycrystalline silicon 170 near the selected gate 1440. In one embodiment, the material is a nitrided stone 190 (see the twenty-first figure 'X-X' section). Nitride 190 was deposited on the structure and polished with CMP until silicon oxide 1710 was exposed in the memory array area. See Figure 22 (A) (χ-X, section). Silicon nitride 1910 remains in the cave 1 8 1 0. In addition to CMP 'II Fossil 1910 can be processed (pr〇cesse (j) to deposit a layer of material with a flat top surface (not shown) and etch the material and silicon nitride at the same etch rate until silicon oxide 丨7 丨 〇 is exposed. This material can be a photoresist. This material can be removed after the silicon nitride is etched.

1242264 V. Description of the invention (18) Antireflection coating layer (ARC) 2010 ′ As shown in FIG. 22 (A), it is flowed on the silicon nitride 1910 and baked. After this step, the structure has a flat top surface. The wafer is coated with a photoresist layer 2020. The photoresist is patterned to protect a portion of the nitride nitride 190 on one side of each of the select gate lines 1400. The twenty-second figure (B) (top view) shows the position of the mask 2020 corresponding to the feature shown in the third figure (A). The photoresist 2020 is located at the future position of the control gate line 丨 70 'and exposes these areas between the adjacent selection gate lines 丨 4 0, and the control gate in the adjacent selection gate line 140 Extremely polycrystalline silicon 170 will be removed. The longitudinal edge of the mask 2 0 2 0 can be placed at any position above the selection gate line 丨 4 〇. The silicon nitride 1910 and anti-reflective coating (ARC) 2010 exposed by the photoresist 2020 were removed. The remainder of the photoresist 2020 and the anti-reflective coating layer (ARC) 201 is then removed. The completed memory arrangement is shown in XX'3 (X-X 'section). At the bottom of the cave 1810, a silicon nitride 1910 protects a portion of the polycrystalline silicon 170 having a width W1 (Figure 20 and Figure 23). The silicon oxide 1710 is removed by blanket etching. The completed structure is shown in Figure 24 (χ-χ, section). 70. Silicon nitride 1910 is used as a mask, and polycrystalline silicon 17 is charged in the arrangement area.

1242264 V. Description of the Invention (19)-Carved. Saving money is selective to the oxide of oxid, so it will stop on ΟΝΟ 164. With silicon nitride 1 91 0 as a mask, ONO 1 64 and polycrystalline silicon 60.1 are etched. Layers 164 and 160.1 are completely removed from areas not covered by silicon nitride 1910. See figure 26 (X-X, section). The silicon nitride layers 1910, 810, 1 030, and silicon oxide 150 were partially removed during the etching of ON0 164. The floating gate 160 and the control gate line 170 are the result of completely defining this step, and look like the third picture (A) and the third picture (B). The width of the top surface of the control gate line 1 70 is as defined above and is associated with W1 of the twenty figures. The wafer was coated with a photoresist 2620 (Figure 27 (A), χ — χ, cross section, and Figure 27 (B) top view of an arrangement that does not include a dielectric layer). The photoresist is patterned to expose the source line 178. Each source line 78 traverses the memory arrangement between two adjacent control gate lines 1 70, and a source or sink is provided to each cell in two columns with two control gate lines attached. The alignment of the mask 2620 is not critical because the left and right edges of the mask opening can be placed anywhere on the selection gate line 丨 40 or the control gate line 丨. In the area exposed by the mask 2620 (for example, the area of the source line 178), the dioxide 220 is removed from the trench 220T. Remove the master on the source line at this moment ^

Page 23 • 1242264 V. Description of the invention (20) Silicon oxide in the area 15 0. Then, perform source line implantation (N +) with the same mask. In some embodiments, this is a high-energy, high-implantation concentration, or it may be a low-energy, low-concentration, high-angle implant (for example, the angle can be from 10 to 30 degrees) to reach 0 · 1 // m to 〇 2 // m source line diffusion depth. In another embodiment, a mask 2 6 2 0 is formed, and then high-energy N + implantation is performed before the oxide oxide 2 2 0 is etched away, and then the silicon oxide 2 2 is performed with the same mask. 0 is etched away from the trench, followed by other, low-energy N-type implants with the same mask. The first (high-energy) implant is at least partially obstructed in the trench by oxidation seconds 2 2 0 to avoid a short circuit between the source line 178 and the N-type isolation region 604 (sixth figure). See the aforementioned U.S. Patent No. 6,355,524. Photoresist 2620 is removed. A thin silicon dioxide layer 2904 (Figure 28 (A), cross-section) is formed by a suitable technique (for example, TEOS, HTO, RT), and on a substrate. Examples of silicon oxide on the surface of silicon 2 〇 4 the thickness of 2000 Å to 300 Å. If the oxidized stone 2900 4 is deposited by thermal deposition method, thermal oxidation ′ rapid thermal oxidation), The silicon oxide on the surface of the disordered silicon will be very thin. The non-fossilized fossil evening layer 2 910 was deposited and spun in an unexpected manner (not shown). Second etch to form sidewall spacers on the gates of the surrounding transistors (not shown). Spaces 2910 are also formed in the memory bank to protect the substrate 120 as -lang endpoints. One N + Plant Two Two

Page 24 1242264 V. Description of the invention (21) Create an LDD (lightly dopant drain) structure for the peripheral transistor (not shown), and increase the NMOS transistor gate with the impurity concentration in the periphery. A pole and source line region 178 and a mixed bit line region 174. The twenty-eighth figure (B) is a top view of the completed memory arrangement structure. The floating gates, control gates and selection gates and the sitting silicon nitride layer etc. mask this implantation 'so that no additional masking is required in this memory arrangement. Memory fabrication can be accomplished using known techniques. In the example in Figure 29, metal inter-level dielectrics 3204 are deposited on the wafer. Contact openings are etched into the dielectric layers 3204, 2904, and 150 to expose the bit line regions 174. A conductor layer 3210 is deposited and patterned to form bit lines that contact the bit line regions 74. If layers 3 2 0 4, 2 9 0 4 and 1 50 are formed from silicon dioxide, the alignment of the mask (not shown) used to define the contact openings is not critical because the gate 1 4 0 is selected from nitrogen The silicon layer is protected by 910 and 1030. Fig. 30 is a circuit diagram of a memory arrangement of an embodiment, which is a NOR type arrangement, which is explained in the aforementioned U.S. Patent No. 6,355,524. Each bit line 32 1 0 is shared by the two rows of the memory arrangement 32 1 0. A memory cell 3 2 1 0 is injected with hot electrons from the channel region of the cell (the P-type region within the cell's floating gate and the substrate 1 2 0 under the selected gate) to the floating gate 160 (hot electron injection). The memory cell is generated by a floating gate 1 6 0

Page 25: 1242264 V. Description of the invention (22) FN tunneling to source line area 178 or channel area (Fowler-Nordheim

Tunnel ing). The cell is read by the current induced in the corresponding bit line area 174. The selection gate 14 is driven to a suitable high voltage during reading, programming, and possible erasing operations to select the corresponding memory row. Additional details on the memory fabrication process are in another U.S. patent application by the inventor γ i D i ng (Receiving No .: M-1 2 9 0 2)

The contents disclosed in "NONVOLATILE MEMORIES AND METHODS OF FABRICATION" are incorporated herein by reference. In the thirty-first figure, a floating gate is fabricated by using a single polycrystalline silicon layer. This wafer is transmitted through the stage shown in FIG. Next, polycrystalline silicon 160 is deposited and moderately infiltrated with impurities. An exemplary polysilicon 160 has a thickness of 1600A. The polycrystalline silicon 160 includes a portion 160C between the protruding portions 220P of the substrate isolation region 220. This section 160C has a flat top surface. This step can be achieved by isotropic deposition of 60 layers (for example: LPCVD) to a suitable thickness, so that a portion of the 160 layer on the side wall of the protruding portion 22p can be deposited during the deposition process. Meet. Polycrystalline stone 160 is anisotropically etched to form a dielectric polysilicon space on the sidewall of the dielectric without masking on the memory array. Thirteen pictures). The end point of the etching is when the silicon nitride is exposed and / or the oxide in the trench is exposed to 2 2 0. Polycrystalline stone is etched by the base to isolate the oxide stone

'1242264 V. Description of the invention (23) Top surface of 220. The polycrystalline silicon portion 16〇 (; is turned toward the top surface and becomes the same as the top surface of the silicon oxide 2 2 0

Under etch, the -plane of the part. The mask 1500 is removed as shown in Fig. 17 (a). The final structure can be as described in the third remaining manufacturing steps. Polysilicon intervals are shown in Figure 16 and 12. 2 The fourteenth figure shows the embodiment outside. This structure is like the third; the other 160 in the manufacturing stage is a thin layer. Therefore, the io6c portion * is only bismuth, but the top surface of the polycrystalline silicon falls on the top surface of the protruding portion 220P, and the 0 surface is not flat. The sexual). As shown in the thirty-second figure, the non-isotropic downward part 10C is formed on the structure of the thirty-first figure in the isotropic direction, and can be omitted. The mask portion was etched to make the thirtyth: the exposed portion of polycrystalline silicon 160, the surface undulation of each structure. Since the polycrystalline stone is walking on the side wall of the protruding portion 220P. This twenty-two: pole 160 one up-down (Figure 35). More advantageously, the floating pole gives a large surface area repeating 170 or more, so the capacitive coupling of the pole facing the control gate is increased. 'Between the moving gate and the control gate Figure X-Γ Figure 6 shows the memory side of the illustrated Figure 5

1242264

The present invention is not limited to any particular technology for reading, deleting or stylizing 'or to a memory array of the NOR type, j, or is not limited to a memory array architecture or a manufacturing method. For example, the mask 1500 (seventeenth figure \;) \ may contain many long bars extending in one direction through the entire memory arrangement, as shown in the thirty-seventh figure. The source line can be formed by a layer lying on the substrate 120 and contacting the source line base region 178, and the source line does not need to pass through a trench for isolation. Similarly, the 'substrate isolation region' is isolated at the source line 178. The dielectric 220 does not need to be etched from inside the trench, before the source line is infiltrated with impurities. Substrate isolation can be formed using the method described in U.S. Patent Application No. 10 / 266,378, issued by Chia-Shun Hsiao on October 7, 2002, incorporated by reference in the present invention. . Shallow trench isolation can be replaced by LOCOS or other isolation methods known or to be invented. The invention is applied to a multi-level memory unit (a unit that can store multiple bits of information). Other embodiments or variations are within the scope of the present invention and are defined within the scope of patent applications.

P.28 • 1242264 Brief description of the drawings Brief description of the drawings The first diagram shows a cross section of a memory cell of the prior art. The second diagram (A) and the second diagram (B) show one implementation of the present invention. Example of a memory cell section. The second image (C) is a top view of some features in the second image (A). The second image (D) shows a horizontal section of some features in the second image (A). The third figure (A) is a bird's-eye view of one of the structures in the memory fabrication process of one embodiment of the invention. The third picture (B) is a macro view of the memory during the manufacturing process in the third picture (A). O The fourth to eighth pictures show the third picture (A) and the third picture during the manufacturing process. The cross section of the memory in the third figure (B). The ninth figure is a macro view of the memory in the third figure (A) and the third figure (B) during the manufacturing process.

Page 1242264 Schematic description of the tenth figure, eleven, twelve, thirteen (A), thirteen (B), fourteen, fifteen, sixteen (A) shows the third figure in the manufacturing process (A) and the cross section of the memory in the third figure (B). The sixteenth figure (B) is a macro view of the memory in the third figure (A) and the third figure (B) during the manufacturing process. Figure 17 (A) is the third figure (A) and the third figure (B) during the manufacturing process

Aerial view of memory. The seventeenth figure (B) is a macro view of the memory in the third figure (A) and the third figure (B) during the manufacturing process. The eighteenth to twenty-first and twenty-second (A) figures show the cross sections of the memory in the third (A) and the third (B) during the manufacturing process.

Figure 22 (B) is a bird's-eye view of the memory in Figures 3 (A) and 3 (B) during the manufacturing process. The twenty-third to twenty-sixth figures, and the twenty-seventh figure (A) show the cross sections of the memory in the third figure (A) and the third figure (B) during the manufacturing process. The twenty-seventh figure (B) is the third figure (A) and the third figure in the manufacturing process

Page 30 Ί242264 A brief bird's-eye view of the memory in (B). The twenty-eighth figure (A) shows a cross section of the memory in the third figure (A) and the third figure (B) during the manufacturing process. The twenty-eighth figure (B) is a bird's-eye view of the memory in the third figure (A) and the third figure (B) during the manufacturing process.

The twenty-ninth figure shows a cross section of the memory in the third figure (A) and the third figure (B) during the manufacturing process. Figure 30 is a circuit diagram of the memory in Figures 3 (A) and 3 (B). Figures 31 to 35 are the manufacturing process of the embodiment of the present invention. Macro view of the memory.

The thirty-sixth figure is a scraped surface of the memory during the manufacturing process of the embodiment of the present invention. Figures 37 and 38 are bird's-eye views of the memory arrangement (ar r ay) in the manufacturing process of the embodiment of the present invention.

Page 31! 1242264 Simple illustration of the diagram Explanation of the symbols of the diagram First picture

120: semiconductor substrate 130 silicon dioxide 120: on substrate 1 40: selection gate 1 50: silicon dioxide 154: ONO layer 1 6 0: floating gate 150, 154: dielectric layer 164 0Ν0 layer 17 0: control gate 174: Ν + source region 178: Ν + drain region

Figures 2 to 38 Figures 16 0 .1, 16 0. 2: Two layers of floating gates 1 4 0: Selection of gates 160: Combination of 160.1 layers and 160.2 layers 1 6 4: Introduction Electrical layer 17 0: Control gate D1: Overlay 810: Dielectric layer

Page 32 1242264 Brief description of the drawing 1 6 0 2: Floating gate interval Ws: Select gate width D fs: Interval 16 (K 2 to select gate 1 4 0 Distance 1010, 1 030: Dielectric Layer 160 floating gate 120 semiconductor substrate 220 substrate isolation area (field isolation area) 170 control gate line 120 mixed P-type substrate 410 silicon dioxide layer (pad oxide layer) 420 silicon nitride layer 220T: isolation trench 220.1 :-Thin layer of SiO 2 layer 220.2:-Layer of SiO 2 layer 2 2 0P: The protrusion of SiO 2 220 is higher than that of the base portion 604: N-type area 120W: P-type well area 710: Active area 1 3 0: Silicon dioxide 14 0: Polycrystalline silicon layer 8 1 0: Silicon nitride 1 0 1 0: Silicon dioxide 1 0 3 0: Silicon nitride layer 1 50: Silicon dioxide

1242264 Schematic description

Page 34 160. 2 • Polycrystalline fragment 1 60. 2Α: Polycrystalline silicon space 160 · 1: Polycrystalline silicon 160.2B: Space 1500: Photoresist mask 178: Source line area 174: Bit line area 170C :: Cave 164: ΟΝΟ 1810 Cave 2010 Anti-reflective coating 1910 Silicon nitride 2020 Photoresist layer 262 0 Photoresist (mask) 3204 Interlayer dielectric

Claims (1)

1242264 Case No. 93103313 Adjusted month, revised six, applied for patent scope 1. A method of manufacturing an integrated circuit including a non-volatile memory, the method includes: forming a first structure on a semiconductor substrate, the The first structure includes: a gate of a first conductor, the gate of the first conductor belonging to a non-volatile memory unit; and a first interlayer forming a layer of memory and an upper portion on the first side wall forming a The first layer is formed on the element, the element is removed; the G2 is not too high, the dielectric is on the gate of the first conductor; ('' FG layer π) to provide a conductive floating gate to the non-volatile Unit, wherein the floating gate of the conductor includes a second portion protruding from the first portion, the second portion protruding above is formed on a dielectric, and the first dielectric is at least on a side wall, and A gate of the first conductor; two dielectrics on the FG layer; ('' G2 layer π) providing a gate of a second conductor to the non-conductor on the first structure, the FG layer, and the second dielectric Volatile memory monolayer So that the top of the gate of the second conductor becomes the top of the floating gate of the conductor. 2. The method as described in item 1 of the scope of patent application, wherein the FG layer includes a first layer and a second layer, the second layer is formed after the first layer, and the floating gate of the conductor The first part of the pole is formed by the first layer, and the second part of the conductor's floating gate is formed by the second layer. Page 35 1242264 Case number 93103313 6. The scope of patent application 3. The method in item i of the scope of patent application, wherein the ^ layer is composed of several sub-layers, and the one or more sub-layers are represented in the = floating gate Part one and part two. 4. The method as described in item 3 of the scope of patent application, wherein the step of forming the F comprises: J v forming the FG layer on the first structure; and then proceeding without a mask over the memory unit The anisotropic money engraved the FG layer to remove the FG layer from the top of the first structure, but left the FG layer on the first dielectric on the sidewall of the first structure. 5. As in the method of claim 4, the method further includes forming a plurality of substrate isolation regions, each of the plurality of substrate isolation regions being a dielectric region, and a portion of the dielectric region is prominent. On a semiconductor substrate, where the formation of the FG layer on the first structure causes the thickness of the FG layer between the substrate isolation regions adjacent to the first structure to be greater than the FG layer above the substrate isolation region The thickness of the FG layer will cause the FG layer to be removed from at least part of the substrate isolation region and the first structure but not between the substrate isolation region adjacent to the first structure. . 6. The method as described in item 1 of the patent application, wherein the memory unit is one of the plurality of memory units, and the method further includes an etching of the FG layer to remove the interposer. Different memory Page 36 1242264 Case No. 93103313 Amendment 6. The scope of the patent application The part of the FG layer between the units.体 意 记性 发 containing the electric circuit volume of 1010 kinds of recipes. 包包 法 方 应, Polar structure: the structure of the inclusions in the gate junction, the first base into the first base, The half-one is in the seat structure-the body guide that belongs to the pole gate-the body that has the ancient mouth, ^ one # the body guide of the pole gate 1 the first and second in the mass medium and the quality; The single element of the elementary body recalls the first, the first, the first, and the first, and the one and the one are written down, and the one is formed into a wall shape, a layer shape, and a polar shape. The first and the first layer of the gate, the first floating floating integrated package containing a layer for FG to mention, the middle 1 its layer G MF yuan C single layer body a first pole: the gate contains the moving package floating The FG of the step body is used for the formation of the shape, and the next floating body in the layer is used to guide the body. • The structure is superimposed on one of the wall structures. Eroding the quality of the protrusion and the structure of the junction part, the second layer of the electric media This is the second order of the element and the hidden layer of the layer. The first is the first to the electric body mediated by the gate. Sudden step # layer of the second layer of the second time the second of the money in the middle of the moment ’Single body Fang Yi persecution / Θ = the item in the mask Page 37 1242264 Case No. 93103313 Amendment VI. Patent application scope 9. The method in item 7 of the patent application scope, wherein the memory unit is one of a plurality of the memory units, and the method further includes An etching of the second layer to remove portions of the second layer between different memory cells. 10. The method as described in item 7 of the scope of patent application, wherein the top of the gate of the second conductor is not higher than the top of the second portion of the floating gate of the conductor. 11. A method of manufacturing an integrated circuit including a non-volatile memory, the method comprising: a first dielectric on a gate of the first conductor;) to provide a floating gate of the conductor to the non-volatile, the The floating gate of the conductor includes a first portion and a second portion. The upwardly protruding second portion is formed on the first dielectric, and the first dielectric is at least at the gate of the first conductor. On a sidewall; forming a first structure on a semiconductor substrate, the first structure comprising: a gate of a first conductor, the gate of the first conductor belonging to a non-volatile memory unit; and a first interface An electric substance, which forms a layer ("FG layer") of the memory unit, and a first dielectric layer that protrudes upward forms a second dielectric layer (nG2 layer), which is provided on the FG layer; ) To the first structure, the FG layer, and the gate of the second-to-second conductor to the memory unit, the Page 38Ί242264 6. The scope of patent application G2 layer has a P1 part, which P1 part protrudes above the first structure; forming an L1 layer above the G 2 layer, so that the protruding part belonging to the G 2 layer The P1 portion is exposed and cannot be completely covered by the L1 layer>, the G2 layer is partially removed, and the removing step is selective to the L1 layer to form a hole in the P1 portion; at least An L2 layer is formed in the cavity; at least the L1 layer and a part of the G2 layer are removed, and the removing step is selective to the L2 layer. 12. A method of manufacturing an integrated circuit including a non-volatile memory, and the non-volatile memory includes a non-volatile memory unit, the method comprising: forming one or more substrate isolation regions on a semiconductor substrate Forming one or more first structures on the semiconductor substrate, each of the first structures comprising: a conductor line G 1, wherein each of the memory cells includes a gate of a first conductor, the The gate of the first conductor includes a portion of the conductor's line G1; and a first dielectric on the conductor's line G1; forming a layer (FG layer) to provide a floating gate of the conductor to each of the non- A volatile memory unit, wherein each of the floating gates of the conductor includes a first portion and a second portion protruding upward, the second portion protruding upward is formed on the first dielectric and Covering at least one side wall of line G1 of the conductor; Page 39 1242264 Amendment ----- Tiger 9310% _ Year 6 、 Scope of patent application _ ^ Open p by-or multiple masks to graphically represent the unit to shift the same memory unit The layered portion in between, where all the one or more shadows in the _memory-early 7C area are located on the conductor's line G1 and / or the substrate isolation area. I 彖 is bit 1? The method described in item 12 of the patent scope, which further includes forming a second dielectric on the FG layer; forming a G2 layer on the first society; On, ue g. The structure, the FG layer, and the second dielectric are removed from the G2 layer and the FG layer, but the floating gate of the conductor is premature. . Use a trowel to form the gates of the two conductors and the method of item 14. The first layer and the second layer, such as the scope of the application for patent No. 19 TS a, wherein the "layer contains a. # + + Ί Two layers, and the second layer is formed after the first layer, in which the conductor of the conductor is floating, ^ .. ^ ^ A the first part of the moving gate is made by the first layer Is formed, and the floating layer p of the conductor is Ar? V, the second layer is formed. The upwardly protruding second part of the moving closed electrode is the method in item 12 of the scope of patent application of 152, where the ⑺ The layer is composed of one or more sub-layers, which is 4 ^ of the 4 channels of 士士 a, and all the sub-layers are part of the 表现 of the conductor / manual gate; ^ # 丄 ν 丨 cut and The second part that protrudes upwards. Contains 16. A integrated circuit, including page 40, 1242264, case number 93103313, Λ_η. Amendment 6. Patent application scope: semi-conductor-first-first-body substrate dielectric region in the semiconducting conductor The gate in which the gate belongs to a non-volatile region The non-volatile floating-conductor moving gate belongs to the non-volatile containing a first part and a flat section, and is divided equally with the gate of a second conductor from the gate of a second conductor Seated but not seated on the first dielectric material to gate the second electrode and the gate of the second conductor, the second memory, the semiconductor memory, and the second memory The upper protruding surface, the pole, the distance is small outside the floating pole to the body of the conductor 0 body base dielectric body unit base element; the second plane of the dielectric body unit projects upward from the first Reduce the moving gate of the conductive gate, and move it above the area; above the area of the first conductor electrical region, the part passes over the floating floating gate that leads the conductor. On the conductor, the second part of the second part protruding upwards and the width of the gate of the first body; part of the floating gate on any body of water; the gate of the first conductor is isolated from the first The gate of the conductor is apart. The integrated circuit of item 6, wherein, from a top view, the distance between the upwardly protruding second portion and the gate of the first conductor is smaller than the width of the gate of the first conductor. The integrated circuit of item 16, wherein the second portion protruding upward is located on a portion of the gate of the first conductor. Page 41 1242264 _g No. 93103313 VI. Application scope of patent 19. For the integrated circuit in item 16 of the scope of application for patent, the second part out of ^ is not one of the gates of the first conductor 20. For example, for the integrated circuit in item 16 of the scope of patent application, the gate of the first portion protruding upward and the gate of the second conductor are at least as thick as the thickness of the gate of the first conductor. 21. As for the integrated circuit in item 16 of the scope of the patent application, the gate of the second part protruding upward and the gate of the second conductor are rarely 0. 0 8 // Π1. 22. If the integrated circuit in item 16 of the scope of patent application, the top of the gate of the body is not higher than the second projecting upward 2 3 · If the integrated circuit in item 16 of the scope of patent application, The top of the gate of the body is lower than the upwardly protruding second eighty-two-piece integrated circuit, including: a semiconductor substrate; a first dielectric region on the semiconductor substrate; In the middle of an overlapping medium, the middle medium overlaps, and the overlap reaches the top of the second derivative. In the top of the second guide. 1242264 Case No. 93103313 Amendment VI. Patent application scope-a gate of a first conductor is above the first dielectric region, the gate of the first conductor belongs to a non-volatile memory unit; a second dielectric The second dielectric region belongs to the non-volatile memory cell; a conductive floating gate is above the second dielectric region; the conductive floating gate belongs to the non-volatile memory cell; A memory unit; the gate of a second conductor is located on a portion of the floating gate to the conductor, wherein the top of the gate of the second conductor is not higher than the top of the conductive floating gate; A dielectric to isolate the floating gate of the conductor from the gate of the first conductor and the gate of the second conductor, and separate the gate of the first conductor from the gate of the second conductor Beyond the pole. 25. The integrated circuit as described in claim 24, wherein the top of the gate of the second conductor is lower than the top of the conductive floating gate. 26. An integrated circuit comprising: a semiconductor substrate; a first structure located on the semiconductor substrate, the first structure comprising: a gate of a first conductor, the gate of the first conductor being a non-volatile Memory cell; and a first dielectric on the sidewall of the gate of the first conductor; a conductive floating gate over a second dielectric region, the conductive Floating Page 43 r 1242264-: 6. Scope of patent application The moving gate belongs to the non-volatile memory unit. The conductive floating gate package includes an upwardly protruding structure, which is formed as if in the first A space on a side wall of the dielectric; the gate of a second conductor is located at least in part of the floating gate of the conductor but not in the first conductive interrogating electrode, wherein the conductive floating gate The upwardly protruding structure of the pole is interposed between the gate of the first conductor and the gate of the second conductor; a dielectric to isolate the conductive floating gate from the gate of the second conductor. Included bottom substrate guides should be in the region of the body, and the substrates in the substrate are semi-conducting. The first region is the first region. The first element is f'e. 1 mouth g- ^ \ B 口-3 Mediator-Recalling the integration of this nature in the development of & c »e 一 极 # in the derivation of the first-dimension interregional dielectric, the second base of the dielectric, and the voxel-guided single-half body The memory emits electricity in the region of the recording, but does not pass through the two poles of the first domain, which is a floating bag. The switch should be driven by the approaching, the neighboring power on the region of the structure to create the structure of the region, the elementary electricity outburst on the single mediator of the second memory to the record of this nature, the generator pole kr spoon & The upper electrode guide that moves the floating gate is moved one by one, and the electric gate that contains conductance is not only at the edge-, the edge of the floating edge guides the first part of the floating body of the one pole gate. A floating polar body gate guides the body in the float, and the landing body on which the gate is located is one to one less than the landing body on which the gate is located. "1242264" on page 44 VI. The upwardly protruding structure of the patent application range pole is between the gate of the first conductor and the gate of the second conductor; a dielectric to float the gate of the conductor The gate isolates the gate of the first conductor from the gate of the second conductor, and separates the gate of the first conductor from the gate of the second conductor. Page 45