TWI242267B - Packaging for semiconductor and the manufacturing method - Google Patents

Abstract

This invention provides a common via hole with resin encapsulated semiconductor package body. The packaging for semiconductor and the manufacturing method provide high reliability of connecting via hole and good yield. The via hole for connecting both surface of a double sided substrate (1) with copper foils is to be shared among the circuit pattern of a semiconductor package body and the opening is made to an elongated hole shape, which is followed by dicing the semiconductor package body from half cutting line. Besides, the via hole is undergoing, after an etching treatment of the copper foil layer (10), laser processing of the round holes to produce the elongated hole from connecting a plurality of round holes, by removing substrate material (11) at the opening position.

Description

1242267 Case No. 901171 卯

V. Description of the invention (0 [Field of the invention] The present invention relates to forming a plurality of semiconducting circuit patterns on a double-sided copper box substrate into a matrix shape, and sealing the entire substrate with a crystal at a predetermined position on a chip. ， Slicing and '== ΐPackage. I !? ΐ It is manufactured by arranging via holes on the end side of the semiconductor package for conducting between the two sides of the two copper substrates. Semiconductor package and its manufacturing method. [Know-how] In the past, one-piece resin is sealed into a package: 下 下 Tr: package "), on both sides of a copper box substrate (hereinafter abbreviated as ^ wire :, internal terminals and 'Surface package and two external terminals' are used for substrate through-hole vias or substrate through-hole vias. The vias are used to electrically connect = f-pass openings in a multilayer substrate. Multilayer substrates with more than 4 layers are called internal vias. Inner vias. If it is compared with through-holes =, it can be said that they have high mechanical strength or are in the resin sealing process. Process for preventing resin material from entering through holes It can be cut off. In addition, in order to share the above-mentioned vias and the like between adjacent packages, it is arranged at the outer peripheral end of the package, and then the vias and the like are used when the resin package = knife. Divided on the half-cut line, and the occupation ratio of the substrate relative to the package body will also be reduced. 1242267 ____ Case No. 90117199_ 车 月 日 你, 下 _ V. Description of the Invention A closed-hole processing method of a conductor disposed in a through-hole formed on a substrate, and after removing the copper foil layer on one side in a round shape, the copper foil layer on the reverse side is left, so it is performed by laser light irradiation. Treatment method of the inner peripheral surface after removing and processing the base plate (epoxy resin, glass epoxy resin, etc.), and then conducting the process. [Problems to be Solved by the Invention]

However, the closed-hole method of the through-holes disclosed in the aforementioned Japanese Patent Application Laid-Open No. 1 0-29440 0 requires a special technique for ensuring the mechanical strength of the closed-hole processing, which causes a cost increase. By the way, in recent years, so-called multi-layer substrates with more than 4, 6, or 8 layers have been used in the so-called bui ld-up method of forming internal via holes when the substrates are laminated. The power system is not shaped by the irradiated etch. The 5th (C) factor is left on the 5th (B) copper foil inside the hole.

There is a method of forming a via hole from one side of the copper foil layer. First, the copper box layer of the surface layer is removed in a circular shape, and then the base plate is removed by laser. In this process, the setting of this section is complicated and delicate, and the cross section ^ is formed into a completely cylindrical shape. As shown in FIG. 5 (A), the residue and uncut portion of the chip D are processed at the peripheral edge. As a result, when conducting the conduction treatment of the interlayer through the plating treatment, as shown in the figure, it is not possible to sufficiently secure the integrated contact portion for the conduction between the plating layer and the surface. In the contact part, there is an interface E, and through the half cut of the via hole and external impact, as shown in the figure, the 'contact part is peeled off, causing poor conduction.

1242267 Amendment No. 90miQQ V. Description of the invention (3) [Purpose] In view of this, the present invention is a via of a foil substrate for a semiconductor package and a manufacturing method of D = In addition, the integration of the two-sided copper on the integrated tree will use the semiconductor package between the two sides of the vias; sometimes, even when the vias are half-cut ::: products, the same peeling can achieve high Reliability and yield == The contact part will not be [solution to the problem] Directives =. The present invention relates to a semiconductor package and a common method, as described below. In other words, the present invention of the Fengzhuang # conductor package is characterized in that a circuit diagram of a plurality of semiconductor packages 2 is formed in rows and columns between == planes; a unit of semiconductor Packages ⑴ adjacent: a copper pig layer at a common position between the patterns is formed with an elongated hole-shaped opening (30); two in the long axis direction of the opening (3)

Page 6 After the two openings (31a, 31b), the base plate (11) exposed by the above-mentioned opening (30) is irradiated with laser light of an intensity not to damage the other copper box layer, so that two An opening (31c) is formed between the openings (31a, 31b), and a non-penetrating interlayer hole (3) having a long hole-like opening is formed; an inner surface of the interlayer hole (3) and After the copper foil layers on both sides have been conducted, a semiconductor crystal (20) and wiring are formed on a predetermined position of the circuit pattern on the θ substrate (1); a semiconductor crystal ( 2 〇) The table is completely sealed with resin, and then the above-mentioned via hole is cut on a half-cut line 1242267

(3) Manufactured.

There is also the above-mentioned method for manufacturing a semiconductor package, characterized in that a plurality of circuit patterns of the semiconductor packages (2) are formed in rows and columns between the two sides of the double-sided copper box substrate (1); A copper foil layer at a common position between adjacent circuit patterns of the semiconductor package (2) forms a long hole-shaped opening (30); then, two ends of the opening (30) in the long-axis direction are connected to each other. Two openings (31a, 31b); then, the base plate (11) exposed by the opening (30) is irradiated with laser light of a strength not to damage the other copper foil layer, so that the two openings (31 An opening (31c) is formed between 31a and 31b) to form a non-penetrating interlayer hole (3) having a long hole-like opening; copper is formed on the inner surface and both sides of the interlayer hole (3) After the foil layer is turned on, a semiconductor chip (20) is installed on a predetermined position of the circuit pattern on the substrate (1) and a wiring is formed; the surface of the substrate (1) device with the semiconductor crystal square (20) is completely Sealed with resin, then the vias (3) are separated on the half-cut line. Furthermore, in the resin sealing process, the fluorine resin film 40d may be interposed between the female jig 40 and the resin-sealed resin 25a. In addition, it should be noted that 'about the above-mentioned pictograms are reference supplements used for easy understanding of the present invention, but are not limited to the type 0 on the drawing. The diagram is briefly explained: The first figure shows the embodiment of the present invention. A perspective view of the appearance of a semiconductor package. ! 242267

Appearance. Fig. 3 shows the sequence of formation of vias in the embodiment of the present invention. Fig. 4 shows the resin sealing process, the process of enlarging the process-part of the enlargement (B) and the cutting process of the embodiment of the present invention ^ ) A, 丨 & FIG. 5 is a cross-sectional view of Qianyu A, 丨 surface animal ... a cross-sectional view of a via hole known to Bebu. Explanation of symbols] 1 ~ substrate; 11 ~ resin layer (base plate); 20 ~ semiconductor crystal; 21 ~ stage; 2 3 ~ metal wire; 2 5 ~ resin package; 25b ~ ¥ groove; 30 ~ opening 3 1 b ~ open hole (other end); 32 ~ interstitial hole for heat radiation; 40 ~ female female fixture; 40 ~ b convex part; 40d ~ fluorine resin film; 50 ~ cutting edge; E ~ interface. 1 0 ~ copper foil layer; 2 ~ package; 20a ~ electrode; 2 2 ~ internal terminal; 2 4 ~ external terminal; 2 5a ~ resin; 3 ~ interlayer hole; 31a ~ open hole (one end); 31c ~ Opening hole (middle); 4 ~ mo (id) metal fixture; 40a ~ bottom surface; 40 ~ c edge line; 5 ~ cutting device; D ~ processing chip;

Invention Examples

Page 8 1242267 --- Case No. 90117199 V. Description of the invention (6) January 1st Amendment The following is an embodiment of the semiconductor package of the present invention and a method for manufacturing the same, and will be described with reference to the drawings. Fig. 1 is a perspective view showing the appearance of a semiconductor package according to an embodiment of the present invention. Fig. 2 is an external view of a substrate on which via holes of an embodiment of the present invention are arranged. Fig. 3 is a cross-sectional view showing the order of formation of vias in the through-holes of the embodiment of the present invention. Fig. 4 is a cross-sectional view showing the resin sealing process (A), an enlarged portion (B) of the resin sealing process, and the cutting process (c) according to the embodiment of the present invention. Figure 5. is a cross-sectional view showing a conventional via hole.

The unit of the package 1 of this embodiment is a semiconductor wafer 20 of a stage 21 mounted on a substrate 1 as shown in FIG. 1 and an internal terminal 22 for connection of a metal wire arranged around the stage 21, And the metal wire 23 connecting the electrode 20a of the semiconductor cube 20 with the internal terminal 22, and the external terminal 24 on the inner side of the substrate 1, and the end side of the package 2, and the internal terminal 22 and the external terminal 24 that are turned on The entirety of the half-cut long-hole-shaped interlayer holes 3 is sealed with a resin and constituted. Since the relevant constituent bodies are the same as the conventional ones, detailed explanations are omitted. The following 'is a detailed description of an embodiment of the formation of the via hole 3 of the semiconductor package of the present invention and a manufacturing method thereof. As shown in FIG. 2, first, a predetermined number of long hole-shaped openings 3 are formed at predetermined positions through the copper foil layer 10 on one side by etching. The openings 30 of this embodiment have a size of, for example, 0.15 mm in diameter and 0. 35 mm in the longitudinal direction. This arrangement position is arranged in a row pattern in a post process, and is arranged in the pattern. When the end portion is further cut at the centerline position in the longitudinal direction of the via hole 3, each common position is set between the adjacent seal bodies 2. Also, because of the exothermic effect

1242267 _Case No. 90117199 Car. Fifth, the invention description (7) is better. Therefore, even if the heat dissipation vias 3 2 are arranged on the inner side of the package 2 (such as the two-point wire locking part in Figure 2).

Next, as shown in FIG. 3, in the first step (a), one end side in the longitudinal direction of the opening portion 30 is connected, and the copper pig layer J 0 on the reverse side is not damaged. The resin layer is removed by irradiation to form a substantially cylindrical opening 3 1 a. In the next step (B), the other end side in the longitudinal direction of the opening portion 30 is connected, and the resin layer 11 is removed to form a substantially cylindrical opening 3 1 b. In the final step (C), the resin layer remaining in the middle portion irradiated to form the opening 3 1 c between the irradiation positions is removed. As a result, three openings 31a, 311) and 310 which are continuously removed are formed, and the interlayer hole 3 having a long hole-like opening shape is formed. Thereafter, a conduction process is performed on the inner surface of the via hole 3 by an electrolytic method. In this process, as shown in FIG. 3, the via hole 3 of this embodiment has a mortar-like shape, and a large contact area can be ensured due to the long hole shape. ^ In this embodiment, the processing through the laser light is performed at a high speed (for example, 1000 cavities per second) by a laser drilling machine equipped with a Galvano system. Shadow, pattern

= The conventional method is to sinter on the substrate 1 through the photo method, display / extract the solution, and then form a predetermined number of the circuit platform 21, the internal terminal 22 and the external terminal 24 at a predetermined position, and then The semiconductor wafer is mounted on a flat surface, and then a metal wire connection is performed. Then, as shown in FIG. 4, the entire substrate 1 is set on the mold gold resin, and sealing A is performed: the filling of the resin 25a for fat sealing is performed, and the bottom surface 4II body 25 is formed. In the female metal jig section of the mold metal jig 4, a V-shaped convex portion 40b is formed in a grid. 5. Description of the invention (8) is large, and the ridge line 40c of the convex portion 40b is connected. The line at the center of the via 3 on the substrate i side corresponds to the top and bottom. Via the convex portion 40b, the grid-like v-shaped groove 25b (hereinafter referred to as "v-groove") on the upper surface of the resin sealing body corresponds to a position corresponding to the up-down direction of the via hole 3. In addition, the releasability of the Yoshio male + shape metal fixture 40 and the resin 25 & makes the gaseous film 40d interposed between the bottom surface 40a of the female shape fixture 40.

Finally, the entire substrate 1 is detached from the jig 4 and fixed to the cutting device. A cutting blade 50 cuts along the V groove 251 ", and is divided into 1 unit each time it reaches the interlayer L. : The thickness of the cutting blade 50 is to set a circumferential portion that cannot be touched. The interstitial hole 3 is divided to form a lead seal for the internal terminal 22 and the external terminal 24 of the sealing body 2 which is a through hole: Ϊ2: Two. : And '4, it is necessary to change the partition plane and part of the interstitial hole 3 from the seal / ^ 25 cut surface to approximately the same.' The substrate 1 is not extended by the outer ring temple of the package 2 丨, And it is designed as the effect of the invention: Layered-hole semiconductor package and its manufacturing method *, because ^

The shape of the private part of the conductive part of the conductive process is about peeling when the via hole is half-cut in the via hole = lifting upward, and the reliability of the electrical connection of the package is strengthened, so that the invention The purpose of the rainbow, production efficiency is improved, and: ;; :::: Yield of body manufacturing 制造

Claims (1)

1242267 1. A semiconductor package characterized by having a circuit pattern of a plurality of semiconductor packages (2) formed in rows and columns between two sides of a two-sided copper foil substrate (1); a unit of semiconductor package The body (2) is a common stone between adjacent circuit patterns, and a copper foil layer is disposed to form a long hole-shaped opening (3㈧; the two ends in the long axis direction of the opening two 1/3/3) are connected with each other. The two openings (31 &,) are then irradiated with the laser light of a strength not to damage the other copper foil layer to the base plate (11) exposed at the opening (30), so that the two openings An opening (31c) is formed between the holes (3U, lb), and a non-penetrating interlayer hole (3) having a long hole-like opening is formed; an inner surface of the interlayer hole (3) and After the copper foil layers on both sides have been conducted, a semiconductor crystal cube (20) and wiring are formed on a predetermined position of the circuit pattern on the substrate (0). A semiconductor crystal cube (20) is installed on the substrate (1). ) The surface is completely sealed with resin, and then the interlayer hole (3) is cut on a half-cut line. 2 · A method for manufacturing a semiconductor package, characterized in that: a circuit pattern of a plurality of semiconductor packages (2) is formed in rows and columns between two sides of a double-sided copper foil substrate (1); A copper foil layer at a common position between the adjacent circuit patterns of the package body (2) forms a long hole-shaped opening (30); then, two ends of the opening (30) in the long-axis direction are connected to each other. Two openings (3a, 31b), and then irradiate the base plate (11) exposed by the opening portion (30) with laser light of a strength not to damage the other copper foil layer, so that the two An opening (31c) is formed between the openings (3ia, 31b) to form a long hole-shaped opening. Page 1212267 ___90117199____Noon in January __ VI. Patent application scope Non-penetrating interlayer hole (3); after the inner surface of the interlayer hole (3) and the copper foil layers on both sides are conducted, A semiconductor crystal cube (20) is installed on a predetermined position of the circuit pattern on the substrate (1), and wiring is formed; a surface of the semiconductor crystal cube (20) on the substrate (1) device is completely sealed with a resin, and then The interlayer hole (3) is cut on the half-cut line. 3. A method for fabricating a semiconductor package as described in item 2 of the scope of patent application, wherein during the resin sealing process, the fluorine resin film (40d) is interposed between the female fixture (40) and the resin Sealing resin (25a). Page 13