CN114823606A - Packaging element with composite pin structure and manufacturing method thereof - Google Patents

Packaging element with composite pin structure and manufacturing method thereof Download PDF

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Publication number
CN114823606A
CN114823606A CN202210366449.4A CN202210366449A CN114823606A CN 114823606 A CN114823606 A CN 114823606A CN 202210366449 A CN202210366449 A CN 202210366449A CN 114823606 A CN114823606 A CN 114823606A
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China
Prior art keywords
pin
pins
substrate
chip
layer
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Pending
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CN202210366449.4A
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Chinese (zh)
Inventor
王永辉
何中雄
李季学
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PanJit International Inc
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PanJit International Inc
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Application filed by PanJit International Inc filed Critical PanJit International Inc
Priority to CN202210366449.4A priority Critical patent/CN114823606A/en
Publication of CN114823606A publication Critical patent/CN114823606A/en
Pending legal-status Critical Current

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814—Conductive parts
    • H01L21/4885—Wire-like parts or pins
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Lead Frames For Integrated Circuits (AREA)

Abstract

The invention is a packaging element with combined pin structure and its preparation method, plan out a body area and a pin area on a base plate, and set up a crystal plate and connect the crystal plate to the conducting layer of the relative surface of the base plate electrically on the body area of the base plate; the pin area predefines a plurality of pin positions which are parallel, when the electric connection operation of the chip is completed in the body area, a cutting tool can be used for cutting along the edge of the body area and the pin positions, the body area forms a packaging element body, and a plurality of pins are formed at the plurality of pin positions; the pins of the invention are formed integrally by the substrate of the packaging element body, and the traditional lead frame is not needed.

Description

Packaging element with composite pin structure and manufacturing method thereof
Technical Field
The present invention relates to a package device, and more particularly, to a package device with a composite pin structure.
Background
Pins (pins) of a conventional semiconductor package device are mainly formed by a copper lead frame (lead frame), and for example, the power transistor shown in fig. 16 is manufactured by bonding a chip 300 on a die pad area of a lead frame 301, and a plurality of parallel pins 302 are preformed on the lead frame 301, after the bonding, a wire bonding step is performed to electrically connect signal contacts on the chip 300 to different pins 302 on the lead frame 301 through wires 303, and finally, the chip 300 is covered with an insulating molding compound 304.
Fig. 17 and 18 show horizontal and vertical packaging methods, respectively, in which if the signal contacts of the chip 300 are all located on the same plane, the horizontal packaging of fig. 17 is adopted during wire bonding, and the signal contacts located on the surface of the chip 300 are connected to the corresponding pins 302 on the lead frame 301 through wires 303; if the signal contacts of the chip 300 are located on the top and bottom surfaces, respectively, during wire bonding, as shown in the vertical package of fig. 18, the signal contacts on the top surface of the chip 300 are connected to the corresponding pins 302 through wires 303, and the other signal contact on the bottom surface of the chip 300 is connected to the lead frame 301 through solder such as silver or solder.
No matter horizontal or vertical packaging is adopted, through hole mounted (PTH) packaging devices mainly use the pre-formed pins of the lead frame as the pins of the packaging device, but the use of the lead frame has the disadvantage that the lead frame of a dedicated type needs to be designed and manufactured for various packaging devices, and the packaging manufacturer needs to purchase the lead frame as the raw material for the supplier, so the packaging manufacturing cost is relatively high.
On the other hand, the finished product after packaging has a relatively large overall thickness and is not favorable for thinning the device because of the thickness of the lead frame, the height of the chip, the height of the wire bonding and the thickness of the sealing material.
Disclosure of Invention
Accordingly, the present invention is directed to a package device with a composite pin structure without using a lead frame as a raw material and a method for fabricating the same.
The invention relates to a packaging element with a composite pin structure, which comprises:
a packaging element body, including a substrate composed of an insulating body and multiple conductive layers, wherein the substrate is formed with a chip placing opening for accommodating a chip;
a plurality of pins extending outward from the package device body and electrically connected to the chip, each pin being a composite laminated structure, the composite laminated structure including:
the insulating body integrally extends from the packaging element body, and the plurality of conducting layers are arranged on two opposite surfaces of the insulating body to be electrically connected with the chip.
The invention relates to a method for manufacturing a packaging element with a composite pin structure, which comprises the following steps:
preparing a substrate, wherein the substrate is divided into a body area and a pin area, a plurality of pin positions are preset in the pin area, the substrate comprises an insulating body, and two opposite surfaces of the insulating body are respectively provided with at least one conducting layer;
forming a chip placing opening and at least one through hole in the body region;
placing a wafer into the wafer placing opening;
electrically connecting the chip to the conductive layer and the via hole of the substrate;
the molding packaging element body and the one-hand foot are cut along the edge of the body area and the stitch position, the body area is made to form a packaging element body, the substrate reserved at the stitch position forms a plurality of stitches, and each stitch comprises the insulating body and the conducting layers on the two opposite surfaces of the insulating body.
The invention provides a chip arrangement by using the same substrate, the chip is electrically connected with the conducting layer of the substrate, a plurality of pins can be obtained by cutting the substrate and the conducting layer, and the conducting layer on each pin is electrically connected with the chip, thereby forming a thin packaging element without using a traditional lead frame.
Drawings
FIGS. 1A to 1E: the manufacturing process of a preferred embodiment of the present invention is schematically illustrated.
Fig. 2A to 2B: a part of the manufacturing process of another preferred embodiment of the present invention is schematically illustrated.
FIG. 3: the operation of the stitch cutting according to a preferred embodiment of the present invention is illustrated.
FIG. 4: a plan view of a preferred embodiment of the present invention.
FIG. 5: the invention is a partial enlarged view of the stitch.
Fig. 6A to 6E: the manufacturing process of another preferred embodiment of the present invention is schematically illustrated.
FIG. 7: FIGS. 6A-6E are schematic plan views of the embodiment after forming through holes in the stitch areas.
FIG. 8: FIGS. 6A-6E are schematic plan views of the embodiment after completion of stitch cutting.
FIG. 9: fig. 6A to 6E are schematic perspective views of the embodiment after finishing stitch cutting.
FIG. 10: a schematic plan view of another embodiment of the pin of the present invention.
FIG. 11: fig. 10 is a schematic diagram of the pins after being plugged into the circuit board.
FIG. 12: a schematic plan view of another embodiment of the pin of the present invention.
FIG. 13: fig. 12 is a schematic diagram of the pin after being plugged into the circuit board.
FIG. 14: the invention also discloses a plane view of another embodiment of the stitch.
FIG. 15: fig. 14 is a schematic diagram of the pins after being plugged into the circuit board.
FIG. 16: a schematic perspective view of a conventional power transistor.
FIG. 17: a cross-sectional view of a conventional horizontal package device.
FIG. 18: a cross-sectional view of a conventional vertical package device.
Detailed Description
Referring to fig. 1A to 1D, in the first embodiment of the present invention, a metal lead frame is not used as a raw material in the manufacturing process, and a required pin can be formed through a panel level package Process (PTH) package device, which is taken as an example. Referring to fig. 1A, in the embodiment, a Copper foil board (CCL) is selected as a substrate, the Copper foil board is formed by laminating Copper foils on the upper and lower surfaces of an insulating body 10, the Copper foils are used as conductive layers 11 and 12, a body area a and a pin area B are pre-divided on the substrate, the body area a is used for accommodating a wafer, forming a conductive through hole, or manufacturing a redistribution layer (RDL) to form an area of a package element body, the pin area B is an area where pins of the package element are finally formed, and the positions and the number of the pins are planned in the pin area B according to product specifications.
Referring to fig. 1B and 1C, a wafer placing opening 13 and a via hole 14 are formed in the body region a, and a conductive material is plated on an inner wall surface of the via hole 14 or filled in the via hole 14, so that the via hole 14 is electrically connected to the conductive layers 11 and 12; the wafer 20 is placed in the wafer placing opening 13, the wafer 20 has signal contacts 21, and the positions of the signal contacts 21 are not limited, and may be on the same surface of the wafer 20 or on the upper and lower surfaces of the wafer 20. In the embodiment of fig. 1C, the upper and lower surfaces of the wafer 20 have signal contacts 21.
Referring to fig. 1D, after the wafer 20 is placed, different signal contacts 21 are electrically connected to the pin areas B according to device requirements, and the electrical connection may be realized by electroplating, forming one or more redistribution trace layers (RDLs), and the like; fig. 1D only schematically shows that the signal contacts 21 are electrically connected to the conductive layers 11 and 12 in the pin area B, for example, an insulating layer 30 is formed on the substrate to cover the substrate and the chip 20 and extend to the pin area B, and then a circuit layer 40 is formed on the surface of the insulating layer 30 by a photolithography process, the circuit layer 40 is electrically connected to the corresponding signal contacts 21 and also extends to the pin area B; the signal contacts 21 on the bottom surface of the chip 20 can be fabricated with a bottom circuit layer 42 for electrically connecting to the corresponding conductive layer 12, via hole 14, etc.
Referring to fig. 1E, a passivation layer (resist mask)50 is formed on the outermost surface of the substrate body region a, and the passivation layer 50 does not need to extend to cover the stitch region B; in this embodiment, a passivation layer 50 is formed on each of the upper and lower sides of the body region a of the substrate.
In the foregoing embodiment, the substrate is a copper foil substrate. In addition, the substrate may also be an insulating substrate made of a general dielectric material, and the upper and lower surfaces of the insulating substrate are not laminated with copper foil in advance, and a desired conductive circuit layer may be formed on the surface of the insulating substrate by a photolithography process, for example, the conductive layers 11 and 12 and the circuit layer 40 are formed by the photolithography process.
Referring to fig. 2A and 2B, in another embodiment, no additional circuit layer 40 is required to be formed on the substrate, and the conductive layers 11 and 12 and the bottom circuit layer 42 originally laminated on the upper and lower surfaces of the substrate are used to electrically connect to the chip 20.
Referring to fig. 3 and 4, a cutting tool is used to cut the body region a and the pin region B of the substrate, wherein the package device body 100 is formed after cutting along the edge of the body region a, and the package device body 100 is rectangular. Cutting in the pin area B to perform pin forming operation, reserving a predetermined pin position and removing unnecessary substrate area, wherein the reserved substrate forms pins 60 of the packaging element; the left side of the schematic diagrams of fig. 1A-1E only shows the side view structure of a single pin 60, and in practice, the package device has a plurality of parallel pins. In the present embodiment, a forming machine (routing machine) may be used to cut the excess substrate to form the required pins 60, and other forming methods such as stamping, laser cutting, etc. may also be used to form the pins 60, such as controlling the milling cutter 200 to move along the cutting path R of fig. 3, i.e. along the edge of the predetermined position of the pin 60.
Each pin 60 has a structure as shown in fig. 5, and includes an insulating body 10 at least in the middle, and conductive layers on the front and back sides of the insulating body 10, wherein the conductive layers may include the copper foil layer 12 of the substrate itself or the circuit layer 40 and the bottom circuit layer 42 formed by subsequent processes; each pin 60 is electrically connected to the wafer 20 through the conductive layer. Since the pins 60 are formed after the body 10 is cut, the length/width of the pins 60, the pitch (pitch) between adjacent pins 60, etc. can be cut according to the specification of the product, and are not limited by the predetermined specification of the conventional leadframe. The thickness of each pin 60 itself or the thickness of the surface conductive layer can also be adjusted, for example, by stacking the insulating layer 30 or the circuit layer 40 to increase the thickness of the overall pin 60, or by electroplating to make the thicker circuit layer 40 to increase the thickness of the overall pin 60.
Referring to fig. 6A to 6E, another embodiment of the present invention is different from the embodiment of fig. 1A to 1E in that a plurality of through holes 15 are formed in the pin area B by mechanical drilling (as shown by arrows), the positions of the through holes 15 are distributed at the edge of each pin position as shown in fig. 7, and a plating layer 151 is plated on the inner wall surface of each through hole 15. When the pin area B of the package component is subjected to the pin forming step, the cutting tool cuts along the edge of the pin 60 to simultaneously cut the through holes 15, as shown in fig. 8 and 9, the cut through holes 15 naturally form concave arc-shaped notches 601 on two opposite sides of the pin 60, and the surface of each notch 601 is provided with the plating layer 151 to increase the tin-coated area on the sides of each pin 60, thereby improving the tin-wetting property of the package component. In this embodiment, since the through holes 15 and the hole wall plating are simultaneously formed during the formation of the through holes 14 in the body region a, no additional drilling and plating operations are required after the formation of the pins 60, thereby simplifying the process steps. However, in other embodiments, the pin 60 may be formed and then the entire surface of the pin 60 may be plated to make more area of the surface of the pin 60 to be attached with solder.
Referring to fig. 10 and 11, in the step of forming the pin, the pin 60 forms a pin body 61 and a narrowed portion 62, one end of the narrowed portion 62 is connected to the bottom surface of the package device body 100, and the other end is connected to the pin body 61; the width of the constriction 62 is slightly smaller than the width of the stitch body 61. Because the width of the narrowed portion 62 is smaller than the diameter of the solder hole on the circuit board P, when the pin 60 is inserted into the circuit board P, the bottom surface of the package component body 100 can be flush with the surface of the circuit board P, and this embodiment can improve the stability of the Surface Mount Technology (SMT) when soldering to the circuit board P, and ensure that the package component does not shake on the circuit board P. The constriction 62 can be formed by cutting along a cutting path R as shown in fig. 10 using a milling cutter, and moving the milling cutter toward the center of the pin 60 to slightly cut the tip of the portion of the pin 60 when the milling cutter moves to the joint of the pin 60 and the bottom surface of the package body component 100, and then cutting along the edge of the pin 60 after the milling cutter is withdrawn outward, thereby forming the constriction 62 at one end of the pin 60.
Referring again to fig. 12 and 13, in the step of forming the pins, grooves 102 may also be formed on the bottom surface of the package component body 100, and the grooves 102 are located on two opposite sides of each pin 60; similarly, when the pin 60 is inserted into the circuit board P, the bottom surface of the package component body 100 can be flush with the surface of the circuit board P, so that the package component does not shake on the circuit board P, and the gap formed between the package component body 100 and the surface of the circuit board P by the groove 102 can also increase the heat dissipation effect. The groove 102 can be formed by cutting along a cutting path R as shown in fig. 12 by a milling cutter, and when the milling cutter moves to the interface of the pin 60 and the package body 100, the milling cutter is controlled to move slightly inward toward the bottom surface of the package body 100, and the milling cutter is withdrawn outward and then cut along the edge of the pin 60, so as to form the groove 102 on the bottom surface of the package body 100.
Referring to fig. 14 and 15, compared to the embodiment of fig. 10, the pin 60 of the present invention may further form a supporting portion 63, the supporting portion 63 is connected to the bottom surface of the package body 100 and has a width slightly larger than that of the pin body 61, and the width of the supporting portion 63 is also larger than the diameter of the solder hole on the circuit board P; the narrowed portion 62 is formed at the bottom end of the support portion 63, and the width of the narrowed portion 62 is slightly smaller than the diameter of the solder hole on the circuit board P. When the package component is plugged on the circuit board P, the lower edge of the supporting portion 63 is pressed against the surface of the circuit board P, so that a heat dissipation gap G is formed between the bottom surface of the package component body 100 and the circuit board P, and the part below the narrowed portion 62 can enter the soldering hole; the package device body 100 and the surface of the circuit board P have a heat dissipation gap G therebetween, so that the heat dissipation effect can be further improved.
Based on the above detailed description, embodiments of the invention may have one or more of the following advantages:
1. the invention utilizes the Panel Level Package (PLP) technology to manufacture the package element, and pins required by the package element can be manufactured without using a lead frame.
2. Compared with the traditional packaging element, the invention can effectively reduce the whole thickness of the packaging element because the lead frame, the wire bonding and the glue (molding) are not needed, thereby being beneficial to reducing the product volume and improving the heat dissipation effect.
3. When the side of the pin is notched, the tin-adhering area can be increased, and the solderability (solderbility) of the product can be improved.
4. The formed product can be judged for quality control by an automatic optical inspection instrument (AOI) to detect whether the appearance has defects.
Although the present invention has been described with reference to the preferred embodiments, it should be understood that various changes, substitutions and alterations can be made herein without departing from the spirit and scope of the invention as defined by the appended claims.

Claims (14)

1. A kind of packaging element with composite pin structure is characterized in that it includes:
a packaging element body, including a substrate composed of an insulating body and multiple conductive layers, wherein the substrate is formed with a chip placing opening for accommodating a chip;
a plurality of pins extending outward from the package device body and electrically connected to the chip, each pin being a composite laminated structure, the composite laminated structure including:
the insulating body integrally extends from the packaging element body, and the plurality of conducting layers are arranged on the two opposite surfaces of the insulating body to be electrically connected with the wafer.
2. The packaging device with composite pin structure of claim 1, wherein the packaging device body has a protection layer on each of two opposite surfaces thereof.
3. The package component with composite pin structure as claimed in claim 1, wherein the package component body has a via hole therein, the via hole being electrically connected to at least one of the conductive layers.
4. The package component with composite pin structure of claim 1, wherein the side of each pin is formed with a plurality of arc-shaped notches, and the surface of each arc-shaped notch has a plating layer.
5. The package component with composite pin structure of claim 1, wherein each pin comprises a narrowed portion and a pin body, one end of the narrowed portion is connected to the package component body, and the other end is connected to the pin body;
the width of the narrowing part is smaller than that of the pin body.
6. The packaging component of claim 1, wherein the packaging component body has a plurality of grooves formed on a surface thereof extending out of the pins, and each of the pins has one of the grooves on opposite sides thereof.
7. The package component with composite pin structure of claim 1, wherein each pin comprises a supporting portion, a narrowing portion and a pin body sequentially extending, one end of the supporting portion is connected to the package component body;
the width of the supporting part is larger than that of the pin body, and the width of the pin body is larger than that of the narrow part.
8. A method for manufacturing a package device with a composite pin structure is characterized by comprising the following steps:
preparing a substrate, wherein the substrate is divided into a body area and a pin area, a plurality of pin positions are preset in the pin area, the substrate comprises an insulating body, and two opposite surfaces of the insulating body are respectively provided with at least one conducting layer;
forming a chip placing opening and at least one through hole in the body region;
placing a wafer into the wafer placing opening;
electrically connecting the chip to the conductive layer and the via hole of the substrate;
forming a packaging element body and pins, cutting along the edges of the body area and the pin positions to form a packaging element body in the body area, and forming a plurality of pins on the substrate reserved at the pin positions, wherein each pin comprises the insulating body and the conducting layers on the two opposite surfaces of the insulating body.
9. The method of claim 8, wherein the step of electrically connecting the chip and the conductive layer of the substrate further comprises:
forming an insulating layer on the surface of the substrate, wherein the insulating layer covers the chip;
forming a circuit layer on the insulating layer, wherein the circuit layer is electrically connected to the chip, and the circuit layer extends to the pin positions.
10. The method of claim 9, wherein a passivation layer is formed on the circuit layer and under the substrate in the body region.
11. The method of claim 8, wherein a plurality of through holes are formed in the pin area and a conductive layer is formed on an inner wall of each through hole when the chip placement opening and the at least one via hole are formed in the body area, the through holes being distributed along an edge of the pin;
in the step of forming the pins, the through holes are cut to form a plurality of notches in the side surfaces of the pins.
12. The method of claim 8, wherein in the step of forming the pins, an end of each pin adjacent to the package body is partially cut to form a narrowed portion on each pin.
13. The method of claim 8, wherein in the step of forming the pins, the package component body is partially cut on a side thereof connected to the pins to form a recess, and each pin has a recess on opposite sides thereof.
14. The method of claim 8, wherein in the step of forming the pins, each pin comprises a supporting portion, a narrowing portion and a needle body sequentially extending, wherein one end of the supporting portion is connected to the package body; the width of the supporting part is larger than that of the pin body, and the width of the pin body is larger than that of the narrow part.
CN202210366449.4A 2022-04-08 2022-04-08 Packaging element with composite pin structure and manufacturing method thereof Pending CN114823606A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN202210366449.4A CN114823606A (en) 2022-04-08 2022-04-08 Packaging element with composite pin structure and manufacturing method thereof

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN202210366449.4A CN114823606A (en) 2022-04-08 2022-04-08 Packaging element with composite pin structure and manufacturing method thereof

Publications (1)

Publication Number Publication Date
CN114823606A true CN114823606A (en) 2022-07-29

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Family Applications (1)

Application Number Title Priority Date Filing Date
CN202210366449.4A Pending CN114823606A (en) 2022-04-08 2022-04-08 Packaging element with composite pin structure and manufacturing method thereof

Country Status (1)

Country Link
CN (1) CN114823606A (en)

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