1241680 A7 B7 五、發明說明（ 發明領域： (請先閱讀背面之注意事項寫本頁) 本發明係有關於一種介電層的形成方法，且特別是有 關於一種在單一反應室中形成ONO(oxide-nitride-oxide)介 電堆疊層的方法。 發明背景： 當電腦微處理器愈來愈快速，對記憶體的需求也相對 地愈高。記憶體的其中一種為隨機存取記憶體（RAM)，例 如動態隨機存取記憶體（DRAM)，早已在電腦中廣泛的應 用’但其資料會隨著電源供應的中斷而消除，故稱作揮發 性記憶體。相對地，一種稱為非揮發性記憶體，例如快閃 記憶體（Flash memory)，其資料不會因為電源供應的中斷而 消失’而可應用在其它不同的場合，比如個人電腦或是個 人數位助理等。 經濟部智慧財產局員工消費合作社印製 在製作§己憶體的資料儲存電容時，通常會在兩個電極 之間形成一層絕緣介電層來防止儲存資料電荷流失。以快 閃記憶體為例，介電層係製作在懸浮閘（floating gate)與控 制閘（control gate)之間。請參照第i圖，其繪示傳統快閃 記憶體之結構剖面示意圖。在一半導體基底丨〇上形成有一 閘極堆疊層，且在閘極堆叠層兩側的基底1〇中形成有源極 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公餐） 1241680 A7 五、發明說明（） /汲極區1 2，以形成一半導體電晶體，控制資料的存取。閘 極堆疊層由下而上依序包括氧化矽層1 4，作為閣極介電 層；複晶矽I 16，作為懸浮閘；介電層丨8，作為絕緣層， 防止記憶儲存資料流失，目前普遍使用氧化石夕-氣化碎氧 化矽（ΟΝΟ)介電層，可獲得較佳的絕緣效果，以及較高的 崩潰電壓，藉以使快閃記憶體具有較佳的電性操作性能； 複晶矽層20，以作為控制閘極；矽化鎢層22，跟複晶矽層 20 —起作為控制閘極，並藉以降低控制閘極的電阻；以及 頂蓋層24，用以保護底下的矽化鎢層22。在閘極堆疊層的 側壁上一般會形成一閘極間隙壁26，保護閘極堆疊層之側 壁免受後續製程的破壞。 線 由於ΟΝΟ介電層1 8係用來防止儲存於懸浮閘隻電荷 /；IL ^因此όνο "電層1 8結構的良窥直接會影響記憶體 的操作性能。傳統在製作0Ν0介電層丨8時，是利用兩個 不同的沉積反應室分別沉積氧化矽層與氮化矽層，堆疊形 成ΟΝΟ介電層18。然而，當晶圓從其中一個沉積反應室 移到另一個沉積反應室時，必須破壞原有的真空狀態，使 得此段沉積過程的時間拉長，因而無法有效地提昇產能， 而且在移轉過程中晶圓容易受到周圍殘存微粒的污染，使 得ΟΝΟ介電層1 8無法形成良好的結構，而致使〇Ν〇介電 層1 8的品質無法順利提昇。 本紙張尺度適用中國國家標準（CNS)A4規格⑵G χ 297公餐 1241680 A7 B7 五、發明說明（） 發明目的及概述： <請先閱讀背面之注意事項寫本頁) 鑒於上述之發明背景中，傳統ΟΝΟ介電層的製作方法 容易使ΟΝΟ介電層受到污染，而且無法提昇產率。因此， 本發明提供一種單一反應室形成介電堆疊層的方法及其裝 置，可以在單一反應室中形成介電堆疊層，不僅不會有微 粒污染的問題發生，而且可以有效地提昇製作介電層的生 產效率。 本發明提供一種製作介電堆疊層之裝置。此裝置至少 包括一沉積反應室，可載入一晶圓於沉積反應室中；一第 一供氣裝置，用以供應一矽烷氣體至沉積反應室；一第二 供氣裝置，用以供應一氨氣至沉積反應室；一第三供氣裝 置，用以供應一氧化氮氣體至沉積反應室；以及一排氣裝 置，用以排出沉積反應室中的氣體。其中，矽烷氣體與氧 化氮氣體反應在晶圓上沉積形成氧化矽層，且矽烷氣體與 氨氣反應在晶圓上沉積形成氮化矽層。 經濟部智慧財產局員工消費合作社印製 本發明亦提供一種介電堆疊層之製造方法，此方法至 少包括下列步驟。首先將一晶圓載入一沉積反應室中。接 著在沉積反應室中通入矽烷氣體與氧化氮氣體，藉以在晶 圓上沉積第一氧化石夕層。然後改變通入氣體，在沉積反應 室中通入矽烷氣體與氨氣，藉以在晶圓上沉積氮化矽層。 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐) 1241680 α7 Β7 五、發明說明（） 之後再改換氣體，在沉積反應室中通入矽烷乳體與氧化氮 氣體，藉以在晶圓上沉積第二氧化石夕層。 利用本發明之單一反應室形成介電堆登層的方法及其 裝置，可以在單一反應室中連續形成ΟΝΟ介電堆疊層，不 僅0Ν0介電堆疊層結構良妤，而且可以增進0Ν0介電堆 疊層的製作效率。 圖式簡單說明： 本發明的較佳實施例將於往後之說明文字中輔以下列 圖形做更詳細的闡述，其中： 第1圖是習知一種快閃記憶體之結構剖面示意圖，在 兩層複晶矽層之間形成0Ν0介電層。 第2圖緣示本發明形成0Ν0介電堆疊層之沉積裝置的 區塊圖。 第3圖繪示本發明之一較佳實施例之沉積裝置的操作 條件關係圖。 第4圖繪示關於第3圖之操作條件所形成之結構剖面 示意圖。 經濟部智慧財產局員工消費合作社印製 第5圖繪示本發明之沉積裝置之一變化例的操作條件 關係圖。 第6圖繪示關於第5圖之操作條件所形成之結構别面 5 1241680 A7 B7 五、發明說明（ 經濟部智慧財產局員工消費合作社印製 示意 圖。 第7圖本發明之另 一較佳實施例之沉積裝 件關 係圖，可獲得較佳之氮化矽層結構。 圖號對照說明： 10 半導體基底 12 源極/汲極區 14 氧化矽層 16 複晶矽層 18 ΟΝΟ層 20 複晶矽層 22 矽化鎢層 24 頂蓋層 26 間隙壁 1 10 供氣裝置 1 12 氨氣供應裝置 114 矽烷供應裝置 116 氧化氮供應裝置 1 18 氮氣供應裝置 120 供氣裝置 130 製程反應室 132 氣體流量控制盒 134 反應室 140 晶圓 150 節流閥 160 排氣裝置 200 半導體基底 210 導電層 212 氧化矽層 213 氮氧化矽層 214 氮化矽層 215 氮氧化矽層 216 氧化矽層 Τι > Τ2 溫度 ti ' t2 ' t3 ' tn 時間 作條 發明詳細說明： 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） --------------Μ — f琦先閱讀背面之注意事項¥寫本頁) .線- 12416801241680 A7 B7 V. Description of the invention (Field of invention: (Please read the notes on the back to write this page) The present invention relates to a method for forming a dielectric layer, and in particular to a method for forming ONO in a single reaction chamber ( oxide-nitride-oxide). Background of the Invention: As computer microprocessors become faster and faster, the demand for memory is relatively higher. One of the memories is random access memory (RAM) ), Such as dynamic random access memory (DRAM), has been widely used in computers' but its data will be eliminated with the interruption of power supply, so it is called volatile memory. In contrast, a type is called non-volatile Sexual memory, such as Flash memory, its data will not disappear because of the power supply interruption, and can be applied to other different occasions, such as personal computers or personal digital assistants. Intellectual Property Bureau of the Ministry of Economic Affairs Printed by employee consumer cooperatives. When making §memory data storage capacitors, an insulating dielectric layer is usually formed between the two electrodes to prevent the storage of data charges. Taking flash memory as an example, the dielectric layer is made between a floating gate and a control gate. Please refer to FIG. I, which shows a schematic cross-sectional view of the structure of a traditional flash memory. A gate stack layer is formed on a semiconductor substrate, and a source electrode is formed in the substrate 10 on both sides of the gate stack layer. The paper size is applicable to the Chinese National Standard (CNS) A4 specification (210 X 297 meals). ) 1241680 A7 V. Description of the invention () / Drain region 12 to form a semiconductor transistor to control data access. The gate stack layer includes a silicon oxide layer 14 from bottom to top in order to serve as a gate electrode Electrical layer; polycrystalline silicon I 16 as a suspension gate; dielectric layer 丨 8 as an insulating layer to prevent the loss of memory and stored data. At present, the oxide layer of silicon oxide-gasified broken silicon oxide (〇ΝΟ) dielectric layer is commonly used to obtain Better insulation effect and higher breakdown voltage, so that the flash memory has better electrical operation performance; the polycrystalline silicon layer 20 as a control gate; the tungsten silicide layer 22, and the polycrystalline silicon layer 20 — as the control gate, and Low control gate resistance; and a cap layer 24 to protect the underlying tungsten silicide layer 22. A gate gap wall 26 is generally formed on the side wall of the gate stack layer to protect the side wall of the gate stack layer from The destruction of subsequent processes. Because the ΝΟΟ dielectric layer 18 series is used to prevent the charge stored in the floating gate / IL; therefore, a good look at the structure of the electrical layer 18 directly affects the operating performance of the memory. Traditionally in When the ON0 dielectric layer is made, two different deposition reaction chambers are used to deposit a silicon oxide layer and a silicon nitride layer, respectively, and stacked to form a ONO dielectric layer 18. However, when the wafer is moved from one of the deposition reaction chambers to In another deposition reaction chamber, the original vacuum state must be destroyed, so that the length of the deposition process is prolonged, so that the productivity cannot be effectively improved, and the wafer is easily contaminated by residual particles around it during the transfer process, making ΝΝΟ The dielectric layer 18 cannot form a good structure, so that the quality of the ONO dielectric layer 18 cannot be improved smoothly. This paper scale applies Chinese National Standard (CNS) A4 specifications ⑵ G χ 297 public meal 1241680 A7 B7 V. Description of the invention () The purpose and summary of the invention: < Please read the notes on the back first to write this page) In view of the above background of the invention The traditional manufacturing method of the ONO dielectric layer is easy to contaminate the ONO dielectric layer, and the yield cannot be improved. Therefore, the present invention provides a method and a device for forming a dielectric stack layer in a single reaction chamber, which can form a dielectric stack layer in a single reaction chamber, which not only does not cause the problem of particle contamination, but also effectively enhances the production of dielectrics. Production efficiency. The invention provides a device for manufacturing a dielectric stack layer. This device includes at least a deposition reaction chamber that can load a wafer into the deposition reaction chamber; a first gas supply device for supplying a silane gas to the deposition reaction chamber; a second gas supply device for supplying a Ammonia gas to the deposition reaction chamber; a third gas supply device for supplying a nitric oxide gas to the deposition reaction chamber; and an exhaust device for exhausting the gas in the deposition reaction chamber. Among them, a silane gas and a nitrogen oxide gas are deposited on the wafer to form a silicon oxide layer, and a silane gas and ammonia gas are deposited on the wafer to form a silicon nitride layer. Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economics The present invention also provides a method for manufacturing a dielectric stack. This method includes at least the following steps. A wafer is first loaded into a deposition reaction chamber. Then, a silane gas and a nitrogen oxide gas are introduced into the deposition reaction chamber, thereby depositing a first oxide layer on the wafer. Then, the gas to be introduced is changed, and a silane gas and an ammonia gas are introduced into the deposition reaction chamber, thereby depositing a silicon nitride layer on the wafer. This paper size is in accordance with China National Standard (CNS) A4 (210 X 297 mm) 1241680 α7 Β7 V. Description of the invention () After changing the gas, pass the silane emulsion and nitrogen oxide gas into the deposition reaction chamber, so that A second oxide layer is deposited on the wafer. The method and device for forming a dielectric stack landing layer by using the single reaction chamber of the present invention can continuously form a ΝΟ dielectric stack layer in a single reaction chamber. Production efficiency of layers. Brief description of the drawings: The preferred embodiment of the present invention will be described in more detail in the following explanatory text with the following figures, where: Figure 1 is a schematic cross-sectional view of a conventional flash memory structure. A 0N0 dielectric layer is formed between the multiple layers of polycrystalline silicon. Fig. 2 shows a block diagram of a deposition device for forming a ONO dielectric stack according to the present invention. Fig. 3 is a diagram showing a relationship between operating conditions of a deposition apparatus according to a preferred embodiment of the present invention. Figure 4 is a schematic cross-sectional view of the structure formed by the operating conditions of Figure 3. Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs. Figure 5 shows a relationship diagram of the operating conditions of a modified example of the deposition apparatus of the present invention. Figure 6 shows the structural aspect formed by the operating conditions of Figure 5 5 1241680 A7 B7 V. Description of the invention (Schematic printed by the Employee Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs. Figure 7 Another preferred implementation of the present invention The relationship between the deposited components of the example can obtain a better silicon nitride layer structure. The comparison of the drawing numbers: 10 semiconductor substrate 12 source / drain region 14 silicon oxide layer 16 polycrystalline silicon layer 18 ONO layer 20 polycrystalline silicon layer 22 Tungsten silicide layer 24 Top cover layer 26 Partition wall 1 10 Gas supply device 1 12 Ammonia gas supply device 114 Silane supply device 116 Nitric oxide supply device 1 18 Nitrogen supply device 120 Gas supply device 130 Process reaction chamber 132 Gas flow control box 134 Reaction chamber 140 Wafer 150 Throttle valve 160 Exhaust device 200 Semiconductor substrate 210 Conductive layer 212 Silicon oxide layer 213 Silicon oxynitride layer 214 Silicon nitride layer 215 Silicon oxynitride layer 216 Silicon oxide layer Ti > Τ2 Temperature ti 't2 't3' tn Time to make a detailed description of the invention: This paper size applies the Chinese National Standard (CNS) A4 specification (210 X 297 mm) -------------- Μ — F Qi first read the notes on the back ¥ write this page). Line-1241680
發明說明（ ---------- - - - --- (請先閱讀背面之注意事？寫本頁) 本發明提供-種單-反應室中形成介電堆叠層的方法 及其裝置，在單-反應室中形成介電堆疊層，可以提昇製 作介電層的生產效率…可以避免介電堆疊層受到微粒 染，而影響其結構品質。 卜線 首先針對本發明之設備結構作介紹。請參照第2圖， 其繪示本發明形成介電堆疊層之沉積裝置的區塊圖。本發 明之沉積裝置主要包括複數個供氣裝置uo、一個製程反 應室130與一個排氣裝置16〇。其中，供氣裝置包括一個 氦氣(nh3)供應裝置112，用以提供氨氣；一個石夕院(SiH4) 氣體供應裝置114,用以提供矽烷氣體；一個氧化氮（N2〇) 氣體供應裝置116,用以提供氧化氮氣體；以及一個1氣（1^2) 供應裝置118,用以提供氮氣，作為製程反應室中的載氣。 供氣裝置110所提供之氣體均經由輸送管路連接通入製程 反應室130進行反應，藉以沉積形成所需的介電堆疊層。 製程反應室130至少包括一個氣體流量控制盒132與 一個沉積反應室134,並且可將一片半導體晶圓14〇載入， 經濟部智慧財產局員工消費合作社印製 以進行、/儿積製程。供氣裝置1 1 〇所提供之氣體首先進入氣 體流量控制盒1 3 2，使反應氣體在氣體流量控制盒丨3 2中 均勻分布，並且控制氣體進入沉積反應室丨3 4之流量，以 達到高度的均勻性。 7 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公餐） 1241680 A7 B7 五、發明說明（） 藉由控制不同的反應氣體進入沉積反應室丨34中進行 勻相反應’在晶圓140上依序沉積不同的介電層，藉以形 成結構良好的介電堆疊層’而且不需要破壞原有的真空狀 態’也不會有污染的問題發生。 在沉積反應室1 3 4中反應剩餘的氣體經由排氣裝置 160抽出，在沉積反應室134與排氣裝置16〇之間可設置 一個節流閥1 5 0，控制排氣的速率。此外，沉積反應室i 3 4 的底部可以連接一個底部供氣裝置120，對沉積反應室134 的底部供應氮氣（NO，加強沉積反應室1 34底部的排氣能 力。另外，對於氨氣供應裝置112與氧化氮氣體供應裝置 1 1 6可以增加分支管路，直接連接至排氣裝置，並且在管 路上設置閥門，以調節氣體的供應。本發明之沉積裝置的 其他部分與台灣應用材料公司的SiNgen Centura與OxZgen Centura反應室近似，並包含於本文之中，但本發明於此僅 作舉例，並不限定於此種產品，亦可應用於其他近似的產 品，在不脫離本發明之精神之原則下，均在本發明之範圍 内。 第3圖是繪示本發明之一較佳實施例之沉積裝置的操 作圖。請同時參照第2圖與第3圖，首先，將晶圓14〇載 入本發明之沉積裝置中。將沉積裝置之溫度調整到T1，大 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公t ) ---------------^--- 請先閱讀背面之注意事^^!;寫本頁) 訂，· 丨-I線 經濟部智慧財產局員工消費合作社印製 1241680 A7 B7 五、發明說明（） 約為600-8 50 C之間，壓力調整約在〇·〇 1-30torr之間，在 固定溫度與壓力下，由矽烷氣體供應裝置H4與氧化氮氣 體供應裝置1 1 6分別提供矽烷氣體與氧化氮氣體，並可選 擇性地混入氮氣’控制反應氣體濃度，在沉積反應室丨34 中反應持續進行11時間，於晶圓！ 40表面上沉積形成一層 氧化矽層，11時間必須視氧化矽層的厚度決定。接著在不 改變溫度與壓力的情況下，轉換供應氣體，由矽烷氣體供 應裝置1 1 4與氨氣供應裝置丨丨2分別供應矽烷氣體與氨 氣’在沉積反應室1 3 4中持續反應進行12時間，於晶圓1 〇 表面上沉積形成一層氮化矽層，t2時間必須視氮化矽層的 厚度決定。然後再轉換氣體，由矽烧氣體供應裝置1 1 4與 氧化氮氣體供應裝置1 1 6分別提供矽烷氣體與氧化氮氣 體，在沉積反應室134中反應持續進行t3時間，於晶圓140 表面上沉積形成一層氧化石夕層。 請參照第4圖，其繪示關於第3圖之操作條件玉所形 成之結構剖面示意圖。經由上述的步驟，在晶圓丨4 〇戶f包 含之半導體基底200上依序沉積形成氧化矽層212、氮化 石夕層2 1 4與氧化石夕層2 1 6，以構成氧化石夕-氮化石夕-氧化石夕 (ΟΝΟ)介電堆疊層結構。在第4圖中係以快閃記憶體結構 為例，因此ΟΝΟ介電堆疊層是形成在複晶矽層2 1 2上。但 是此ON0介電堆疊層的製造方法亦可應用在其他的產品 上，例如動態隨機存取記憶體（DRAM)的電容器，或是其他 9 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） (請先閱讀背面之注意事寫本頁)Description of the invention (---------------- (Please read the note on the back first? Write this page) The present invention provides a method for forming a dielectric stack layer in a single-reaction chamber and In the device, a dielectric stack layer is formed in a single-reaction chamber, which can improve the production efficiency of making the dielectric layer ... It can prevent the dielectric stack layer from being stained by particles, which affects its structural quality. First, the device structure of the present invention is directed to Please refer to FIG. 2 for a block diagram of a deposition device for forming a dielectric stack layer according to the present invention. The deposition device of the present invention mainly includes a plurality of gas supply devices uo, a process reaction chamber 130 and an exhaust gas Device 16. The gas supply device includes a helium (nh3) supply device 112 for supplying ammonia, a Shixiyuan (SiH4) gas supply device 114 for supplying silane gas, and a nitrogen oxide (N2〇 ) A gas supply device 116 for supplying nitrogen oxide gas; and a 1 gas (1 ^ 2) supply device 118 for supplying nitrogen as a carrier gas in the process reaction chamber. The gas provided by the gas supply device 110 is passed through Conveying pipeline connection to process reaction chamber 1 30 to perform a reaction to deposit a desired dielectric stack layer. The process reaction chamber 130 includes at least a gas flow control box 132 and a deposition reaction chamber 134, and a semiconductor wafer 14 can be loaded. The intellectual property of the Ministry of Economic Affairs Printed by the Consumer Cooperative of the Bureau to carry out the production process. The gas provided by the gas supply device 1 10 enters the gas flow control box 1 3 2 first, so that the reaction gas is evenly distributed in the gas flow control box 3 2 and Control the flow of gas into the deposition reaction chamber 丨 3 4 to achieve a high degree of uniformity. 7 This paper size applies Chinese National Standard (CNS) A4 specifications (210 X 297 meals) 1241680 A7 B7 V. Description of the invention () By Control different reaction gases to enter the deposition reaction chamber 34 for homogeneous reactions 'sequentially deposit different dielectric layers on the wafer 140 to form a well-structured dielectric stack layer' without destroying the original vacuum state 'There is no problem of pollution. The gas remaining in the reaction in the deposition reaction chamber 134 is extracted through the exhaust device 160, and the deposition reaction chamber 134 and the exhaust gas are discharged. A throttle valve 150 can be set between 160 and 160 to control the exhaust rate. In addition, a bottom gas supply device 120 can be connected to the bottom of the deposition reaction chamber i 3 4 to supply nitrogen to the bottom of the deposition reaction chamber 134 ( NO, to strengthen the exhaust capacity at the bottom of the deposition reaction chamber 1 34. In addition, for the ammonia gas supply device 112 and the nitrogen oxide gas supply device 1 1 6 branch pipes can be added, directly connected to the exhaust device, and a valve is provided on the pipeline The other parts of the deposition device of the present invention are similar to the SiNgen Centura and OxZgen Centura reaction chambers of Taiwan Applied Materials Co., and are included in this article, but the present invention is only an example here and is not limited to Such products can also be applied to other similar products, and all are within the scope of the invention without departing from the spirit of the invention. FIG. 3 is an operation diagram of a deposition apparatus according to a preferred embodiment of the present invention. Please refer to FIG. 2 and FIG. 3 at the same time. First, the wafer 14 is loaded into the deposition apparatus of the present invention. Adjust the temperature of the deposition device to T1. The size of the paper is applicable to the Chinese National Standard (CNS) A4 specification (210 X 297 g t) --------------- ^ --- Read the note on the back ^^ !; write this page) Order, · 丨 -I line printed by the Intellectual Property Bureau of the Ministry of Economic Affairs and Consumer Cooperatives 1241680 A7 B7 V. Description of the invention () Between 600-8 50 C, pressure The adjustment is between 0.001-30torr. Under a fixed temperature and pressure, the silane gas supply device H4 and the nitrogen oxide gas supply device 1 1 6 provide silane gas and nitrogen oxide gas, respectively, and nitrogen can be selectively mixed. 'Control the reaction gas concentration, and the reaction continues for 11 hours in the deposition reaction chamber 丨 34, on the wafer! A silicon oxide layer is deposited on the surface of 40, and the time depends on the thickness of the silicon oxide layer. Then, without changing the temperature and pressure, the supply gas is switched, and the silane gas supply device 1 1 4 and the ammonia gas supply device 丨 2 are respectively supplied with the silane gas and ammonia gas. The continuous reaction proceeds in the deposition reaction chamber 1 3 4 At 12 hours, a silicon nitride layer is formed on the surface of the wafer 10, and the time t2 must be determined by the thickness of the silicon nitride layer. Then, the gas is changed, and the silane gas supply device 1 1 4 and the nitrogen oxide gas supply device 1 16 respectively provide silane gas and nitrogen oxide gas, and the reaction continues in the deposition reaction chamber 134 for t3 time on the surface of the wafer 140 Deposition forms a layer of oxidized stone. Please refer to FIG. 4 for a schematic cross-sectional view of the structure formed by the jade with respect to the operating conditions of FIG. 3. Through the above steps, a silicon oxide layer 212, a nitride layer 2 1 4 and a oxide layer 2 1 6 are sequentially deposited on the semiconductor substrate 200 included in the wafer 400 to form an oxide layer- Nitride stone oxide-oxide stone (ONO) dielectric stacked layer structure. In Figure 4, the flash memory structure is taken as an example, so the ONO dielectric stack layer is formed on the polycrystalline silicon layer 2 1 2. However, this ON0 dielectric stack manufacturing method can also be applied to other products, such as dynamic random access memory (DRAM) capacitors, or other 9 paper standards that are applicable to China National Standard (CNS) A4 specifications (210 X 297 mm) (Please read the notes on the back first to write this page)
> · · i n tew n n ϋ ϋ« 一 01 Λβ -I n ϋ ϋ »ϋ ·Βί i met I 經濟部智慧財產局員工消費合作社印製 !241680 A7 B7 " -——^ — --—-------- 五、發明說明（） 類似的產品上 第5圖是繪示本發明之沉積裝置之一變化例的操作 圖，第6圖是繪示關於第5圖之操作條件下所形成之結構 剖面示意圖。請同時參照第2圖、第5圖與第6圖，如前 面實施例所述’在第一層氧化石夕層2 1 2沉積完成之後’加 入一個中間處理步驟，改變通入氣體’以氨氣供應裝置1 1 2 與氧化氮氣體供應裝置116分別提供氨氣與氧化氮氣體， 在沉積反應室1 34中反應持續進行tn時間，在氧化矽層2 1 2 上形成一層薄的氮氧化石夕層2 1 3，然後再進行氮化矽層2 1 4 的沉積。在沉積完氮化矽層2 1 4之後，同樣進行此一中間 處理步驟，在氮化矽層2 1 4上形成一層氮氧化矽層2 1 5， 之後再進行氧化矽層2 1 6的沉積，藉以形成本發明之多層 介電堆疊層結構。由於在乳化石夕層2 1 2、2 1 6與氮化石夕層 2 1 4之間形成氮氧化石夕層2 1 3、2 1 5 ’可以使氧化石夕層與氛 化石夕層之間形成更密合的晶體結構，增進介電堆叠層的電 性操作特性。 經濟部智慧財產局員工消費合作社印製 接著將介紹本發明之另一較佳實施例之操作條件。第7 圖是繪示本發明之另一較佳實施例之操作圖，請同時參照 第2圖與第7圖，首先將晶圓140載入本發明之沉積裝置 中。將沉積裝置之溫度調整到T1，大約為600-85(rc之間， 且較佳是約為750-85(TC之間，壓力調整約在〇 〇N3〇at〇rr 10> · · in tew nn ϋ ϋ «一 01 Λβ -I n ϋ ϋ» ϋ Βί i met I Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs! 241680 A7 B7 " -—— ^ — ---- ------- V. Description of the invention (5) Figure 5 on a similar product is an operation diagram showing a variation of the deposition device of the present invention, and Figure 6 is a diagram showing the operating conditions of Figure 5 Schematic cross-section of the structure formed. Please refer to Fig. 2, Fig. 5 and Fig. 6 at the same time. As described in the previous embodiment, "After the deposition of the first oxide layer 2 1 2 is completed," add an intermediate processing step and change the gas to be passed in to ammonia. The gas supply device 1 1 2 and the nitrogen oxide gas supply device 116 respectively provide ammonia gas and nitrogen oxide gas, and the reaction is continued for tn time in the deposition reaction chamber 1 34 to form a thin layer of oxynitride on the silicon oxide layer 2 1 2 After the layer 2 1 3, a silicon nitride layer 2 1 4 is deposited. After the silicon nitride layer 2 1 4 is deposited, this intermediate processing step is also performed to form a silicon oxynitride layer 2 1 5 on the silicon nitride layer 2 1 4, and then the silicon oxide layer 2 1 6 is deposited. To form the multilayer dielectric stack structure of the present invention. Because the oxynitride layer 2 1 3, 2 1 5 is formed between the emulsified stone layer 2 1 2, 2 1 6 and the nitrided stone layer 2 1 4, the oxidized stone layer and the atmospheric fossil layer can be formed. Form a more compact crystal structure and improve the electrical operating characteristics of the dielectric stack. Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs Next, the operating conditions of another preferred embodiment of the present invention will be described. FIG. 7 is an operation diagram illustrating another preferred embodiment of the present invention. Please refer to FIG. 2 and FIG. 7 at the same time. First, the wafer 140 is loaded into the deposition device of the present invention. The temperature of the deposition device is adjusted to T1, which is about 600-85 (rc, and preferably about 750-85 (TC, the pressure is adjusted to about 〇N3〇at〇rr 10).
1241680 A， Β7 五、發明說明（） --------------^--- (請先閱讀背面之注意事寫本頁) 之間，在固定的溫度與壓力下，由矽烷氣體供應裝置U4 與氧化氮氣體供應裝置1 1 6分別提供矽烷氣體與氧化氮氣 體，在沉積反應室1 3 4中反應持續進行t丨時間，於晶圓1 4〇 表面上沉積形成一層氧化矽層，t丨時間必須視氧化矽層的 厚度決定。接著調整沉積反應室134的溫度T2，大約為 65 0-75 0°C之間，由矽院氣體供應裝置丨14與氨氣供應裝置 1 1 2分別供應矽烷氣體與氨氣，在沉積反應室丨3 4中持續 反應進行12時間’於晶圓1 〇表面上沉積形成一層氣化石夕 層’ t2時間由氮化矽層的厚度決定。之後再調整沉積反應 室134的溫度至T1，由矽烷氣體供應裝置114與氧化氮氣 體供應裝置11 6分別提供矽烷氣體與氧化氮氣體，在沉積 反應室1 3 4中反應持續進行13時間，於晶圓1 4 〇表面上沉 積形成一層氧化矽層，所形成之結構如第4圖所示。在此 溫度操作條件下，ΟΝΟ介電堆疊層可以獲得較佳的時間關 聯介電崩潰（Time dependent dielectric breakdown，TDDB) —··線- 特性，使ΟΝΟ介電堆疊層更加耐久。 同樣地，可以選擇性地在氧化石夕層2 1 2與氮化石夕層2 1 4 /儿積之後’分別加入一個中間處理步驟，在氧化石夕層2 1 4 經濟部智慧財產局員工消費合作社印製 與氛化矽層214,以及氮化矽層214與氧化矽層216之間， 分別形成氮氧化矽層2 1 3與2 1 5，增進介電堆疊層之結構 特性’至於其操作過程’如前所述，因此不再資述。 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） A7 1241680 _B7_ 五、發明說明（） 綜上所述，本發明提供一種單一反應室形成介電堆疊 層的方法及其裝置，可以在同一反應室中依序形成多層不 產響 生影 的， 程染 製污 昇生 提發 以程 可過 ’ 轉 程移 過間 轉中 移為 間因 中統 要傳 需有 不會 , 不 層且 電而 介， 的率 同效 疊 堆 介 之 成 形 所 法 方 之 。 明性 發久 本耐 以與 0 性 題電 問的 Αν σ ΛΟ 力 質更 品得 的獲 層以 電可 介層 所 員 人 之 術 技！ 此例 悉施 熟實 如佳 較 之 已 而 以 用 J.I1 ¥ 並 的 以 本 定 明範 發利 本專 為請 僅申 述之 所明 上發 改 效 等 之 成。 完内 所圍 下範 神利 精專 之請 示申 揭之 所述 明下 發在 本含 離包 脫應 未均 它 ， 其飾 凡修 ; 或 圍變 H ·1 n n i« 1 n L- n n n I · l 1 (請先閱讀背面之注意事項寫本頁) 經濟部智慧財產局員工消費合作社印製 2 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐）1241680 A, Β7 V. Description of the invention () -------------- ^ --- (Please read the note on the back first and write this page), under a fixed temperature and pressure The silane gas supply device U4 and the nitrogen oxide gas supply device 1 16 respectively provide silane gas and nitrogen oxide gas, and the reaction continues in the deposition reaction chamber 1 34 for t 丨 time, and is formed on the surface of the wafer 140 A silicon oxide layer, the time t 丨 must be determined by the thickness of the silicon oxide layer. Next, the temperature T2 of the deposition reaction chamber 134 is adjusted to approximately 65 0-75 0 ° C. Silane gas and ammonia gas supply devices 14 and 1 1 2 are respectively supplied with silicon gas and ammonia gas in the deposition reaction chamber.丨 The continuous reaction in 34 is carried out for 12 hours 'on the wafer 10 to form a layer of gasified rock on the surface of the wafer' t2 time is determined by the thickness of the silicon nitride layer. After that, the temperature of the deposition reaction chamber 134 is adjusted to T1, and the silane gas supply device 114 and the nitrogen oxide gas supply device 116 supply silane gas and nitrogen oxide gas, respectively. The reaction continues in the deposition reaction room 1 3 4 for 13 hours. A silicon oxide layer is deposited on the surface of the wafer 140, and the structure is shown in FIG. 4. Under this temperature operating condition, the ONO dielectric stack can obtain better time-dependent dielectric breakdown (TDDB) ---- line-characteristics, making the ONO dielectric stack more durable. Similarly, you can optionally add an intermediate processing step after the oxidized stone layer 2 1 2 and the nitrided stone layer 2 1 4 / child product, respectively, and consume it at the oxidized stone layer 2 1 4 Cooperative printed and atmosphered silicon layer 214, and between silicon nitride layer 214 and silicon oxide layer 216, respectively forming silicon oxynitride layers 2 1 3 and 2 1 5 to improve the structural characteristics of the dielectric stack layer 'as for its operation The process is as described previously, so it will not be described again. This paper scale is applicable to China National Standard (CNS) A4 specification (210 X 297 mm) A7 1241680 _B7_ V. Description of the invention () In summary, the present invention provides a method and device for forming a dielectric stack layer in a single reaction chamber. , Can be formed in the same reaction chamber in order to produce multiple layers of non-sounding shadows, Cheng Ding pollution ascension promotion process can be passed through the process of moving through the interim transfer to the interim due to the need to transfer , The rate is the same as the method used in the formation of stacked stacks. Brightness and longevity. The resistance is obtained with the Αν σ ΛΟ strength of the 0-point electrical question. The quality of the obtained layer is improved by the skills of the members of the dielectric layer! In this example, it ’s better to use J.I1 ¥ and use the formula of this book to make a profit. This book is only for the purpose of requesting only the stated improvements and improvements. Fan Shenli, who is surrounded by the contents of the document, issued a request for disclosure, which is not included in this document, and it should be decorated in any way; or it will be changed. H · 1 nni «1 n L- nnn I · L 1 (Please read the notes on the back to write this page first) Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs 2 The paper size is applicable to China National Standard (CNS) A4 (210 X 297 mm)