1241008 f"n 14632twf.doc/006 九、發明說明： 【發明所屬之技術領域】 本發明是有關於一種半導體製程，且特別是有關於 一種凸塊製程（bumping process)與電鍍製程（plating process) 〇 【先前技術】 在半導體產業中，積體電路(Integrated Circuits，1C)的 生產，主要分為三個階段：晶圓（wafer)的製造、積體電路 (1C)的製作以及積體電路(ic)的封裳(package)等。其中， 裸晶片（die)係經由晶圓製作、電路設計、光罩多道製程以 及切割晶圓等步驟而完成，而每一顆由晶圓切割所形成的 裸晶片’經由裸晶片上之銲墊（b〇n(jing pad)與承載器 (carrier)電性連接，以形成一晶片封裝結構。此晶片封裝 結構又可區分為：打線接合(wire b〇ncjing)型態之晶片封 裝結構二覆晶接合(flip chip bonding)型態之晶片封裝結構 以及捲帶自動接合(tape automatic b〇nding)之晶片封裝結 構等二大類。在各種型態之晶片封裝結構中，由於凸塊之 訊號傳輸速度快且適用在高密度封裝巾，因此凸塊已成為 晶片與承載主流的電性連接途徑。在早期技術中凸 塊之材質係以錫轉料私，然而切之凸塊對於環境卻 有極^的傷害’因此近年來已朝向無糾塊的趨勢發展。 奋月參考圖1〜圖4，其繪示習知一種晶圓之無錯凸塊 製程的流程剖面圖。首先，請參考圖1，晶圓剛之表面 上全面性形成—球底金屬層（Under Bump Metallurgy， 124101。_6 yBM⑽’並覆蓋一光阻層120於球底金屬層U〇之上。 2考圖2，利用曝光、顯影的成像技術形成多數 曰i^〇f) Γ光阻層120中，且開口 122的位置對應位在 之銲塾搬上。之後，請參考圖3，以光阻層120 ，罩幕(mask)如球底金屬層11G為電難子層進行三次 形ηΓ在開口 122所顯露之球底金屬層110上依序 j錫層I32、銀層m與銅層m。接著，請參考圖4， 除，㈣底金屬層110去 銀層134與銅層136進行迴銲(reflow)， 曰m塊凸塊m可作為晶圓觸上每一 曰曰片（未繪示)對外紐連接—電路板(未繪示)之媒介。 德/翻tl’、m述方式所形成之凸塊13G在迴銲之後錫/ 點Γ产不=無法均勻結合。而且，由於錫/銀/銅各層的熔 在迴鲜的過程中溶點較高的材料就可能 的某一處。不論是上述何種狀況，都 曰4成無錯凸塊之可靠度的下降。 、 【發明内容】 材質在独-種頻餘，適於形成 圓之製裎，適於在晶 曰圓本提出一種凸塊製程，包括下列步驟：提供-曰曰囫’晶圓上具有多個銲塾；在晶圓 形成多個開口於光阻層中，且每-開口顯露== 1241 哪_。_6 一，在開口内之銲墊上形成多個第一合金塊，·在第一合金 塊上形成多個第二合金塊；最後，去除光阻層。 口 依照本發明的較佳實施例所述，在提供晶圓之後以 及形成光阻層之前，可更在晶圓上形成一重配置線路層 (re-distdbuticm layer，RDL)，而銲墊係位於重配置線路^ 上。其中，形成重配置線路層之方式例如係濺鍍、蒸鑛或 電鍍。此外，在形成重配置線路層之後以及形成光阻^之 前，例如更形成一球底金屬層於重配置線路層上，且^口 顯露出球底金屬層之部分表面。 或者’在提供晶圓之後以及形成光阻層之前，可在 晶圓上形成一球底金屬層，且開口顯露出球底金屬層之部 分表面。 在上述形成有球底金屬層之實施例中，形成第一合 金塊之方法例如係以球底金屬層為電鍍種子層而進行電 鑛，並將晶圓浸入於一電鍍液中，以使錫與銅之析出物附 著於球底金屬層上，而形成第一合金塊。此外，形成第二 合金塊之方法例如係以球底金屬層為電鍍種子層而進行電 鍍，並將晶圓浸入於一電鍍液中，以使錫與銀之析出物附 著於第一合金塊上，而形成第二合金塊。 或者，形成第一合金塊之方法例如係以球底金屬層 為電鍍種子層而進行電鍍，並將晶圓浸入於一電鍍液中， 以使錫與銀之析出物附著於球底金屬層上，而形成第一合 金塊。此外，形成第二合金塊之方法例如係以球底金屬層 為電鍍種子層而進行電鍍，並將晶圓浸入於一電鍍液中， 1241008 14632twf.doc/006 以使錫與銅之析出物附著於第一合金塊上，而形成第二合 金塊。 另外，在去除光阻層之後，例如更移除未被第一合 金塊所覆蓋之球底金屬層。 再者，形成第二合金塊之後例如更迴銲第一合金塊 與第二合金塊。此外，在形成第一合金塊時，第一合金塊 例如未填滿開口。 本發明另提出一種電鍍製程，其適於在一晶圓上方 之一光阻層的多個開口中進行。其中，晶圓上具有多個銲 墊，一導體層配置於晶圓上且覆蓋銲墊，而光阻層之開口 係位於銲墊上方。此電鍍製程包括下列步驟：以導體層為 ，鍍種子層而進行電鍍，而在開口内之導體層占形成多個 第一合金塊；之後，以導體層為電鍍種子層而進行電鍍， 而在第一合金塊上形成多個第二合金塊。 依照本發明的較佳實施例所述，在形成第一合金塊 時’第一合金塊例如未填滿開口。 此外，形成第一合金塊之方法例如係以導體層為電 錢種子層而進行電鍍，並將晶圓浸入於一電鍍液中，以使 锡與銅之析出物附著於導體層上，而形成第一合金塊。另 外形成第二合金塊之方法例如係以導體層為電鍍種子層而 進行電鍍，並將晶圓浸入於一電鍍液中，以使錫與銀之析 出物附著於第一合金塊上，而形成第二合金塊。 或者，形成第一合金塊之方法例如係以導體層為電 錢種子層而進行電鍍，並將晶圓浸入於一電鍍液中，以使 1241008 14632twf.doc/006 錫與銀之析出物附著於導體層上，而形成第一合金塊。此 外，形成第二合金塊之方法例如係以導體層為電鍍種子層 而進行電鍍，並將晶圓浸入於一電鍍液中，以使錫與銅之 析出物附著於第一合金塊上，而形成第二合金塊。 綜上所述，本發明之凸塊製程與電鍍製程可提高晶 片與承載器之間以凸塊進行電性連接的可靠度。 為讓本發明之上述和其他目的、特徵優點能更明 顯易懂，下文特舉較佳實施例，並配合所附圖式，作詳細 說明如下。 【實施方式】 請參考圖5〜圖U，其繪示本發明一實施例之凸塊 製程的流程剖面圖。首先，請參考圖5，提供一晶圓細， 而晶圓2GG上具有多數個銲塾搬，其顯露於保護層綱 之開口中。接著，請參考® 6，例如在晶圓2〇〇之表面上 全面性形成-球底金屬層210，而球底金屬層训例如是 Hi飢、鉻等金屬所組成多層金屬層。其巾，球底金 :Μ如以濺鑛、蒸鐘或電錢的方式形成於晶圓200 之表面上，以作為後續進行電鍍處理之種子層。 外圓細之主動表面因應不同接點位置的晶 : σ ，作一重配置線路層（未繪示），並在重配置線 成上述球底金屬層210,以進行後續之電G ，、t墊2〇2係位於重配置線路層上。 括日ίί，參考圖7’形成一光阻層220於晶圓200上， 、’ 〇曝光、顯影的成像技術或其他方式形成多個開 124101- 口 222於光阻層220中，而每一個開口 222皆位於一個鲜 墊202上方。此外，若未形成球底金屬層21〇時，則每一 個開口 222皆顯露一個銲塾202上方。其中，光阻層22〇 例如疋由液態光阻或乾膜(djyfllm)所形成。 接著，請參考圖8，在每個開口 222内之銲墊202上 方的球底金屬層210上形成一個第一合金塊232。其中， 形成第一合金塊232之方法例如係以球底金屬層21〇為電 鍍種子層而進行電鍍，並將晶圓200浸入於一電鍍液中， 以使錫與銅之析出物附著於球底金屬層210上，而形成第 一合金塊232。其中，第一合金塊232例如未填滿開口 222， 而其高度可藉由改變電鍍液中錫離子與銅離子之濃度、電 流時間/安培數等參數而進行控制。 接著，請參考圖9，在每個第一合金塊232上形成一 個第二合金塊234。其中，形成第二合金塊234之方法例 如係以球底金屬^ 210 $電鑛種子層而進行電鍵，並將晶 圓200浸入於一電鍵液中，以使錫與銀之析出物附著於第 一=金塊232+上，而形成第二合金塊234。第二合金塊234 之同度同樣藉由改變電鍍液中錫離子與銀離子之濃度、電 流時間/安培數等參數而進行控制。 、值得注意的是，雖然、在圖8與圖9之說明中係以形 成錫銅材質之第-合金塊232以及锡銀材質之第二合金塊 234為例’但亦可先形成錫銀材質之第一合金塊况，之 後再形成錫銅材質之第二合金塊234。當然，第一合金塊 232與第一合金塊234之材質也不偈限於錫銅合金與錫銀 I241QQLf.d〇c/〇〇6 i金第而其他適當之合金材質。其中，基於環保考 1 / -合金塊232與第二合金塊234 = 之合金材質為佳。 何貝係以不3鉛 ，著’請參考圖9與圖1〇，去除光阻層22〇 法例如是= 移除部分球底金屬層210之方 盘第最ί今iti圖1G與圖U，例如對第—合金塊232 時t 迴鲜’以形成球狀的凸塊230。此 】由於錫/銀/銅已分別以合金型態存在第—合金塊况 銀中’因此在迴焊之後就可輕易獲得錫/ 全塊，:由凸蜂？30。當然，不論是何種材質之合 於塊的材質均勻性皆可明顯優 均勻性。再加以迴銲所獲得之凸塊的材質 圓^本發明一實施例之電鑛製程適於在一晶 晶圓t 層220的多個開口 222中進行。其中， ^球底+屬爲具有多個鲜塾2〇2，一導體層(例如圖中緣示 光阻声22^ 〇)配置於晶圓2〇0上且覆蓋銲墊202，而 此電“ r : = 口？2係位於銲墊202上方。請參照圖8， 而在；二22以導體層210為電鍍種子層而進行電鍍， 232 導體層210上形成多個第一合金塊 行電/ 9’以導體層210為電鍍種子層而進 X在母個第—合金塊232上形成一個第二合金塊 1241008 14632twf.doc/006 234。 •雖然本實施例之電鍍製程係搭配前一實施例之凸塊 製程做介紹，但本發明之電輕程並不偈限於應用 製程中。 尾 綜上所述，在本發明之凸塊製程與電鍍製程中，由 於直接形成兩種合金塊，而非形成單一材質之金屬塊，因 此兩種合金塊在後續進行迴銲之後可獲得充分混合，進而 提高晶片與承載器之間以凸塊進行電性連接的可靠度。 雖然本發明已以較佳實施例揭露如上，然其並非用 以限定本發明，任何熟習此技藝者，在不脫離本發明之精 神和範圍内，當可作些許之更動與潤飾，因此本發明之= 遵範圍當視後附之申請專利範圍所界定者為準。 【圖式簡單說明】 圖1〜圖4繪示為習知一種晶圓之無鉛凸塊製程的流 程剖面圖。 圖5〜圖11繪示為本發明一實施例之凸製程及豆 所採用之電鍍製程的流程剖面圖。 、 八 【主要元件符號說明】 100 晶圓 102 銲墊 110 球底金屬層 120 光阻層 122 開口 130 凸塊 132 錫層 12 1241008 14632twf.doc/006 134 ： 銀層 136 ： 銅層 200 ： 晶0 202 ： 銲墊 204 ： 保護層 210 ： 球底金屬層 220 ： 光阻層 222 ： 開口 230 ： 凸塊 232 ： 第一合金塊 234 ： 第二合金塊1241008 f " n 14632twf.doc / 006 IX. Description of the invention: [Technical field to which the invention belongs] The present invention relates to a semiconductor process, and in particular to a bumping process and a plating process 〇 [Previous technology] In the semiconductor industry, the production of integrated circuits (1C) is mainly divided into three stages: wafer (wafer) manufacturing, integrated circuit (1C) manufacturing, and integrated circuit ( ic) package and so on. Among them, the die is completed through the steps of wafer fabrication, circuit design, photomask multiple processes, and wafer dicing, and each bare wafer formed by wafer dicing is processed by soldering on the bare wafer. The pad (jing pad) is electrically connected to the carrier to form a chip packaging structure. This chip packaging structure can be further divided into: wire bONC Jing type chip packaging structure 2 There are two types of flip chip bonding chip packaging structures and tape automatic bunding chip packaging structures. In various types of chip packaging structures, signal transmission due to bumps It is fast and suitable for high-density packaging towels, so bumps have become the electrical connection between the chip and the mainstream. In the early technology, the material of the bumps was tin-to-material. However, the cut bumps are extremely environmentally friendly. Therefore, in recent years, there has been a trend toward no block correction. Fen Yue refers to FIG. 1 to FIG. 4, which show a cross-sectional view of a conventional wafer error-free bump process. First, please refer to FIG. 1. ,crystal Fully formed on the surface of the surface-ball-bottom metal layer (Under Bump Metallurgy, 124101. _6 yBM⑽ 'and cover a photoresist layer 120 above the ball-bottom metal layer U0. 2 Consider Figure 2, using the imaging technology of exposure and development The majority of the photoresist layer 120 is formed, and the position of the opening 122 is correspondingly moved on the welding pad. After that, please refer to FIG. 3. With the photoresist layer 120, the mask is like a ball bottom. The metal layer 11G is a sublayer of electric difficulty. The shape ηΓ is sequentially formed on the ball-bottom metal layer 110 exposed in the opening 122. The tin layer I32, the silver layer m, and the copper layer m are in order. Next, please refer to FIG. The metal layer 110 is deflowed to the silver layer 134 and the copper layer 136 for reflow. The m bumps m can be used as a wafer to contact each wafer (not shown). ). The 13G bumps formed in the German / Turn tl ', M method described above can not be uniformly combined after the solder / point Γ production is not equal. Moreover, because the tin / silver / copper layers are fused during the refreshing process A material with a higher medium melting point may be somewhere. Regardless of the above-mentioned conditions, the reliability of 40% error-free bumps is reduced. SUMMARY OF THE INVENTION The material is unique and suitable for the formation of a round wafer. It is suitable for presenting a bump process in a crystal wafer. The process includes the following steps: providing a wafer with a plurality of solder wafers. ; Multiple openings are formed in the photoresist layer on the wafer, and each opening is exposed == 1241 which _._ 6 First, a plurality of first alloy blocks are formed on the pads in the openings, and · are formed on the first alloy block Multiple second alloy blocks; finally, removing the photoresist layer. According to the preferred embodiment of the present invention, after the wafer is provided and before the photoresist layer is formed, a reconfiguration circuit layer may be further formed on the wafer ( re-distdbuticm layer (RDL), and the pads are located on the reconfiguration line ^. Among them, the method of forming the reconfigured circuit layer is, for example, sputtering, vapor deposition, or electroplating. In addition, after the reconfiguration circuit layer is formed and before the photoresist is formed, for example, a ball-bottom metal layer is further formed on the reconfiguration circuit layer, and a part of the surface of the ball-bottom metal layer is exposed. Alternatively, after the wafer is provided and before the photoresist layer is formed, a ball-bottom metal layer may be formed on the wafer, and the opening may expose a part of the surface of the ball-bottom metal layer. In the above embodiment in which the ball-bottom metal layer is formed, the method for forming the first alloy block is, for example, performing electro-mineralization using the ball-bottom metal layer as a plating seed layer, and immersing the wafer in a plating solution to make tin Precipitates with copper adhere to the ball-bottom metal layer to form a first alloy block. In addition, the method for forming the second alloy block is, for example, electroplating using a ball-bottom metal layer as a plating seed layer, and immersing the wafer in a plating solution so that the precipitate of tin and silver adheres to the first alloy block. To form a second alloy block. Alternatively, the method for forming the first alloy block is, for example, electroplating by using a ball-bottom metal layer as a plating seed layer, and immersing the wafer in a plating solution, so that the precipitate of tin and silver adheres to the ball-bottom metal layer. To form a first alloy block. In addition, the method for forming the second alloy block is, for example, electroplating with a ball-bottom metal layer as a plating seed layer, and immersing the wafer in a plating solution, 1241008 14632twf.doc / 006 to adhere the tin and copper precipitates. A second alloy block is formed on the first alloy block. In addition, after removing the photoresist layer, for example, the ball-bottom metal layer not covered by the first alloy block is further removed. After the second alloy ingot is formed, for example, the first alloy ingot and the second alloy ingot are re-soldered. In addition, when the first alloy block is formed, the first alloy block does not fill the opening, for example. The invention further provides a plating process, which is suitable to be performed in a plurality of openings of a photoresist layer above a wafer. The wafer has a plurality of solder pads, a conductor layer is disposed on the wafer and covers the solder pads, and the opening of the photoresist layer is located above the solder pads. The electroplating process includes the following steps: plating is performed by using a conductor layer as a seed layer, and a plurality of first alloy blocks are formed by the conductor layer in the opening; and thereafter, the conductor layer is used as a plating seed layer and electroplating is performed, and A plurality of second alloy blocks are formed on the first alloy block. According to a preferred embodiment of the present invention, when the first alloy block is formed, the first alloy block does not fill the opening, for example. In addition, the method for forming the first alloy block is, for example, electroplating using a conductor layer as an electric seed layer, and immersing the wafer in a plating solution, so that the precipitate of tin and copper adheres to the conductor layer, and is formed. First alloy block. In addition, the method for forming the second alloy block is, for example, electroplating using a conductor layer as a plating seed layer, and immersing the wafer in a plating solution, so that the precipitate of tin and silver adheres to the first alloy block, and is formed. Second alloy block. Alternatively, the method for forming the first alloy block is, for example, electroplating using a conductor layer as a seed layer of electricity, and immersing the wafer in a plating solution so that the precipitate of tin and silver adheres to 1241008 14632twf.doc / 006 On the conductor layer to form a first alloy block. In addition, the method for forming the second alloy block is, for example, electroplating by using the conductor layer as a plating seed layer, and immersing the wafer in a plating solution so that the precipitate of tin and copper adheres to the first alloy block, and A second alloy block is formed. In summary, the bump manufacturing process and the plating process of the present invention can improve the reliability of the electrical connection between the wafer and the carrier by the bumps. In order to make the above and other objects, features, and advantages of the present invention more comprehensible, preferred embodiments are described below in detail with the accompanying drawings, as follows. [Embodiment] Please refer to FIG. 5 to FIG. U, which are cross-sectional views showing a process of a bump manufacturing process according to an embodiment of the present invention. First, please refer to FIG. 5, a wafer is provided. The wafer 2GG has a plurality of solder pads, which are exposed in the openings of the protective layer. Next, please refer to ® 6, for example, a ball-bottom metal layer 210 is formed on the surface of the wafer 200 in a comprehensive manner, and the ball-bottom metal layer is a multilayer metal layer composed of a metal such as Hi, chrome, and the like. The towel, ball-shaped gold: M is formed on the surface of the wafer 200 in the manner of splattering, steaming bell or electric money, as a seed layer for subsequent plating treatment. The active surface of the thin outer circle corresponds to the crystals at different contact positions: σ, and a reconfiguration circuit layer (not shown) is formed, and the reconfiguration line is formed into the above-mentioned ball-bottom metal layer 210 for subsequent electric power G, t pad The 202 series is located on the reconfiguration line layer. For example, referring to FIG. 7 ′, a photoresist layer 220 is formed on the wafer 200, and a plurality of openings 124101-ports 222 are formed in the photoresist layer 220 by imaging techniques such as exposure and development, and each The openings 222 are all located above a fresh pad 202. In addition, if the ball-bottom metal layer 21 is not formed, each of the openings 222 is exposed above a welding pad 202. The photoresist layer 22 is formed of, for example, a liquid photoresist or a dry film (djyfllm). Next, referring to FIG. 8, a first alloy block 232 is formed on the ball-bottom metal layer 210 above the pad 202 in each opening 222. Among them, the method for forming the first alloy block 232 is, for example, electroplating with the ball-bottom metal layer 21 as a plating seed layer, and immersing the wafer 200 in a plating solution to make the precipitates of tin and copper adhere to the balls. The first metal block 232 is formed on the bottom metal layer 210. Among them, the first alloy block 232 does not fill the opening 222, for example, and its height can be controlled by changing parameters such as the concentration of tin ions and copper ions in the plating solution, current time / amperage, and the like. Next, referring to FIG. 9, a second alloy block 234 is formed on each of the first alloy blocks 232. Among them, the method of forming the second alloy block 234 is, for example, performing electric bonding with a ball-bottom metal ^ 210 $ electric ore seed layer, and immersing the wafer 200 in an electric key liquid so that the precipitate of tin and silver adheres to the first 1 = on the gold block 232+, and the second alloy block 234 is formed. The same degree of the second alloy block 234 is also controlled by changing parameters such as the concentration of tin ions and silver ions in the plating solution, and the current time / amperage. It is worth noting that although the description of FIGS. 8 and 9 is based on the formation of the first alloy block 232 of tin-copper material and the second alloy block 234 of tin-silver material as examples, it is also possible to form a tin-silver material first. The second alloy block 234 made of tin-copper material. Of course, the materials of the first alloy block 232 and the first alloy block 234 are not limited to tin-copper alloy and tin-silver I241QQLf.doc / 〇〇6 and other appropriate alloy materials. Among them, the alloy material based on the environmental protection test 1 /-alloy block 232 and the second alloy block 234 = is preferred. He Bei does not use 3 lead, please refer to FIG. 9 and FIG. 10. The method of removing the photoresist layer 22 is, for example, removing part of the square bottom metal layer 210 of the square plate. FIG. 1G and FIG. For example, the first alloy block 232 is refreshed at t to form a spherical bump 230. [This] Since tin / silver / copper has existed in the form of alloys—the first alloy block condition in silver ’, so tin / full block can be easily obtained after re-soldering: 30. Of course, no matter what kind of material is, the uniformity of the material can obviously be better. Furthermore, the material of the bumps obtained by the re-welding is round. The electro-mineralization process according to an embodiment of the present invention is suitable for being performed in the plurality of openings 222 of the t-layer 220 of a crystal wafer. Among them, ^ Bottom + belongs to a plurality of fresh 塾 202, a conductor layer (for example, the photoresistance sound 22 ^ 〇 shown in the figure) is arranged on the wafer 2000 and covers the pad 202, and this electric "R: = 口? 2 is located above the bonding pad 202. Please refer to FIG. 8, and perform electroplating using the conductor layer 210 as the plating seed layer, and a plurality of first alloy blocks are formed on the conductor layer 210. / 9 'with the conductor layer 210 as the plating seed layer and X to form a second alloy block on the first-alloy block 232 1241008 14632twf.doc / 006 234. • Although the plating process of this embodiment is implemented in conjunction with the previous one The bump process of the example is described, but the electric light range of the present invention is not limited to the application process. As mentioned above, in the bump process and electroplating process of the present invention, two kinds of alloy blocks are directly formed, and It does not form a metal block of a single material, so the two alloy blocks can be fully mixed after subsequent re-soldering, thereby improving the reliability of the electrical connection between the wafer and the carrier by the bump. Although the present invention has better The examples are disclosed as above, but they are not intended to limit the present invention. Anyone who is familiar with this technique can make some modifications and retouching without departing from the spirit and scope of the present invention. Therefore, the scope of the present invention = compliance scope shall be determined by the scope of the attached patent application. Brief description] Figures 1 to 4 are cross-sectional views of a conventional lead-free bump manufacturing process for wafers. Figures 5 to 11 are schematic views of a bump process and an electroplating process used for beans according to an embodiment of the present invention. [Cross section of the process.] [Description of main component symbols] 100 Wafers 102 Welding pads 110 Metal bottom layer 120 Photoresist layer 122 Opening 130 Bump 132 Tin layer 12 1241008 14632twf.doc / 006 134: Silver layer 136: Copper layer 200: Crystal 0 202: Welding pad 204: Protective layer 210: Spherical metal layer 220: Photoresist layer 222: Opening 230: Bump 232: First alloy block 234: Second alloy block