TWI240383B - Layout for memory cells - Google Patents

Abstract

The present invention provides a layout for memory cells, which includes a plurality of word lines, a plurality of first source/drain lines, a plurality of second source/drain lines, and a plurality of memory cells, wherein each memory cell has a gate structure coupled to one of the word lines; a first source/drain area coupled to one of the first source/drain lines or the first bit lines; a first spacer between the first source/drain area and the gate for storing electrons or charges; and a second source/drain area coupled to one of the second source/drain lines or the second bit lines; and a second spacer between the second source/drain area and the gate for storing electrons or charges.

Description

1240383 V. Description of the invention (1) The technical field of the invention belongs to the Yuan ::: has a unit 'especially a memory of a single unit that can process the amount of data logical bit 7 " memory', which effectively increases the memory. The previous technology can also maintain Er Chu accepts the baby. "Belonging to" is non-volatile, even if the power is cut off, the data is a mask; two / can be divided according to whether the stored data can be erased / Λ sk deleted), erasable read-only memory (Flash Μ) can erase the read-only memory (EEPR〇M), flash memory helmet Memory). Among them, once the Mask Rom data is written: remember mass production, low cost, high reliability And large-capacity n (f) i · Flash memory uses data to inject or pull electrons out of the floating g gate for data storage, and is both non-volatile and capable of ... Data: enable data to be stored without power, but Also, refer to Figure 1a, which is a diagrammatic representation of the conventional flash memory memory. When the conventional flash memory is intended to be programmed, it will be m and please. U on When a high voltage is applied, the electrons pass from: two = / and the pole 1 0 1 a through the gate oxide layer 1 〇2 and enter the floating gate 1 〇3.… ...: Figure 1b, Figure 1b shows the habit The known flash memory is recorded in the early erasing diagram. When the conventional flash memory is to be erased, it is applied to the control gate 105. Or zero voltage at the drain electrode of the silicon based substrate ι〇ι "Η Shi

1240383 V. Description of the invention (2) · When the voltage is increased, the electrons pass from the floating gate 丨 03 through the gate oxide 丨 02 and return to the sum electrode 1 0 1 a. It can be known that the conventional flash memory can be programmed or erased a group of data at a time. Therefore, the number of memory units in the entire flash memory can be programmed or erased at the same time. Number of processed data sets. Figure 1c is a schematic diagram showing the process behind the conventional mask-only read-only memory unit. First, provide a silicon substrate 1 2 0 formed with a memory cell such as a MOS transistor, and an oxide layer 2 2 is formed on the silicon substrate 2 2. The memory cell has a gate 1 2 3 and a source drain. 1 2 1 a, 1 2 1 b. Among them, the gate electrode 1 2 3 is, for example, a polycrystalline layer; the source drain 丨 2 1 a, 1 2 1 b may be a p + diffusion region or an n + diffusion region, and the n + diffusion region is shown in FIG. 1 c. . Then, a photolithography process is performed using a coded mask (c 0 demask) to form a patterned photoresist layer on part of the gates 1 2 3 and the source and drain electrodes 1 2 1 a, 1 2 1 b, and then there is a memory for the formation The silicon substrate of the cell is subjected to channel implantation to complete the coding of the memory cell. When the gate 1 2 3 of the memory cell is not covered by the patterned photoresist layer, the channel region 1 2 4 will be implanted to define the memory cell as "丨"; otherwise, when the gate 1 2 of the memory cell is 3 When covered with a patterned photoresist layer, the channel area 1 2 4 will not be implanted and the memory unit is defined as coded as “0”. The implantation programming of the memory unit is performed in the middle of the manufacturing process 'To drive ions into the channel region (C ha η ne 1 Region) to adjust the starting voltage vt (Threshold Voltage), the process

0748-9572TlVF (nl); Claire.pt (l page 6 1240383 V. Description of the invention (3) The formulating step is after the M0S transistor is made and the contact (contact) or inner layer dielectric material (Inter Layer Di (Electri CS) is executed before the formation. When producing the chip structure of the mask-type read-only memory (R0M), in addition to making the chip according to the program code in a short time, the area of the memory cell needs to be reduced to According to the above description, it is obvious that there is still room for improvement in the conventional technology. SUMMARY OF THE INVENTION In view of this, the object of the present invention is to provide a layout of a multi-bit memory unit, and improve the layout of the memory unit through different layout structures. Density 'increasing the number of bits for processing data' raises the amount of data that can be processed by flash memory or mask-only read-only memory. According to the above purpose, the present invention provides a layout of a memory unit, including a complex digital element line; Plural first sources / ;: and polar lines; plural second sources / non-polar lines; and plural memory cells, each memory cell having: a gate structure coupled to one of the word lines; a first source / A polar region, which is coupled to one of the first source / non-polar line or the first bit line, and has a first gap wall between the first source / drain region and the gate electrode, and the first gap wall is used for storing electrons Or charge, and a second source / drain region, coupled to one of the second source / drain line or the second bit line, and a second gap between the second source / drain region and the gate According to the above purpose, the present invention further provides a layout of a memory cell, including: a complex digital line; a complex first source / drain line; a complex second source / drain line Polar lines and plural memory cells, each memory cell has: a gate surname structure connected to one of the character lines; a first source / drain region, coupled \

0748-9572TWF (nl); Claire.ptd Page 7 1240383 V. Description of the invention (4) ^ :: original source and polar line or -bit line Among them-. 1 禺 妾 to-source / drain line Or _ γ and a second source / drain: one of the 'inter-pole structure and the first-source / drain element line; it has a β-source / drain interval that can be selectively formed or programmable Each has a memory electronic signal. The drain extension area is used to store or according to the above-mentioned purpose, the present invention further includes: a complex number element line; a complex number, a layout of a memory unit, an epipolar line; and a complex number memory unit, a = / and an extreme line; Two source / drain structure, coupled to one or two of the character line 1, the unit has: a gate junction: source / drain line or first-: one of the first line of the yuan line, lightly connected to the first area , Which is coupled to the second source / sink = and-the second source drain, the gate structure is one of the 5th bit line; the other is an anti-dazzle wire. The source-source and polar regions or the second source-drain region have characteristics, and advantages, respectively, and can be more clear and coordinated with the attached drawings to make the above and other objects of the present invention easier to understand. The following is enumerated-preferred implementation Fang Yang's detailed description is as follows: Implementation: Please consider Figure 2a. Figure 2a is a schematic cross-sectional view showing the multi-bit erasable memory unit of the present invention. , ...

The multi-bit memory cell of the present invention includes a semiconductor substrate 201 forming an active / drain region S / D. A gate electrode 202 is formed on the semiconductor substrate 201, and a gate dielectric layer 203a is formed between the gate electrode 202 and the semiconductor substrate 201; and a gap wall 2 is formed on the side wall of the intermediate electrode 202. 4. The barrier wall 204 is used to store electrons or charges, and an oxide layer is formed between the barrier wall 204 and the gate electrode 202.

1240383 V. Description of the invention (5) 20 3b; Moreover, a metal silicon and a compound layer 2 05 are formed on the gate electrode 20 2 and the source / drain region S / D. The semiconductor substrate 201 is, for example, a silicon substrate; the gate and 202 are, for example, a polycrystalline silicon layer; the gate dielectric layer 203a is, for example, a gate oxide layer; and the spacer 2 is, for example, a nitride layer; a metal The stone oxide layer 2 05 is, for example, Tisi2, cobalt disilicon (coSi2), or nickel silicide (NiSi). Next, a dielectric layer such as a hafnium oxide layer is formed on the semiconductor substrate 201 and the above-mentioned components, and a trench is defined on the dielectric layer to expose the source / drain region S / between the gates 202. The surface of D; then, a conductive layer is filled in the trench as a contact plug to be conductive with the bit line formed later. Please refer to Fig. 2b. Fig. 2b is a schematic cross-sectional view showing the multi-bit mask of the present invention. A gate dielectric layer 222a and an interrogation electrode 2 = 3 are formed on the semiconductor substrate 220 of the present invention. A photoresist layer formed using a coded photomask and the gate electrode 223 are used as a mask, and the half-body substrate 2 2 0 is doped. Steps to form a source / drain extension region 221 (source / drain extens ion) on the semiconductor substrate 2 2 0 on the side of the gate 2 2 3, and then, a gap 224 is formed on a side wall of the gate 223, and An oxide layer 2221 is formed between the partition wall 2 24 and the gate electrode 2 23. The gate electrode 223 and the source // and the electrode region S / D are opened to form a metal silicide layer 2 2 5. The gate electrode 2 2 3 and the spacer m are used as a mask to perform an ion implantation step on the semiconductor substrate 22 to form a source / drain region «S / D ° ,, Because when reading data, if the source / drain region S / D and the gate electrode 223 are passive and extended, the starting voltage of the memory cell will be larger. Therefore, a general value is applied to the gate electrode 223 Read voltage Risi, source / drain region s /]) None ·

1240383 V. Description of the invention (6)-The method is turned on, and there is only a small leakage current or a secondary start current, so it will be read out. If there is an active drain region 2 2 1 between the source / drain region S / D and the gate 223, the starting voltage can be smaller. Therefore, when a general value reading is applied to the gate u 3 At the voltage, the source / drain region s / D can conduct current, so it will read "1". Therefore, we can say that when there is a source-drain extension region 2 2 1 formed to abut the gate 2 2 3 , It will be defined as coded as "factory; on the contrary, when there is no source-drain extension 2 2 1 to be adjacent to gate 2 2 3, it will be defined as coded as " 〇π. Figure 2c, Figure 2c is a schematic cross-sectional view of a read-only memory cell of the One-Time Programmable (OTP) Anti-fuse of the present invention. A semiconductor substrate of the present invention is formed on 230 A gate dielectric layer 2 32a and a gate electrode 23 3 are used, and the gate electrode 233 is used as a mask to perform a doping step on the semiconductor substrate 2 3 0 to form a semiconductor substrate 2 3 0 on the side of the gate 2 3 3. Source drain extension region 231 (source / drain extension); Next, a gap wall 2 3 4 is formed on the side wall of the gate electrode 233, and the gap wall 2 3 4 and the gate electrode 2 3 3 are formed. There is an insulating layer 2 3 2b. A metal silicide layer 23 5 is formed on the gate 2 33 and the source / drain region S / D. The semiconductor substrate 2 3 0 is ionized with the gate 2 33 and the spacer 234 as a mask. An implantation step to form the source / drain region S / D on the semiconductor substrate 230. After the heat treatment, the source / drain extension region 231 will diffuse below the gate 23 3, resulting in the gate 23 3 and the source / drain extension region. There is only a gate dielectric layer 232c spaced between 23, and a portion of the gate dielectric layer 2c 32c can be selectively applied with a high electric field to cause it to collapse and cause leakage, which is used as an anti-fuse memory.

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The anti-fuse is straight when reading the record and the technique; 愔 1 If there is no collapse between the source / drain region S / D and the gate 233, there is very little leakage current ^; V source has no pole region 8/1) There is p between S / D and gate 3 which cannot be guided. ^ This will read ', G ". And if the source drain region has a large leakage current, 0 this =: Beizhi anti-refining silk, then the memory cell's collapse will apply a normal reading voltage on the gate 233: 'source drain region S / D has a large amount of leakage current, so τ is read out. Because we can δ 'when there is a collapsed anti-fuse adjacent to the gate 2 3 3 τ, it will be defined as the code "丨"; conversely, when no collapsed f-fuse and the gate 2 3 3 are formed When they are adjacent, they will be defined as "0 ,." For the first embodiment, please refer to Figs. 3a-3c. Fig. 3a is a schematic diagram showing the first embodiment of a single multi-bit memory cell according to the present invention. Fig. 3b is a schematic diagram showing the layout of the multi-bit memory unit of the present invention, and Fig. 3C is an equivalent circuit diagram showing the layout of the multi-bit memory unit of Fig. 3b. Please refer to Fig. 3a 'first to provide a A semiconductor substrate (not shown), a multi-bit memory cell as shown in Figure 2a or 2b is formed on the semiconductor substrate, and an active area 30 is defined on the multi-bit memory cell. Among them, a single multi-bit memory The layout of the cell includes a word line WL1, a first bit line BL3 and a second bit line BL4, and a first contact C1 and a second contact C2; wherein the word line is the gate The wire, the contact is the contact plug. Word line WL1, first bit line BL3, second bit line BL4 Perpendicularly intersect, and the first bit line BL3 and the second bit line BL4 are parallel to each other, and the first bit line BL3

0748-9572TWF (nl); Claire.ptd Page 11 1240383 V. Description of the invention (8) Bit line BL3 and second bit line BL4 are separated by word line WL1 to two sides. The first contact C1 is electrically connected to the first bit line B L3, the second contact C2 is electrically connected to the second bit line BL4, and the first contact C1 and the second contact C2 are located in characters. Line WL1 separates the different sides. The defined range of the active area 30 includes the above-mentioned components, and the active area 30 is a rectangular active area. The first contact C1 and the second contact C2 are located at diagonal positions of one of the active areas 30, respectively. Please refer to Figs. 3b-3c, which is a schematic diagram showing the layout of the multi-bit memory cell of the present invention, showing word lines WL1, WL2, WL3, bit lines BL1, BL2, BL3, BL4, BL5, BL6, contacts C1, C2, memory cell 301 and active area 30. Among them, the memory cell 301 is a single multi-bit memory cell shown in FIG. 3a, and the diagram in FIG. 3b shows a plurality of memory cells 301. Each contact point can be shared with an adjacent memory cell. In the equivalent circuit diagram of Fig. 3c, it is clearly shown that the second contact C2 of the memory cell 301 is shared with the adjacent memory cell and is electrically connected. For the second embodiment, please refer to Figs. 4a-4c. Fig. 4a is a schematic diagram showing a second embodiment of the layout of a single multi-bit memory cell of the present invention, and Fig. 4b is a diagram showing the multi-bit of the present invention. Schematic diagram of the layout of the memory unit. Figure 4c is an equivalent circuit diagram showing the layout of the multi-bit memory unit in Figure 4b. Please refer to FIG. 4a, which is a schematic diagram showing a second embodiment of the layout of a single multi-bit memory cell according to the present invention. In this embodiment, a semiconductor substrate (not shown) is first provided. A multi-bit memory cell as shown in Figs. 2a and 2b is formed on the semiconductor substrate. An active area 40 is defined on the multi-bit memory cell.

0748-9572TWF (nl); Claire.ptd Page 12 1240383 V. Description of the invention (9) Among them, the layout of a single multi-bit memory cell includes a word line WL1, a 'first bit line BL3 and a first The two-bit line BL4, and a first contact C1 and a first, second contact C2; wherein the word line is the conductor of the gate, and the contact is the contact plug. The word line WL1 intersects the first bit line BL3 and the second bit line BL4 perpendicularly, and the first bit line BL3 and the second bit line BL4 are parallel to each other, and the first bit line BL3 and the second bit line The line BL4 is divided into two sides by a character line WL1. The first contact C1 is electrically connected to the first bit line BL3, the second contact C2 is electrically connected to the second bit line BL4, and the first contact C1 and the second contact C2 are located on the word line WL1 separates the different sides. The defined range of the active area 40 includes the above-mentioned components, and the active area 40 is a rectangular active area and forms a specific angle with the character line WL1. The first contact C1 and the second contact C2 are respectively It is located at both ends of the active area 40. The specific angle between the active area 40 and the word line WL1 is less than 90 degrees. Please refer to FIGS. 4b-4c, which is a schematic diagram showing the layout of the multi-bit memory cell of the present invention, showing word lines WL1, WL2, WL3, boundary [4, bit lines 811, 812, 613, 81 /, contact (: 1, (: 2, memory cell 401 and active area 40. Among them, memory cell 401 is a single multi-bit memory cell shown in Fig. 4a, and the figure in Fig. 4b shows a complex number Each memory cell 4 0 1 can be shared with a neighboring memory cell. The equivalent circuit diagram in Figure 4 c clearly shows that the second contact C 2 of the memory cell 4 0 1 is shared with the neighboring memory cell. And electrical connection. For the second embodiment, please refer to Figs. 5a-5d, and Figs. 5a-5b show a single unit of the present invention.

0748-9572TWF (nl); Claire.ptd Page 13 1240383 V. Description of the invention (ίο) Schematic diagram of the third embodiment of the layout of multi-bit memory cells, Fig. 5 c shows the multi-bit memory of the present invention Schematic diagram of unit layout. Figure 5d is an equivalent circuit diagram showing the layout of the multi-bit memory cell in Figure 5c. Please refer to Figs. 5a-5b, which are schematic diagrams showing a third embodiment of the layout of a single multi-bit memory cell according to the present invention. In this embodiment, a semiconductor substrate (not shown) is first provided. A multi-bit memory cell as shown in FIG. 2 is formed on the semiconductor substrate. An active area 50 is defined on the multi-bit memory cell. Among them, the layout of a single multi-bit memory cell includes a word line WL1, a first bit line BL3 and a second bit line BL4, and a first contact C1 and a second contact C2; Among them, the word line is the wire of the gate; the contact is the contact plug. The word line WL1 intersects the first bit line BL3 and the second bit line BL4 perpendicularly, and the first bit line BL3 and the second bit line BL4 are parallel to each other, and the first bit line BL3 and the second bit line The line BL4 is divided into two sides by a character line WL1. The first contact C1 is electrically connected to the first bit line B L3, the second contact C2 is electrically connected to the second bit line BL4, and the first contact C1 and the second contact C2 are located in characters. Line WL1 separates the different sides. The defined range of the active area 50 includes the above-mentioned components, and the active area 50 is a rectangular active area and forms a specific angle with the character line WL1. The first contact C1 and the second contact C2 are respectively It is located at both ends of the active area 50. The specific angle between the active area 50 and the word line WL1 is less than 90 degrees.

The layout of another single multi-bit memory cell includes a word line WL2, a first bit line B L3 and a second bit line B L4, and a second contact C2 and a third J

0748-9572TWF (nl); Claire.ptd Page 14 1240383 V. Description of the invention (11) Contact C3; where the character line is the conductor of the gate; the contact is the contact plug: plug. The word line WL2 is perpendicular to the first bit line BL3 and the second bit line BL4. The first bit line BL3 and the second bit line BL4 are parallel to each other, and the first bit line BL3 and the second bit line The element line BL4 is divided into two sides by a character line WL2. The second contact C2 is electrically connected to the second bit line BL4, the third contact C3 is electrically connected to the first bit line BL3, and the second contact C2 and the third contact C3 are located on the word line WL2 separates the different sides. The defined range of the active area 50 includes the above-mentioned components, and the active area 50 is a rectangular active area and forms a specific angle with the character line WL2. The second contact C2 and the third contact C3 They are located at two ends of the active area 50, respectively. The specific angle between the active area 50 and the character line WL2 is less than 90 degrees. Please refer to Figures 5 c-5 d. Figure 5 c is a schematic diagram showing the layout of the multi-bit memory cell of the present invention, showing word lines WL1, WL2, WL3, bit lines BL1, BL2, BL3, BL4. , BL5, BL6, contacts C1, C2, C3, memory cell 501 and active area 50. Among them, the memory cell 501 is a single multi-bit memory cell shown in Figs. 5a-5b, and the diagram in Fig. 5c shows a plurality of memory cells 501, and each contact can communicate with the adjacent memory cell. Therefore, each contact can be shared by four memory cells 501. The equivalent circuit diagram in FIG. 5d clearly shows that the second contact C2 of the memory cell 51 is shared with the neighboring memory cell and is electrically connected. For the fourth embodiment, please refer to Figs. 6a-6d. Figs. 6a-6b are schematic diagrams showing a fourth embodiment of the layout of a single multi-bit memory cell according to the present invention, and Fig. 6c is a diagram showing many of the present invention. Schematic diagram of the layout of the bit memory unit, Figure 6d is f

0748-9572TWF (nl); Claire.ptd Page 15 1240383 V. Description of the invention (12) The number of bits shown in Figure 6c is < yin staying; + / die & 丄 ^ Equivalent circuit diagram. Figures 6a to 6b are diagrams showing a fourth embodiment of a single multi-bit = memory cell layout of the present invention. In this embodiment, firstly, a semiconductor conductor substrate is provided with a plurality of memory cells formed on the semiconductor conductor substrate as described in Section 2— ^ ^ + ^ σσ and 3 ζ diagrams. Defined as an active zone. Please refer to Figure 6a. In the basin, g xi yi yi ## 1 ^ Among them, the layout of multiple memory cells earlier includes a child line WL, a younger one line BL3 and a second first Contact C1 and a second pile fir2 • Gan Shi _ ^, one after another accounts for C. Where the sub-element line is the V line of the gate electrode and the contact point is the contact plug. The first bit line BL3 and the second bit line BL4 intersect each other with the line WL1 perpendicularly, that is, 筮 a-仏 t ~ ^ and the second bit line BL3 and the second bit line BL4 are formed by the word :: WL : No, it is separated by left and right sides. First contact. It is connected to the first bit line bls, I, the second contact C2 is electrically connected to the second bit line BL4, and the first contact C1 and the second contact C2 are located at different positions separated by the word line WL1. side. The defined range of the active area 60 includes the above-mentioned elements. The active area 60 has an extended area to form a z-type active area. The active area 60 is composed of a main area and an extended area. The two extension areas are located at both ends of the main body and are connected perpendicularly to the main body area. The first and polar regions are included in one of the extension areas and part of the main body area, and the second source / contained in the active area. In addition—the extension area and part of the main area, because; the first contact C1 corresponding to the f-polar area and the second contact / correspondence to the second source / infinity area are respectively located in the active area 60 extended area End position 第 16 页

I 0748-9572TWF (nJ); CJaire.ptd 1240383 V. Description of the invention (13) Please refer to Fig. 6b 'another single multi-bit word line WL2, a second one ~ ϋτ4 t * one. Also the layout includes — two-contact enq two-line BL bit, and one-line " point is the contact plug. . Among them, the sub-element line is the interdigitated line between the second bit line criminal and the third bit line BL5 intersecting line perpendicularly, and the second bit line D = is separated from the word line WL · Two ... The first: the contact ^ second line ^ is electrically connected by a word, the third contact C3 and the third bit are electrically connected = the first contact C2 and the third contact C3 are located by the word line η, The defined range of the active area 60 includes the above-mentioned Z-type active areas. The 6G area is composed of a main body and an extended area, ^ at both ends of the main body and perpendicular to the main body, and a second contact point. 2 and: = Do not locate at the ends of the active area 60 extension area. Yian. ‘., Recognize y Please refer to Figures 6c-6d, No. The figure is a schematic diagram showing the layout of a plurality of Yi Zao 7C of the present invention, showing the character line ^, milk 2, ° yuan line, BL2, BL3, BL4, BL5, criminal, BL7, a plurality of contacts such as bit c1 , C〗, π, etc., the memory is fine! And active area 60; # character line, the wire of the gate; the contact is the contact plug. The memory cell 60i is a single multi-bit memory cell shown in Figures "~ 6." The diagram in Figure 6c shows a plurality of memory cells 60 1. Each contact can be connected to a neighboring memory cell. Therefore, each contact can be shared by 4 memory cells 6 0 1. The equivalent circuit diagram in FIG. 6d clearly shows that the second contact c 2 of memory cell 60 1 is shared with neighboring memory cells and is electrically connected. Fifth Embodiment

〇748-9572TWF (nl); Claire.ptd Page 17 1240383 V. Description of the invention (14) Please refer to Figures 7a-7d. Figures 7a-7b show the layout of a single multi-bit memory cell of the present invention. FIG. 7c is a schematic diagram showing the layout of the multi-bit memory unit of the present invention, and FIG. 7d is an equivalent circuit diagram showing the layout of the multi-bit memory unit of FIG. 7c. Please refer to Figs. 7a-7b, which are schematic diagrams showing the fifth embodiment of the layout of a single multi-bit memory cell according to the present invention, respectively. In this embodiment, a semiconductor substrate (not shown) is first provided, and a multi-bit memory unit as shown in FIG. 2 is formed on the semiconductor substrate. The multi-bit memory unit is defined as an active area 70.

The layout of a single multi-bit memory cell includes a word line WLi or WL2, a first bit line BL3, and a first contact point Ci and; among them, the word line is the wire of the gate; the contact point is Touch the plug.

The first bit line BL3 intersects the character line wl1 or WL2 perpendicularly. The first bit line BL3 is separated by the word line WL1 or WL2 into left and right sides. The first contact point Ci is located on one of the word line WL1 or WL2 And is electrically connected to the first bit line bL3. The defined range of the active area 70 includes the above-mentioned elements. The active area 70 has mutually extending extensions to form a τ-type active area. The τ-type active area 70 is composed of a main area (ma ^ n area) and an extension area ( extended area) constitutes one end of the main body area and the middle part of the extended area are interconnected, and the main body area is parallel to the corresponding first source line or first bit line, the extended area is parallel to the corresponding child line t1, and the first The first contact C1 corresponding to the drain region is included in a part of the main body region, and the first contact π corresponding to the second drain region includes an extension region of the active region and a part of the main body region. Please refer to Figures 7c-7d. Figure 7c shows a multi-bit record of the present invention.

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V. Description of the invention (15) Schematic diagram of the layout of the memory cell, showing word lines WL1, WL2, bits; & BL1, BL2, BL3, BL4, BL5, BL6, BL7, and multiple contacts such as C1, C111, C112, etc., metal wire memory cell 701 and active area 708; among them, the word line is the wire of the gate; the contact point is the contact plug. Memory cell 7 〇1 is a single multi-bit memory cell as shown in Figures 7a-7b. The diagram in Figure 7C shows a plurality of memory cells 70 1, and each contact corresponding to the drain region can be changed. The two left and right memory cells 701 share each other, and the same row of memory cells 70m share the source, and the contact C111 or C112 is connected to the corresponding additional metal wire or ... 2, which is equivalent to Figure 7d The circuit diagram clearly shows that the first contact C1 of the memory cell 7 〇1 is shared with the adjacent memory cell and is electrically connected, and the same memory cell 7 01 is connected by the contact C⑴ or C1U and the metal wire MΠ or P-connected to make the same column of memory cells 701 share the source, respectively. According to the layout method provided by the present invention, when the memory unit has two and four blocks respectively storing data, it means that one memory unit can process ^ group two's programming or erasing, that is, flash memory or: difficult ^ ^ Memory can be programmed or erased at a time ^ ϋ ° is twice the number of memory cells in the entire memory. , '&Quot;

Although the present invention has been disclosed in a preferred embodiment, such as Ruyi, it is not sufficient to limit the present invention. Any person skilled in this art can make changes and retouch within the scope of ..., Asia, Africa, and God. Therefore, the fourth aspect of the present invention should be regarded as The appended application patents shall prevail. * Protection Range 15

0748-9572TWF (nl); Claire.ptd Page 19 1240383 Brief description of the diagram Figure 1a shows the programming intention of the conventional flash memory unit. Figure 1b is a schematic diagram showing the erasing of a conventional flash memory memory unit. Figure 1c is a schematic diagram showing the process behind the conventional mask-only read-only memory unit. Figure 2a is a schematic cross-sectional view showing a multi-bit readable and writable erasable memory unit of the present invention. Fig. 2b is a schematic cross-sectional view showing a multi-bit mask type read-only memory unit of the present invention. Figure 2c is a schematic cross-sectional view showing a write-once anti-fuse read-only memory cell of the present invention. Figure 3a is a schematic diagram showing a first embodiment of a single multi-bit memory cell of the present invention. Fig. 3b is a schematic diagram showing the layout of the multi-bit memory unit of the present invention. Figure 3c is an equivalent circuit diagram showing the layout of the multi-bit memory cell of Figure 3b. Figure 4a is a schematic diagram showing a second embodiment of the layout of a single multi-bit memory cell according to the present invention. Fig. 4b is a schematic diagram showing the layout of the multi-bit memory unit of the present invention. Figure 4c is an equivalent circuit diagram showing the layout of the multi-bit memory cell of Figure 4b. m 0748-9572TWF (nl); Clai re.ptd Page 20 1240383 Brief description of the drawings Figure -5b is a schematic diagram showing a third embodiment of a single multi-bit memory cell layout of the present invention. Fig. 5c is a schematic diagram showing the layout of the multi-bit memory unit of the present invention. Figure 5d is an equivalent circuit diagram showing the layout of the multi-bit memory cell in Figure 5c. Figures 6a-6b are schematic views showing a fourth embodiment of the layout of a single multi-bit memory cell according to the present invention. Fig. 6c is a schematic diagram showing the layout of the multi-bit memory unit of the present invention. Fig. 6d is an equivalent circuit diagram showing the layout of the multi-bit memory cell of Fig. 6c. Figures 7a-7b are illustrations of the fifth embodiment of a single multi-bit memory cell layout of the present invention. Fig. 7c is a schematic diagram showing the layout of the multi-bit memory unit of the present invention. Figure 7d is an equivalent circuit diagram showing the layout of the multi-bit memory cell of Figure 7c. Explanation of symbols: B ~ memory cell; S / D ~ source / drain region; metal line M11 or M12; WL1, WL2, WL3, WL4 ~ word line; BL1, BL2, BL3, BL4, BL5, BL6, BL7 ~ Bit line

0748-9572TWF (nl); Claire.ptd Page 21 1240383 The diagram briefly illustrates C1, C2, C3, C111, C112 ~ contacts; 1 0 1 ~ $ evening substrate; 1 0 1 a ~ source; 1 0 1 b ~ drain electrode; 102 ~ gate oxide layer; 103 ~ floating gate; 105 ~ control gate; 120 ~ $ base; 1 2 1a, 1 2 1 b ~ source drain Electrode; Φ 1 2 2 ~ oxide layer; 1 2 3 ~ gate electrode; 201 ~ semiconductor substrate; 2 02 ~ gate electrode; 2 0 3a ~ gate dielectric layer; 2 0 3b ~ oxide layer; 2 0 4 ~ Barrier wall; 2 05 ~ metal silicide; 2 2 0 ~ semiconductor substrate; Φ 2 2 1 ~ source drain extension region; 2 2 a ~ gate dielectric layer; 2 2 2 b ~ oxide layer; 2 2 3 ~ gate; 2 2 4 spacer; 2 2 5 metal silicide layer;

0748-9572TWF (nl); Claire.ptd Page 22 1240383 Brief description of the diagram 23 0 ~ semiconductor substrate; 2 3 1 ~ source-drain extension; 232a, 232c ~ gate dielectric layer; 2 3 2 b ~ insulation Layers; 2 3 3 ~ gates; 2 3 4 spacers; 2 3 5 metal silicide layers; 30, 40, 50, 60, 70 ~ active areas; 30 1, 40 1, 50 1, 6 0 1, 70 1 ～ I have memories, monthly bag ❿ Φ

0748-9572TWF (nl); Claire.ptd Page 23

Claims (1)

1240383 VI. Scope of Patent Application 1. A layout of a memory cell, including a line, a complex number, a source number, and a source line, and a source line, and a plurality of memory cells. Each memory cell has: structure, coupling Connected to one of the word lines; a source / drain region coupled to one of the first source / drain lines or the bit line, the first source / drain region and the gate Between-the first gap wall is used to store electrons or charges; and the source / drain region is coupled to the second source / drain lines or the first gate first gap wall to the second bit line Among them, the second gap wall 2. Such as the memory of the application 3 · Such characters as the application 4 · The first of each memory as the application 5 · The second of each memory as the application 6 · as For every memory in Shen, there is between the second source / drain region and the gate, and the second gap wall is used to store electrons or charges. Please refer to the layout of the memory unit described in item 1 of the patent scope. The unit is a memory unit that can be read, written and erased. Please refer to the layout of the memory unit described in item 1 of the patent, whose line is a plurality of gate lines forming these gate structures. Please refer to the layout of the memory unit described in item 1 of the patent scope. The first source / drain region of the unit is coupled to the source / drain line or the first bit line through a contact plug. Please refer to the layout of the memory unit described in the first item of the patent scope. The second source / drain region of the unit is coupled to the source / drain line or the second bit line through a contact plug. Please refer to the layout of the memory cell described in item 1 of the patent scope, the first source / drain region, the second source / drain region of the cell, and 0748-9572TWF (nl); Claire.ptd Page 24 1240383 6. Scope of patent application-The channel between the first and second source areas together constitutes an active area. The direction of extension of the active area and the word The extending directions of the element lines are at right angles. 7. The layout of the memory cell as described in item 1 of the scope of the patent application, wherein the first source / drain region, the second source / drain region, and a first source and a second source of each memory cell The channels between the drain areas together form an active area, and the angle between the extending direction of the active area and the extending direction of the character lines is less than 90 degrees. 8. The layout of the memory cell described in item 1 of the scope of the patent application, wherein the first source / drain region, the second source / drain region and a first source and a second source of each memory cell The channels between the pumping areas together form an active area and an active area. The active area is a Z-type active area. The Z-type active area consists of a main area and two extended areas. area), the two extension areas are respectively located at two ends of the main body and are vertically connected to the active area, and the first source /; and the polar area are included in one of the extension areas and part of the main body area of the active area, The second source / drain region is included in another extension region and a portion of the body region of the body region. 9. The layout of the memory cell described in item 1 of the scope of the patent application, wherein the first source / drain region and the second source / drain region of each memory cell and one of the first and second sources The channels between the pumping areas together form an active area. The active area is a T-shaped active area. The T-shaped active area is composed of a main area and an extended area. One end is connected to a middle portion of the extension region, and the body region is parallel to the corresponding first source / drain line or first bit line, and the extension region 0748-9572TWF (nl); Claire.ptd Page 25 1240383 6. The scope of the patent application is parallel to the corresponding character line, and the first source / drain region is included in a part of the main region 'the second source / > The polar region is included in the extended region of the active region, and part of the main region. 1 〇. — A layout of memory cells, including: a plurality of digital element lines; a plurality of first source / drain lines; a plurality of second source / drain lines; and a plurality of memory cells, each memory cell has: a gate structure Is coupled to one of the word lines; a first source / drain region is coupled to one of the first source / drain lines or the first bit line; and a second source / The drain region is coupled to one of the second source / drain lines or the second bit line; wherein the gate structure and the first source / drain region or the second source / drain region Each has a selectively formed or programmable source-drain extension for storing or memorizing electronic signals. 1 1. The layout of the memory unit as described in item 10 of the scope of the patent application, wherein the memory units are curtain-type read-only memory units (Mask kR0M). 1 2. According to the layout of the memory cell described in item 10 of the scope of the patent application, 彳 | wherein the character lines are a plurality of gate lines forming the gate structures. 1 3. The layout of the memory unit as described in item 10 of the scope of patent application, wherein the first source / drain area of each memory unit is through a contact plug and the corresponding first source / drain line or the The first bit line is coupled. 14. The layout of the memory unit as described in item 10 of the scope of patent application, 0748-9572TWF (nl); Clai re.ptd page 26 1240383 VI. Patent application scope The second source / drain area of each memory unit is through a contact plug corresponding to the second source / drain line Or the second bit line is coupled. · 15. The layout of the memory cell as described in item 10 of the scope of the patent application, wherein each memory cell and the first source / drain region and the second source / drain region and the first The three channels between the second source regions collectively form an active region, and the specific angle at which the active region intersects with the character lines forms a vertical angle. 16. The layout of the memory unit described in item 15 of the scope of patent application, wherein the specific included angle is less than 90 degrees. 17. The layout of the memory cell as described in item 10 of the scope of the patent application, < · wherein the channel of each memory cell and the first source / drain region and the second source / > coupled thereto And the polar area together form an active area. The active area is a * Z-type active area. The Z-type active area is composed of a main area and two extended areas, which are respectively located in the main body. The two ends are perpendicularly connected to the body region, the first source / drain region is included in one of the extension regions and part of the body region, and the second source / drain region is included in the active region. Another extension area and part of the main body area. 18. The layout of the memory cell as described in item 10 of the scope of patent application, wherein the channel of each memory cell and the first source / drain region and the second source / drain region coupled thereto Together, it forms an active area. The active area is a T-shaped active area. The T-shaped active area is composed of a main area and an extended area. One end of the main area is in the middle of the extended area. The parts are interconnected, and the body region is parallel to the corresponding first source line or first bit line, the extension region is parallel to the corresponding word line, and the ' 0748-9572TWF (nl); Claire.ptd Page 27 1240383 6. Scope of patent application ^ In the # area, the 5th source · 1st source and the 1st source / drain region are included in part of the subject ^ Within the main area. The area is included in the extension and part of the main area &19; a layout of a memory cell, including a line of multiple digital elements; a line of plural first sources / animated lines; a line of plural second sources / drain lines; and a plurality of Memory unit, one of each memory unit 1-, structure 'coupled to these words: source A pole line or first-to-one source drain region, coupled to one of the bit lines of the special brother One; and # — π, in the town's second source / drain pole line or the second one's first source> and the polar area, connect to the specialty; and the polar area or the second source > and the extreme bit line One; the source, wherein the gate structure and the second section each have an anti-fuse (Ant i -fuse) on ft ± i -χ * ^ • ten ['§§ ten already thought of the original layout' 2 0 · 如The scope of the patent application is No. 19. A A mouth of the mouth m τ · 廿 1 Dou La—Yekou mouth is free. Jing Yanji Yi (0 ne Τ1 me, where the net 纟 memory is a one-time write strategy. ^ Programmable ROM) 〇2 1 · As described in the scope of the patent application, item i 9 °, the layout of the cells and units', where the character lines are complex gates forming the structure . 22. The layout of the memory unit described in item 9 of the scope of the patent application, wherein the first source / wave plaque of each memory unit is connected to the corresponding first source / line or the first source through a contact plug. A bit line is coupled. 2 3 · According to the layout of the 5th unit described in item 9 of the scope of the patent application, wherein the second source / wave plaque of each memory unit is connected with a contact plug through 0748-9572TWF (nl); Claire.ptd Page 28 1240383 6. Scope of patent application The second source / sink line or the second bit line is coupled. 24. The layout of the memory cells as described in item 19 of the scope of the patent application, wherein each memory cell and the first source region and the second source region and the first and second source regions coupled thereto The three channels together form an active area. The active area is at a vertical angle to the specific missing angle between the character lines. 25. The layout of the memory unit as described in item 24 of the scope of patent application, wherein the specific included angle is less than 90 degrees. 26. The layout of the memory cell described in item 19 of the scope of the patent application, wherein the channel of each memory cell and the first source drain region and the second source region coupled together form an active region , The active area is a Z-type active area, the Z-type active area is composed of a main area (main area) and two extended areas (extended areas), the two extended areas are respectively located at the two ends of the main body and the main area Vertically connected, the first source drain region is included in one of the extension regions and a main body region of the active region, and the second source region is included in the other extension region and a main body region of the active region . 2 7 · The layout of the memory cell described in item 19 of the scope of the patent application, wherein the channel of each memory cell and the first source drain region and the second source region coupled together form an active region , The active area is a T-type active area, the T-type active area is composed of a main area (main area) and an extended area (extended area), one end of the main area and the middle part of the extended area are interconnected, and The main body area is parallel to the corresponding first source line or first bit line, the extended area is parallel to the corresponding word line, the first source drain area is included in a part of the main body area, the Second source region packet 0748-9572TWF (nl); Clai re.ptd page 29 1240383 6. Scope of patent application Included in the extension area and part of the main area of the active area «IBi 0748-9572TWF (nl); Claire.ptd page 30