1240341 九、發明說明： 【發明所屬之技術領域】 本發明是有關於一種覆晶之形成方法，且特別是有關於一種 覆晶之凸塊的形成方法。 【先前技術】 覆晶封裝（Flip chip mounting)製程具有良好電器特性高 輸出/入接點密度’且能縮小IC尺寸增加每片晶圓產出，已被: 好為未來極具潛力之構裝方式。在覆晶技術中，凸塊的製作 (Bumpmg)為覆晶技術的成敗關鍵。目前有多種覆晶技術正在 智展中，纟主要差異在於凸塊（Bump)的材料及形成方式不同。常 見的凸塊材料有錫鉛凸塊(s〇lder Bump)、金凸塊(⑽Bu_、 導電膠凸塊(Conductive Polymer Bump)以及高分子凸塊(吨_ Bump)等四種型態’纟中又以錫鉛凸塊應用最為廣泛。凸塊製程 主要可有二種方式製作’包含蒸鍍法、電鑛法㈣ng)以 及印刷法（Printing)等方式。 立請參照第1A〜1F圖，其繪示依照傳統覆晶之形成方法之示 思圖。傳統覆晶之形成方法包括下列步驟。首先，如第以圖所 不，提供一晶圓，晶圓之基板U《有—主動表面12，主動表面 1主2上具有凸塊下金屬層13。然後，如第1B圖所示，於整個主動 表面12先覆蓋光阻層141。接著 银有如第1C圖所不，光阻層141 、、里圖案移轉定義出開口。 一 ^ u 之後士第ID圖所示，將錫鉛金屬14 真入光阻層之開口中。接莫，士σ楚IP m —、 T接者如第1Ε圖所示，對錫鉛金屬14進 订迴銲（refl〇w)製鞋，形占必以 ^以形成釓錫凸塊15，並移除光阻層141 以製传晶圓1 〇。接英曰 錯錫凸塊15先、、乂 成多個晶片101。之後，將 ‘ '助銲劑（FluX)，並且將具有錫鉛凸塊15的晶 1240341 粒翻覆後與基板16接在一起1240341 IX. Description of the invention: [Technical field to which the invention belongs] The present invention relates to a method for forming a flip chip, and more particularly to a method for forming a flip chip. [Previous technology] Flip chip mounting process has good electrical characteristics, high output / input contact density ', and can reduce IC size and increase the output of each wafer. the way. In flip chip technology, bump fabrication is the key to the success of flip chip technology. At present, there are a variety of flip-chip technologies in the exhibition, the main difference is the material and formation of bumps. Common bump materials include tin-lead bumps (solder Bump), gold bumps (⑽Bu_, conductive polymer bumps (Conductive Polymer Bump), and polymer bumps (ton_Bump)). In addition, tin-lead bumps are most widely used. There are two main ways to make bumps: 'Evaporation method, electro-mining method (ngng), and printing method. Please refer to FIGS. 1A to 1F, which are schematic diagrams showing a method for forming a conventional flip chip. A conventional flip-chip formation method includes the following steps. First, as shown in the figure, a wafer is provided, and the substrate of the wafer is provided with an active surface 12, and the active surface 1 has a metal layer 13 under the bump 2 on the main surface 2. Then, as shown in FIG. 1B, the entire active surface 12 is covered with the photoresist layer 141 first. Next, as shown in FIG. 1C, the pattern of the photoresist layer 141 and the inner layer is shifted to define the opening. After ^ u, as shown in Figure ID, the tin-lead metal 14 is really inserted into the opening of the photoresist layer. Then, as shown in FIG. 1E, T σ IP IP m, T connector, the tin-lead metal 14 is re-welded (refl0w) to make shoes, the shape must be ^ to form the tin-tin bumps 15, The photoresist layer 141 is removed to make a wafer 10. Then, the staggered bumps 15 are formed into a plurality of wafers 101. After that, ‘′ flux (FluX), and 1240341 grains of tin-lead bumps 15 are overturned and then joined to the substrate 16.
迴銲爐進行加溫，使錫鉛凸塊 圖所示。 。最後，將基板連同晶片一起進入 15與基板16焊接在一起，如第J F 當助銲劑沾附不均句時’迴料程中會導致凸塊表面 、’正。此外，凸塊表面極易氧化而形成-氧化層。不平整的凸 氧化層極易導致凸塊與基板焊接不良，進而造成覆晶技術 的失敗。 【發明内容】 有鑑於此，本發明的目的就是在提供一種凸塊的形成方法， 具有平整的表面且不易形成氧化層。藉此，提升覆晶封裝的品質。 根據本發明的目的，提出_種晶圓之形成方法，至少包括步 驟：提供-基板’具有—主動表面，主動表面係暴露出—凸塊下 金屬層，$成&塊於凸塊下金屬層上；喷激—助銲劑於凸塊； 第人干凸塊，使得凸塊呈圓形；立即喷激助鲜劑於凸塊；第 二次迴銲凸塊’用以去除凸塊上之—氧化物，並且平滑凸塊表面。 根據本發明的目的’提出一種凸塊之形成方法，用以形成於 -晶圓之-凸塊下金屬層’凸塊下金屬層係、位於基板之—主動表 面’至少包括步驟：形成—光阻層於主動表面光阻層具有一開 槽’開槽係暴露出凸塊下金屬層；㈣—金屬於開槽中並覆蓋凸 塊下金制；移除光阻層，凸塊係形成—凸塊於凸塊下金屬層 上；喷m-助銲劑於凸塊；第—次迴銲凸塊，使得凸塊呈圓形； 立即噴制銲劑於凸塊n迴銲凸塊，用以 氧化物，並且平滑凸塊表面。 兒上之 根據本發明的目的，提出一種覆晶之形成方法，包括下列步 驟。首先’提供—基板，具有—主動表面，主動表面具有多個凸 塊。之後’噴m-助銲劑於凸塊；第—次迴銲凸塊，使得凸塊呈 1240341 圓形；Μ喷灑助銲劑於凸塊；第二次迴鲜凸塊，用以去除凸塊 上之一氧化物，並且平滑凸塊表面。最後，焊接一底材以及基板， 使得凸塊係連接於底材上。 為讓本發明之上述目的、特徵、和優點能更明顯易僅，下文 特舉一較佳實施例，並配合所附圖式，作詳細說明如下·· 【實施方式】 請參照第2圖，其繪示依照本發明之—較佳實施例之凸塊之 形成方法之流程圖。本實施例係一種凸塊之形成方法用以形成 於-晶圓之-凸塊下金屬層’該凸塊下金屬層係位於晶圓之一主 動表面。本發明之凸塊之形成方法至少包括下列步驟。首先，在 步驟S2G1中’形[光阻層該主動表面，光阻層具有一開槽， 開槽係暴露出凸塊下金屬層。接著，在步驟_中，電鑛^屬 於開槽中，金屬係覆蓋凸塊下金屬層。之後，在步驟咖中， 移除光阻層，金屬係形成—凸塊於該㈣下金屬層上。㈣在 步驟S204中’喷灌一助銲劑於凸塊，且如步驟纏所示，第一 次迴銲凸塊’使得凸塊呈圓形。接著，如步驟_所示，立即 噴麗助銲劑於凸塊’且如步驟窗所示，第二次迴鮮凸塊，用 以去除凸塊上之一氧化物，並且平滑凸塊表面。 請參照第3圖’其繪示依照本發明之一較佳實施例之晶圓之 形成方法之流程圖。本實施例之晶圓之形成方法至少包括步驟。 百先’在步驟S3()1中’提供—基板，具有—主動表面主動表 面具有多個凸塊下金屬層。接著’在步驟隨中，對應地形成 夕個凸塊於凸塊下金屬層上。然後，在步驟s則中喷藏一助 ’于劑於凸&且如步驟S3()4所示，第_次迴鲜凸塊使得凸塊 呈圓形。接著，如步驄Μ 一 驟S305所不，立即喷灑助銲劑於凸塊，且 士步驟S306所不’第二次迴銲凸塊，用以去除凸塊上之一氧化 1240341 物，並且平滑凸塊表面。 請參照第4圖，其繪示依照本發明之一較佳實施例之覆晶之 形成方法之流程圖。本實施例之覆晶之形成方法包括下列步驟。 首先，在步驟S401中，提供一基板，具有一主動表面，主動表 面具有多個凸塊。之後，在步驟S4〇2中，喷灑一助銲劑於凸塊， 且如步驟S403所示，第一次迴銲凸塊，使得凸塊呈圓形。接著， 如步驟S404所示，立即喷灑助銲劑於凸塊，且如步驟S4〇5所示， 第一夂迴ί于凸塊，用以去除凸塊上之一氧化物，並且平滑凸塊表 面。。最後，在步驟S403中，焊接一底材以及基板，使得凸塊 係連接於底材上。 以下係舉一較佳實施例作詳細說明如下，然本較佳實施例並 不會對本發明之保護範圍作限縮。例如本發明雖舉一鉛錫凸塊為 例作％明’然本發明之凸塊材質並不限定於此，凸塊亦可以是金 ^ 塊（G〇ld BumP)、導電膠凸塊（Conductive P〇lymer Bump)以及高 分子凸塊（Polymer Bump)等四種材質。此外，本發明雖舉一電錢 製㈣例作說明，但本發明之凸塊製程並不限定於此，凸塊亦可 糟由条鍍法、電鍍法（Eleetn^plating)以及印刷法㈣如⑽等方式 曰乂月參…、第5A〜50圖’其繪示依照本發明一較佳實施例之覆 妓二成方法的不思圖。覆晶封裝的主要製程包括凸塊製作、晶片 目^ ϋ 弟圖所不，提供一基板21，基板上 與外部電路形成電性連接;接=:材質通常為銅或銘’藉以 23於晶圓21上，保護層可二：f 5B圖所示’塗佈保護層 卜w如 了保濩日日®結構並平坦化表面；保護層 23沒有完全覆蓋住鋁墊 矣而a 士 2保濩層23係暴露出鋁墊22之導電 ^ ’提供之晶圓21具有主動表面20a，且主動表面 1240341 20a具有多個I呂塾22 〇缺接,^ rp 一後，如第％圖所示，以濺鍍（Sputter) 或洛鍍（Evaporati〇n)方， 谐+成，， 墊22之表面上。接著，如大第^ 一*電層241於保護層Μ與紹 具有感光效果的光阻岸25圖所^ ’導電層Μ上先覆蓋一 曰1，例如一層乾膜或是液態光阻劑。利 用適虽的方式，例如圖層移轉方式，於光阻層251上定義出開口， 亚移除部分的光阻層251，保留一 保迢圖案化先阻層25於開口 271 ，如第5E圖所示’卩圖案化光阻層25為一遮罩進行顯 影’顯影完成後對導電芦, θ (卓進订顯 利用濕触刻的方式^=行触刻以圖案化導電層241，如 層，形成-：全Π:!電層241，保留於開口上的導電The reflow furnace is heated to make the tin-lead bumps as shown in the figure. . Finally, the substrate together with the wafer enters 15 and the substrate 16 are soldered together, such as J F. When the flux adheres to the uneven sentence, the surface of the bump will be positive during the return process. In addition, the bump surface is easily oxidized to form an oxide layer. The uneven convex oxide layer can easily lead to poor soldering between the bumps and the substrate, which will cause the failure of flip-chip technology. SUMMARY OF THE INVENTION In view of this, an object of the present invention is to provide a method for forming a bump, which has a flat surface and is not easy to form an oxide layer. This improves the quality of the flip-chip package. According to the purpose of the present invention, a method for forming a wafer is provided, which includes at least the steps of: providing a substrate with an active surface, and the active surface is exposed, a metal layer under the bump, and a metal layer under the bump. Layer; spray-flux on the bump; first dry the bump to make the bump circular; immediately spray the flux on the bump; second re-solder bump to remove the bump on the bump —Oxide and smooth bump surface. According to the purpose of the present invention, a method for forming bumps is provided, which is used to form a -wafer-under-bump metal layer. The "under-bump metal layer system, located on the substrate-the active surface" at least includes the steps of: The resist layer on the active surface photoresist layer has a slotted 'slotting system that exposes the metal layer under the bump; ㈣ — metal in the slot and covers the gold under the bump; removing the photoresist layer, the bump system forms-convex Block on the metal layer under the bump; spray m-flux on the bump; re-solder the bump for the first time to make the bump round; immediately spray flux on the bump n to reflow the bump for oxide And smooth the bump surface. According to the purpose of the present invention, a method for forming a flip chip is provided, which includes the following steps. First, a substrate is provided with an active surface, and the active surface has a plurality of bumps. Afterwards, spray the m-flux on the bumps; re-solder the bumps for a 1240341 round; M spray the flux on the bumps; refresh the bumps a second time to remove the bumps An oxide, and smooth the surface of the bump. Finally, a substrate and a substrate are soldered so that the bumps are connected to the substrate. In order to make the above-mentioned objects, features, and advantages of the present invention more obvious and easy, a preferred embodiment is described below in detail with the accompanying drawings as follows. [Embodiment] Please refer to FIG. 2, It shows a flowchart of a method for forming bumps according to a preferred embodiment of the present invention. This embodiment is a method for forming bumps to be formed on a -wafer-under-bump metal layer ', and the under-bump metal layer is located on one of the active surfaces of the wafer. The method for forming a bump of the present invention includes at least the following steps. First, in step S2G1, the active surface of the photoresist layer is shaped. The photoresist layer has a slot, and the slot exposes the metal layer under the bump. Next, in step _, the power ore is in the slot, and the metal system covers the metal layer under the bump. After that, in step C, the photoresist layer is removed, and a metal system is formed—a bump is formed on the underlying metal layer. ㈣In step S204, a flux is sprayed on the bumps, and as shown in the step, the first re-soldering of the bumps makes the bumps round. Next, as shown in step _, immediately spray flux on the bumps' and as shown in the step window, refresh the bumps a second time to remove an oxide on the bumps and smooth the surface of the bumps. Please refer to FIG. 3 ', which shows a flowchart of a method for forming a wafer according to a preferred embodiment of the present invention. The method for forming a wafer in this embodiment includes at least steps. Baixian 'provides a substrate with an active surface in step S3 () 1' and the active surface has a plurality of under bump metal layers. Then, in the following step, corresponding bumps are formed on the metal layer under the bumps correspondingly. Then, in step s, an auxiliary agent is sprayed and the agent is convex & and as shown in step S3 () 4, the bump is refreshed for the _th time to make the bump round. Next, as in step S305, spray the flux immediately on the bumps, and step S306 to re-solder the bumps a second time to remove one of the 1240341 oxides on the bumps and smooth them. Bump surface. Please refer to FIG. 4, which shows a flowchart of a method for forming a flip chip according to a preferred embodiment of the present invention. The method for forming a flip chip in this embodiment includes the following steps. First, in step S401, a substrate is provided with an active surface, and the active surface has a plurality of bumps. After that, in step S402, a flux is sprayed on the bumps, and as shown in step S403, the bumps are re-soldered for the first time so that the bumps are circular. Next, as shown in step S404, the flux is sprayed on the bumps immediately, and as shown in step S405, the first step is to return the bumps to remove an oxide on the bumps and smooth the surface of the bumps. . . Finally, in step S403, a substrate and a substrate are soldered so that the bumps are connected to the substrate. The following is a detailed description of a preferred embodiment, but this preferred embodiment does not limit the scope of protection of the present invention. For example, although a lead-tin bump is used as an example in the present invention, the material of the bump of the present invention is not limited to this. The bump may also be a gold bump (Conductive bump) Polymer Bump) and Polymer Bump. In addition, although the present invention is exemplified by an example of an electric money system, the bump manufacturing process of the present invention is not limited to this. The bumps can also be processed by strip plating, electroplating (Eleetn ^ plating), and printing. According to a method such as 乂 月 参 ..., FIGS. 5A to 50 ', it shows a schematic diagram of a method for covering prostitutes in accordance with a preferred embodiment of the present invention. The main process of flip-chip packaging includes bump fabrication and chip design. 图 图 所 provides a substrate 21 on the substrate to form an electrical connection with the external circuit; connection =: The material is usually copper or inscribed '23 to the wafer On 21, the protective layer can be two: as shown in f 5B, the protective layer is coated as shown in the structure and the surface is flattened; the protective layer 23 does not completely cover the aluminum pad and a 2 protective layer The 23 series exposes the electrical conductivity of the aluminum pad 22. The provided wafer 21 has an active surface 20a, and the active surface 1240341 20a has multiple I 塾 塾 22 〇 Missing, ^ rp, as shown in Figure On the surface of the pad 22, a sputter or Evaporation square is harmonically formed. Next, the first conductive layer 241, such as a dry film or a liquid photoresist, is first coated on the conductive layer M, such as a protective layer M and a photoresist bank 25 with a photosensitive effect, as shown in FIG. 25. Use appropriate methods, such as layer transfer, to define openings in the photoresist layer 251, sub-remove part of the photoresist layer 251, and retain a patterned first resist layer 25 in the opening 271, as shown in Figure 5E. As shown in the figure, “卩 patterned photoresist layer 25 is developed as a mask.” After the development is completed, conductive reeds, θ (Zhuo Jinxian uses wet touch engraving ^ = row touch engraving to pattern the conductive layer 241, such as a layer , Forming-: All Π :! Electrical layer 241, Conduction remaining on the opening
^ 24 (Under Bump Metallurgy layer TJRM^ 24 (Under Bump Metallurgy layer TJRM
layer)，作為鋁墊 22與 βΥ iayer, UBM 由m r a 4之間的，1面。凸塊下金屬層24通常 ^ (wettin, Τ〇η (barHer 的黏著性，其材質可為紹、鈦、：層：:=墊及保護層良好 止鐸球與銲塾之金屬互相料^阻障層係用以防 屬相擴散，其材質可為鎳釩、鋅箄。g =成二广之後，如第5G圖所示，移除圖案化光阻：可 :係二下金屬層之製程。此時，提供之基板η的主動表面 2〇a係暴露出一凸塊下金屬層24。 刃動表面 在完成凸塊下金屬層之製程後，下一部 之後’如第5Η圖所示，於整個 丙尤Μ 的光阻層26,例如一声乾… 覆盍另一個具有感光效果 一 1 ^ 層乾膜或是液態光阻劑。捲荽，4结 所示，以光罩進彳彡者如第51圖 „ M 系移轉疋義出用以形成凸挣夕田从 開槽27,開槽27係暴露出凸塊下金 鬼之用的 所示，利用金屬電鍍方式，將+Μ 。之後，如第5J圖 *甭掌π 电又万式將金屬28電鍍入蝕刻之 並覆盍凸塊下金屬層24。接著 Η曰27中， 者如第5Κ圖所示，移除光阻層26, 1240341 » 使得金屬28形成-凸塊29於凸塊下金屬層24上。然後，喷麗 一助銲劑於凸塊29’並進行迴銲（Refl〇w)製程將凸塊供烤成圓. 形，如第5L圖所示。由於喷灑助鲜劑於立方形金屬不易均勾， 因此經過第一次迴銲之後，凸塊表面仍不平整。之後，盈須等待 其冷卻，立即再次領麟劑於凸塊29，並再次以迴銲製程將凸 塊29烘烤成形，完成凸塊29的製程，如第5M圖所示。第二次 迴辉係可以平滑凸塊表面並去除凸塊表面之氧化層以利進行後 續之覆晶步驟。 進步地說，凸塊29較佳地是一高船凸塊，其錯錫比係實 質上為95 : 5。配合凸塊材質，迴銲溫度係介於3〇5t：〜37〇c)c。_ 較佳的是，迴銲溫度實質上係36〇它。 完成凸塊製程之後，t晶製程係進入晶片接合的程序。接合 的主要目的疋將長了凸塊的晶粒翻覆後與基板的銲墊接在一 起再進入迴紅爐進行加溫，使晶圓的凸塊與基板的銲墊接合在 一起。首先，將具有凸塊的晶圓分割成多個晶片。接著，將凸塊-29沾上助銲劑（Flux)，將長了凸塊29的晶粒2〇1翻覆後與基板 40的銲墊接在一起。之後，再由接合機辨識對位後將晶片 置放於底材40上，如第5N圖所示，使得晶片2〇1上之凸塊29籲 上接觸於底材40。底材40例如是一基板或一電路板。由於在經 過迴銲爐時，錫鉛凸塊溶融後產生的表面張力，具有自動對位的 效應，使得晶片置放的誤差值可以放鬆，一般自行對位值約為銲 墊直徑的四分之一，亦即晶粒與基板的置放偏移可在25%以内。 助銲劑不僅具有暫時固定晶粒與基板的功能，而且可使錫鉛凸塊 表面的氧化物得以活化，形成良好的結合效果。接著，如第5〇 圖所示，焊接晶片201與底材40，將晶片201連同基板4〇 一起 進入迴銲爐進行加溫，使凸塊29與基板的銲墊接合在一起。最 1240341 ，如第5P圖所不，填充膠材（underfili) 4i於晶片加與底 才4〇之間，並加熱使膠材固化以完成覆晶製程。 本發明上述實施例所揭露之覆晶製程，其中凸塊製作係經歷 兩夂iS杯製程。進行第—次迴銲之前，由於金屬表面粗糙，且立 ^體金屬不易均句地喷灑助銲劑，即使經過迴銲凸塊表面仍不平 整。經過第—次迴銲之後，凸塊已被烘烤成球型，可以均勻替沾 附^塗佈助銲劑。其中，助銲劑補具有暫㈣定晶粒與基板的 功此而且可使錫鉛凸塊表面的氧化物得以活化，形成良好的結 合效果。因此’第二次迴銲係可以平滑凸塊表面並去除凸塊表面 之氧化層’以利進行後續之覆晶步驟。藉此，提升覆晶封裝的品 質。 紅上所述，雖然本發明已以一較佳實施例揭露如上，然其並 非用以限定本發明，任何熟習此技藝者，在不脫離本發明之精神 和範圍内，當可作各種之更動與潤飾，因此本發明之保護範圍當 視後附之申請專利範圍所界定者為準。 【圖式簡單說明] 第1A〜1F圖繪示依照傳統覆晶之形成方法之示意圖。 第2圖繪示依照本發明之一較佳實施例之凸塊之形成方法 之流程圖。 第3圖繪示依照本發明之一較佳實施例之晶圓之形成方法 之流程圖。 第4圖繪示依照本發明之一較佳實施例之覆晶之形成方法 之流程圖。 第5A〜5P圖，其繪示依照本發明一較佳實施例之覆晶形成 方法的示意圖。 1240341 【主要元件符號說明】 10 ·傳統晶圓 11 :基板 12 :主動表面 13 :凸塊下金屬層 141 :光阻層 14 :錫鉛金屬 15 :錫鉛凸塊 16 :基板 20 ·晶圓 201 :晶片 20a :主動表面 21 :基板 22 :鋁墊 23 :保護層 221 :導電表面 241 :導電層 24 :凸塊下金屬 25 :光阻層 25 :圖案化光阻層 26 :光阻層 27 :開槽 28 :金屬 29 :凸塊 40 :底材 41 :膠材 12layer), as the aluminum pad 22 and βΥ iayer, UBM by m r a 4, one side. The metal layer 24 under the bump is usually ^ (wettin, Τηη (barHer's adhesion, its material can be Shao, Titanium, Ti: layer: = = pad and protective layer good stop ball and the metal of the welding pad ^ resistance) The barrier layer is used to prevent the diffusion of the metal phase, and its material can be nickel vanadium and zinc hafnium. G = After Erguang, as shown in Figure 5G, remove the patterned photoresist: Yes: it is the process of the second lower metal layer. At this time, the active surface 20a of the provided substrate η exposes a metal layer 24 under the bump. After the cutting surface finishes the process of the metal layer under the bump, after the next step, as shown in FIG. 5, For example, the photoresist layer 26 of the entire C.M., for example, sounds dry ... overlay another 1 ^ layer of dry film or liquid photoresist with a photosensitive effect. Volume, as shown in 4 knots, with a photomask As shown in Fig. 51, "M system transfer is used to form the bulge, and the groove 27 is exposed from the slot 27, and the slot 27 is exposed to the gold ghost under the bump. Using metal plating, + M will be used. As shown in FIG. 5J, the metal is electroplated into the etching 28 and covered with the metal layer 24 under the bump. Then, as shown in FIG. 5K, Remove photoresist layer 26, 1240341 »so that metal 28 is formed-bump 29 on metal layer 24 under bump. Then, spray a flux on bump 29 'and perform a reflow (Refl0w) process to bump The pieces are roasted into a round shape, as shown in Figure 5L. Because spraying the freshener on the cubic metal is not easy to evenly distribute, the surface of the bump is still uneven after the first re-soldering. After that, you must wait for profit. When it cools, it immediately brings the linser to the bump 29 again, and then bakes the bump 29 in the reflow process to complete the process of the bump 29, as shown in Figure 5M. The second rebirth system can smooth the bump. The bump surface and the oxide layer on the bump surface are removed to facilitate the subsequent flip-chip step. Progressively speaking, the bump 29 is preferably a tall ship bump, and its tin-to-tin ratio is substantially 95: 5. For block materials, the reflow temperature is between 305t: ~ 37 ° c) c. _ Preferably, the reflow temperature is essentially 360 °. After the bump process is completed, the t-crystal process enters the wafer bonding process. Procedure. The main purpose of bonding: after the bumped grains are overturned, they are joined with the pads of the substrate and then returned to the red furnace. The heating is performed to bond the bumps of the wafer to the pads of the substrate. First, the wafer having the bumps is divided into a plurality of wafers. Then, the bump-29 is coated with a flux (Flux), and After the crystalline grains 201 with the bumps 29 are overturned, they are connected to the bonding pads of the substrate 40. After that, the bonding machine recognizes the alignment and places the wafer on the substrate 40, as shown in FIG. 5N. The bumps 29 on the wafer 201 are brought into contact with the substrate 40. The substrate 40 is, for example, a substrate or a circuit board. Due to the surface tension generated after the tin-lead bumps melt when passing through the reflow furnace, The effect of automatic alignment can relax the error value of wafer placement. Generally, the self-alignment value is about one quarter of the pad diameter, that is, the placement deviation of the die and the substrate can be within 25%. The flux not only has the function of temporarily fixing the crystal grains and the substrate, but also can activate the oxide on the surface of the tin-lead bump to form a good bonding effect. Next, as shown in FIG. 50, the wafer 201 and the substrate 40 are soldered, and the wafer 201 and the substrate 40 are brought into a reflow furnace to be heated, so that the bumps 29 and the pads of the substrate are joined together. At least 1240341, as shown in Figure 5P, the underfili 4i is filled between the wafer and the bottom 40, and the glue is cured by heating to complete the flip-chip process. The flip-chip manufacturing process disclosed in the above embodiments of the present invention, wherein the bump manufacturing process is performed through a two-iS cup process. Before the first reflow, the surface of the bumps was uneven because the metal surface was rough and it was not easy to spray the flux on the solid metal evenly. After the first re-soldering, the bumps have been baked into a ball shape, and the flux can be evenly applied. Among them, the flux repair has the function of temporarily determining the crystal grains and the substrate, and can activate the oxide on the surface of the tin-lead bump to form a good bonding effect. Therefore, the 'second reflow system can smooth the bump surface and remove the oxide layer on the bump surface' in order to facilitate the subsequent flip-chip step. This improves the quality of the flip-chip package. As mentioned above, although the present invention has been disclosed as above with a preferred embodiment, it is not intended to limit the present invention. Any person skilled in the art can make various changes without departing from the spirit and scope of the present invention. And retouching, so the scope of protection of the present invention shall be determined by the scope of the appended patent application. [Brief Description of the Drawings] Figures 1A to 1F are schematic diagrams showing a method for forming a conventional flip chip. FIG. 2 shows a flowchart of a method for forming bumps according to a preferred embodiment of the present invention. FIG. 3 is a flowchart of a method for forming a wafer according to a preferred embodiment of the present invention. FIG. 4 shows a flowchart of a method for forming a flip chip according to a preferred embodiment of the present invention. 5A to 5P are schematic views showing a flip-chip formation method according to a preferred embodiment of the present invention. 1240341 [Description of main component symbols] 10 · Traditional wafer 11: Substrate 12: Active surface 13: Metal layer under bump 141: Photoresist layer 14: Tin-lead metal 15: Tin-lead bump 16: Substrate 20 · Wafer 201 : Wafer 20a: active surface 21: substrate 22: aluminum pad 23: protective layer 221: conductive surface 241: conductive layer 24: under bump metal 25: photoresist layer 25: patterned photoresist layer 26: photoresist layer 27: Slot 28: metal 29: bump 40: substrate 41: glue 12