TWI239136B - High-efficiency high-boost-ratio dc/dc converter with reduced peak switch voltage stress - Google Patents

High-efficiency high-boost-ratio dc/dc converter with reduced peak switch voltage stress Download PDF

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TWI239136B
TWI239136B TW93111433A TW93111433A TWI239136B TW I239136 B TWI239136 B TW I239136B TW 93111433 A TW93111433 A TW 93111433A TW 93111433 A TW93111433 A TW 93111433A TW I239136 B TWI239136 B TW I239136B
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circuit
voltage
capacitor
diode
inductor
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TW93111433A
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TW200536242A (en
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Rong-Jong Wai
Rou-Yong Duan
Chung-You Lin
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Wai Zheng Zhong
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    • YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02EREDUCTION OF GREENHOUSE GAS [GHG] EMISSIONS, RELATED TO ENERGY GENERATION, TRANSMISSION OR DISTRIBUTION
    • Y02E10/00Energy generation through renewable energy sources
    • Y02E10/50Photovoltaic [PV] energy
    • Y02E10/56Power conversion systems, e.g. maximum power point trackers

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Abstract

The aim of this invention is to develop a high-efficiency high-boost-ratio DC/DC converter with reduced peak switch voltage stress. In general, a high-boost-ratio DC/DC converter is employed for many applications via the power source of low-voltage batteries. For examples, a high intensity discharge (HID) lamp, the high-voltage dc bus of an uninterruptible power supply (UPS), a travelling wave tube amplifier (TWTA), etc. In order to satisfy the requirement of high-voltage demand, a high-efficiency high-boost-ratio converter is one of the essential mechanisms in power supply systems with low-voltage sources. The high-efficiency high-boost-ratio DC/DC converter with reduced peak switch voltage stress utilizes a three-winding coupled transformer for providing a high conversion ratio without the extreme switch duty-cycle. This three-winding coupled inductor is also facilitated to reduce peak switch voltage stress for decreasing the conduction loss, and to reduce the turn-off rate of the output diode for alleviating the reverse-recovery problem. It can achieve the property of high-efficiency power conversion. The high-efficiency high-boost-ratio DC/DC converter with reduced peak switch voltage stress can be used for low-voltage sources, such as conventional batteries, fuel cells, photovoltaic and wind energy, to further increase the energy utility rate.

Description

1239136 狄、發明說明: 【發明所屬之技術領域】 夺多電源應用場合’例如氣體放電式頭燈、不斷電系 統中反流器之高壓直流匯流排、寬頻行波管放大器· ·等, 均需要高壓直流電源供應,然而一般使用傳統蓄電池作為 電力來源,因此發展高昇壓比換流器為必要之電源轉換機 制。本發明之具減低開關耐壓效能之高效率高昇壓比換流 器,可以將傳統蓄電池、燃料電池、太陽能發電以及風力 發電之低輸出電壓,轉換為高電壓直流電源供電系統,大 幅提昇能源利用率及增加供電穩定度。本發明所涉及之技 術領域包含電力電子、直流/直流換流技術及能源科技之範 ’’雖然本發明所牽涉之技術領域廣泛,但其主要在於發 展具減低開關耐壓效能之高效率高昇壓比換流裝置,以改 善習用換流器之缺失。 【先前技術】 傳統昇壓式換流器,可藉由調整開關之責任週期(Duty Cycle) ’控制輸出電壓昇壓比例,當應用於高昇壓比之情 況下,責任週期需要調整至極大值,然而換流器中電感之 等效電阻(ESR)導致昇壓比有所限制,無法操作於昇壓比例 超過7倍以上之情況且轉換效率不彰。再者,當該昇壓式 換流器之功率半導體開關截止時,兩端電壓值為輸出電 壓,此高於輸入電壓數倍之跨壓,迫使功率半導 選擇高耐壓之則猶,然、而其具有較大二= (Rds^w) ’形成較高之導通損失。除此之外,傳統昇壓式換 1239136 流器中二極體存在逆向回復(Reverse-Recovery)之問題,當 功率半導體開關導通之暫態期間,二極體必須以瞬間大電 流以建立逆偏電壓,此電流流經功率半導體開關,引起嚴 重之切換損失與低轉換效率。基於以上所述,傳統昇壓式 換流器並未具有高昇壓比功能,因此,其侷限於昇壓7倍 以下之直流電源轉換應用上,並且無法達成高效率之電源 轉換機制。 因此許多專家學著提出昇壓換流技術,改善上述傳統 昇壓式換流器缺點。以下將目前世界上領先之昇壓換流技 術彙整比較,以更進一步凸顯本發明之具減低開關耐壓效 能之高效率高昇壓比換流器技術突破之優點。 1. C. W. Roh, S. H. Han? M. J. Youn, uDual coupled inductor fed isolated boost converter for low input voltage applications,” Electronics Letters, \o\. 35, pp. 1791-1792, 1999. 2. E· S. da Silva,L. dos Reis Barbosa,J. B. Vieira,Jr.,L. C. de Freitas,and V. J. Farias, “An improved boost PWM soft-single-switched converter with low voltage and current stresses/9 IEEE Transactions on Industrial Electronics^ vol. 48? pp. 1174-1179, 2001. 3· Q. Zhao,and F· C· Lee,“High-efficiency,high step_up DC-DC converters^ IEEE Transactions on Power Electronics^ vol. 189 pp. 65-73,2003. 4· D. C. Lu,D. K. W. Cheng,and Y· S. Lee,“A single-switch continuous-conduction-mode boost converter with reduced 1239136 reverse-recovery and switching losses/9 IEEE Transactions on Industrial Electronics,, vol. 50, pp. 767-776, 2003. 5. K. Hirachi,and M· Nakaoka,“UPS circuit configuration incorporating buck-boost chopper circuit with two magnetically coupled coils/5 Electronics Letters, vol. 39? pp. 1345-1346, 2003. 6· C· M· C· Duarte,and I· Barbi,“An improved family of ZVS_PWM active-clamping DC-to-DC converters^ IEEE Transactions on1239136 D. Description of the invention: [Technical field to which the invention belongs] Applications for multiple power sources, such as gas discharge headlamps, high-voltage DC busbars of inverters in uninterruptible power systems, wideband traveling wave tube amplifiers, etc., both A high-voltage DC power supply is required. However, traditional batteries are generally used as the power source. Therefore, the development of a high boost ratio converter is a necessary power conversion mechanism. The high efficiency and high boost ratio converter with reduced switching withstand voltage performance of the present invention can convert the low output voltages of traditional storage batteries, fuel cells, solar power and wind power to high voltage DC power supply systems, which greatly improves energy utilization. Rate and increase power supply stability. The technical field covered by the present invention includes the fields of power electronics, DC / DC converter technology and energy technology.``Although the technical field involved in the present invention is wide, it is mainly to develop high efficiency and high boost voltage with reduced switching withstand voltage performance. Than the inverter device to improve the lack of conventional inverters. [Previous technology] Traditional boost converters can adjust the duty cycle of the output voltage by adjusting the duty cycle of the switch. When applied to high boost ratios, the duty cycle needs to be adjusted to a maximum value. However, the equivalent resistance (ESR) of the inductor in the converter causes the boost ratio to be limited. It cannot operate in a situation where the boost ratio exceeds 7 times and the conversion efficiency is not good. Furthermore, when the power semiconductor switch of the boost converter is turned off, the voltage value at both ends is the output voltage, which is a voltage that is several times higher than the input voltage, forcing the power semiconductor to choose the high withstand voltage. And it has a larger two = (Rds ^ w) 'forming a higher conduction loss. In addition, the diode in the traditional boost converter 1239136 has a reverse-recovery problem. During the transient state of the power semiconductor switch, the diode must use an instantaneous high current to establish the reverse bias. Voltage, this current flows through the power semiconductor switch, causing severe switching losses and low conversion efficiency. Based on the above, the traditional boost converter does not have a high boost ratio function, so it is limited to DC power conversion applications with a boost of 7 times or less, and cannot achieve a high-efficiency power conversion mechanism. Therefore, many experts have learned to propose a boost converter technology to improve the shortcomings of the conventional boost converter. The following is a comparison of the world's leading boost converter technologies to further highlight the advantages of the invention's breakthrough in high efficiency and high boost ratio converter technology with reduced switching withstand voltage performance. 1. CW Roh, SH Han? MJ Youn, uDual coupled inductor fed isolated boost converter for low input voltage applications, "Electronics Letters, \ o \. 35, pp. 1791-1792, 1999. 2. E · S. Da Silva L. dos Reis Barbosa, JB Vieira, Jr., LC de Freitas, and VJ Farias, "An improved boost PWM soft-single-switched converter with low voltage and current stresses / 9 IEEE on on Industrial Electronics ^ vol. 48? pp. 1174-1179, 2001. 3 · Q. Zhao, and F · C · Lee, “High-efficiency, high step_up DC-DC converters ^ IEEE Transactions on Power Electronics ^ vol. 189 pp. 65-73,2003. 4 · DC Lu, DKW Cheng, and Y · S. Lee, "A single-switch continuous-conduction-mode boost converter with reduced 1239136 reverse-recovery and switching losses / 9 IEEE Transactions on Industrial Electronics ,, vol. 50, pp 767-776, 2003. 5. K. Hirachi, and M. Nakaoka, "UPS circuit configuration incorporating buck-boost chopper circuit with two magnetically coupled coils / 5 Electronics Letters, vol. 39? Pp. 1345-1346, 2003. 6 · C · M · C · Duarte, and I · Barbi, "An improved family of ZVS_PWM active-clamping DC-to-DC converters ^ IEEE on

Power Electronics^ vol. 17, pp. 1-7, 2002. 參 考 文 獻 輸入 電壓 輸出 電壓 輸出 容量 轉換 效率 電路架構 優缺點比較 [1] 12V 150V 90W 87% 雙耦合電感 優點:高昇壓比 缺點:架構複雜 [2] 80V 200V 400W 97.5% 變壓器 優點:具柔性切換 缺點:昇壓比最多四倍 [3] 60V 380V lkW 91.8% 柄合箝制 優點:架構簡單及使用 較低導通損零件 (250V開關) 缺點:昇壓比無法大幅 提昇、電壓低時 效率不彰及無法 克服線路電Ϊ突 波 [4] 100V 150V 200W 95% 耦合譜振 優點·具柔性切換 缺點:昇壓比低及電感 ___麥量大— 優點:單級直流昇壓轉 交流 缺點:無法用於電壓變 ———料電池 [5] 48V 340V 700W 86% 不斷電系統 1239136 及開關耐壓秦 [6] 300V 400V 1.6kW 98% 主動箝制 ——_______ Ι"ΓΊ ^ ’ _ΤΓΤ_ 1 優點:具柔性切換 缺點:昇壓比低及箝制 電壓高 本發明所揭示之具減低開關耐壓效能之高效率高昇壓 比換流器,運用三繞組之耦合電感,使得鐵粉芯更有效率 地全域操作,不需要增加功率半導體開關之責任週期,即 可大幅度提高傳統昇壓式換流器之昇壓比例,並且有助於 減低開關之耐壓規格,減少導通損失,另一方面,由於耦 a電感具有洩漏電感之特性,減低輸出端二極體逆向回復 之突波電流,達成高效率低壓直流電源轉換成高壓直流電 源之目的。 【發明内容】 一曰圖1表示本發明所揭示具減低開關耐壓效能之高效率 :昇壓比換流器方塊圖,其中包含一直流輸入電路101 :直 流輸入,壓[及輸人濾'波電容q所構成;直流輸人電壓匕與 遽波電容ς並聯相接,可降低直流輸人電壓「漣波;一一 次侧電路102: 一個輕合電感一次側Α及-個功率半導體開 關巧構成,輕合電感—次側&與功率半導體開關$串聯相 f ’ff功率半導體開f導通/截止控_合電感-次側 二丨,里儲存及釋放,一二次側電路1〇3 : -個耦合電感二 二貝1 2個—極體A及一個電容C2所構成;輕合電感二 人^ 2”—極體D2串聯相接,再偕同並聯電容C2 ; —三次 彳’J電路104 ·-個_合電感三次侧—個二極體^及一個 1239136 電容c3所構成;耦合電感三次側z3與二極體/¾串聯相接, -再偕同並聯電容c3 ; —直流輸出電路105 : —個二極體A、 輸出濾波電容Q及負載足所構成;二極體/¾連接濾波電容 C;之正端,同時濾波電容C0亦與負載凡並聯相接;一閉迴 路控制機制106:由電壓命令與直流輸出電壓G迴授比較產 生誤差值,經比例積分控制、脈波寬度調變及驅動放大電 路,輸出為可調整責任週期比之驅動訊號vg,觸發及截止 功率半導體開關S。一次側電路102、二次側電路103與三 次侧電路104之結合方式係以耦合電感一次侧4之正端連 鲁 接耦合電感三次侧A之負端,耦合電感一次侧心之負端與 功率半導體開關S汲極接點處連接三次側電路104電容C3 之負端,三次側電路104二極體/¾之輸出端與三次側電路 10 4電容C3之正端接點處連接耦合電感二次側L2之正端與 二次側電路103電容C2之負端接點處。本發明乃利用直流輸 入電源,經所揭示之具減低開關耐壓效能之高效率高昇壓 比換流器電源轉換後,大幅提昇直流輸入電壓R之位準, 可應用於高電壓需求時之場合;當一次側電路102之功率半 ® 導體開關S導通時,先將直流輸入電壓源之能量儲存於一 次側電路102之耦合電感一次側,以及透過耦合電感將直流 輸入電壓源之能量儲存於三次側電路104之電容C3中;當一 次側電路102之功率半導體開關S截止時,將直流輸入電壓 源、耦合電感一次側、二次側電路103之電容C2以及三次側 電路104之電容C3四者串聯之能量,於直流輸出電路105之 二極體導通時,以電流型式傳導至直流輸出電路105,提 12 I239136 之直流輸出電壓;此時二次側電賴3之電容Q及 壓:路104之電容C3承受大部分直流輸出電路脱跨 ^輪出電壓與該跨壓之差值,即為一次側電路1〇2 流輪tr開^兩端所承受之轉,該電壓遠小於直 之致处髮’故―次侧電路1G2之功率半導體關具低耐壓 中,:,耦合電感-次側電流開始下降逐漸變為零過程 由交=粉芯磁通連續特性,表現㈣合電感二次側電流 C =越上升,接近岭值時,開始對二次侧電路⑻之電容Power Electronics ^ vol. 17, pp. 1-7, 2002. References Input Voltage Output Voltage Output Capacity Conversion Efficiency Circuit Architecture Comparison of Advantages and Disadvantages [1] 12V 150V 90W 87% Dual Coupling Inductor Advantages: High Boost Ratio Disadvantages: Complex Architecture [2] 80V 200V 400W 97.5% Transformer Advantages: Flexible switching Disadvantages: Up to four times the boost ratio [3] 60V 380V lkW 91.8% Handle-clamping Advantages: Simple structure and use of lower conduction loss parts (250V switch) Disadvantages: The step-up ratio cannot be greatly improved, the efficiency is not good when the voltage is low, and it is unable to overcome the line electrical surge [4] 100V 150V 200W 95% coupled spectral vibration advantages and flexible switching disadvantages: low step-up ratio and inductance ___ wheat amount Large— Advantages: Single-stage DC boost to AC Disadvantages: Ca n’t be used for voltage change ——— Battery battery [5] 48V 340V 700W 86% Uninterruptible power system 1239136 and switch withstand voltage Qin [6] 300V 400V 1.6kW 98% Active clamping ——_______ Ι " ΓΊ ^ '_ΤΓΤ_ 1 Advantages: Flexible switching Disadvantages: Low boost ratio and high clamping voltage The high efficiency and high efficiency of the switch with reduced voltage withstanding capability disclosed by the present invention Compared with the converter, the three-winding coupling inductor is used to make the iron powder core operate more efficiently in the whole region. Without increasing the duty cycle of the power semiconductor switch, the boost ratio of the traditional boost converter can be greatly improved. It also helps to reduce the withstand voltage specifications of the switch and reduce the conduction loss. On the other hand, because the coupling inductor has the characteristic of leakage inductance, it reduces the surge current of the reverse recovery of the diode at the output terminal, and achieves high-efficiency low-voltage DC power conversion Purpose of high voltage DC power supply. [Summary of the Invention] Figure 1 shows the high efficiency of the switch withstand voltage reduction efficiency disclosed in the present invention: a block diagram of a boost ratio converter, which includes a DC input circuit 101: DC input, voltage [and input filter ' It is composed of wave capacitor q; the DC input voltage dagger is connected in parallel with the 电容 wave capacitor, which can reduce the DC input voltage "ripple; a primary circuit 102: a light-on inductor primary side A and a power semiconductor switch Clever construction, light closing inductor-secondary side & series connection with power semiconductor switch f 'ff power semiconductor on f on / off control _ switching inductance-secondary side 2 丨 storage and release inside, primary and secondary circuit 1〇 3: 2 coupled inductors, 12 poles-composed of pole body A and a capacitor C2; two light-sense inductors ^ 2 "-pole body D2 connected in series, and then connected to the parallel capacitor C2;-three times' J The circuit 104 is composed of the third side of the inductor—a diode ^ and a 1239136 capacitor c3; the third side of the coupling inductor z3 is connected in series with the diode / ¾, and then the same parallel capacitor c3 is used; 105: one diode A, output filter capacitor Q, and load Diode / ¾ connected to filter capacitor C; the positive terminal, and at the same time, filter capacitor C0 is also connected in parallel with the load; a closed loop control mechanism 106: the error value is generated by comparing the voltage command with the feedback of the DC output voltage G, After proportional integral control, pulse width modulation and driving amplifier circuit, the output is a driving signal vg with adjustable duty cycle ratio, and the power semiconductor switch S is triggered and cut off. The combination of the primary side circuit 102, the secondary side circuit 103, and the tertiary side circuit 104 is to connect the positive end of the primary side 4 of the coupled inductor to the negative side of the tertiary side A of the coupled inductor, and the negative side of the primary side of the coupled inductor and power. The drain terminal of the semiconductor switch S is connected to the negative terminal of the tertiary-side circuit 104 capacitor C3, and the output terminal of the tertiary-side circuit 104 diode / ¾ and the tertiary-side circuit 104 are connected to the positive terminal of the capacitor C3 for a second time. The positive terminal of the side L2 is connected to the negative terminal of the capacitor C2 of the secondary-side circuit 103. The present invention utilizes a DC input power supply, and after the disclosed high-efficiency and high-boost-ratio converter power supply with reduced switching withstand voltage performance, the level of the DC input voltage R is greatly improved, which can be applied to occasions where high voltage is required ; When the power semi-conductor switch S of the primary circuit 102 is turned on, first store the energy of the DC input voltage source on the primary side of the coupling inductor of the primary circuit 102, and store the energy of the DC input voltage source three times through the coupling inductor The capacitor C3 of the side circuit 104; when the power semiconductor switch S of the primary circuit 102 is turned off, the DC input voltage source, the coupled inductor primary side, the capacitor C2 of the secondary circuit 103 and the capacitor C3 of the tertiary circuit 104 The series energy is conducted to the DC output circuit 105 in a current mode when the diode of the DC output circuit 105 is turned on, and the DC output voltage of 12 I239136 is raised; at this time, the capacitor Q and the voltage of the secondary side are 3: circuit 104 The capacitor C3 withstands the difference between the output voltage of most DC output circuits and the voltage across this voltage. In the turn, the voltage is much smaller than the direct cause. Therefore, the power semiconductor switch of the secondary circuit 1G2 has a low withstand voltage. The coupling inductor-secondary current starts to decrease and gradually becomes zero. Continuous characteristic, showing the secondary side current of the coupled inductor C = increases, and when approaching the ridge value, the capacitance of the secondary side circuit starts

Li因此電容^之電壓在—週期内達成平衡。 本^日収善先前技術之原理及對照功效如下: •=側電路102、二次側電路1〇3及三次侧電路1〇4之Li therefore, the voltage of the capacitor ^ reaches equilibrium in a period. The principles and comparative effects of the prior art collected today are as follows: • = of the side circuit 102, the secondary side circuit 103 and the tertiary side circuit 104

^合,具提高昇壓比例、減低功率半導體開關$之财壓 見格之效能:利用耦合電感匝數與電壓成比例之特性, 本發明之裝置具高昇壓比之特性,提供較高於傳統昇壓 ^換流器之昇壓比例;二次側電路1〇3之電容Q以及三 人側,路1 〇4之電容q上電壓,分擔一次侧電路丨之 力率半導體開關$兩端之跨壓,使此電壓低於直流輸出 電路105之輸出電壓&。 2·減低功率半導體開關$财壓規格降低導通損失:一次側 電路102之功率半導體開關$兩端之跨壓被限制於低壓 範圍’可以選用較低耐壓值之MOSFET,因其具較低之 ^阻抗可減低導通損失,進而提升轉換效率。 當:芯利用率:運用三繞組之耦合電感, 一 $關導通s時,耦合電感三次侧之電流對 13 1239136 三次側電路104之電容^充電,類似傳統順向式換流哭 之工作原理;當功率半導體開關S截止時,儲存於 電感上能量透過耦合電感二次側,對負載端釋放能量, 再對二次側電路103之電容C2充電,此工作原理與傳统 返馳式換流器雷同;基於以上所述,三繞組之輕合電感 在全域操作之下,增加該耦合電感鐵粉芯之利用率。 4.耦合電感之漏感減少輸出端二極體逆向回復之問題:當 一次側電路102之功率半導體開關截止時,輪出端二二 體導通—極體電流斜率為耦合電感之漏感函數,其電 流遞減至零而截止,減少其逆向回復之問題,不造成反 向電流突波’減少元件發熱與功率雜,進而提升轉換 效率。 、 5·閉沿,控制機制1〇6: 一般直流輸入電路之直流輸 二:壓K易隨負載變化,可以藉由閉迴路控制機制1〇6 急疋直流輸出電路1〇5之直流輸出電壓&。 【實施方式】 ° 圖2表示本發明所揭示之具減低開關耐壓效能之高效 =昇壓比換流器等效電路,其中三繞組輕合電感利用一 、、且對-之理想變壓器、激磁電感&及等效漏感^表示, ,此理想變壓器之Ε數為%、%以及%,其隨比〜及% 可表不如下: (1) (2) 之電容C2及三 ’假設二次側電路 η2 二 Ν2 丨 Νγ η3 定義一次側跨壓為 Ϊ239136 -人側電路1G4之電容q夠大可視為定電壓源,其電壓分別 為匕2與匕3 ’並且將直流輸入電路1〇1簡化為定電壓源g。 圖3表不本發明所揭示之換流器電壓及電流波形時序。圖 4表示本發明工作模式,其說明如下·· 模式一 [〜G】:Combined, it has the effect of increasing the boost ratio and reducing the financial pressure of the power semiconductor switch $: By utilizing the characteristic that the number of turns of the coupled inductor is proportional to the voltage, the device of the present invention has the characteristics of high boost ratio and provides higher than traditional Boost ^ converter boost ratio; the capacitor Q on the secondary side circuit 103 and the voltage on the capacitor q on the three-side circuit 104 share the power of the primary side circuit Cross voltage, make this voltage lower than the output voltage & of the DC output circuit 105. 2 · Reduce the power semiconductor switch $ financial voltage specification to reduce the conduction loss: the cross-voltage across the power semiconductor switch $ of the primary circuit 102 is limited to the low voltage range. MOSFETs with lower withstand voltage can be selected because they have lower ^ Impedance can reduce conduction loss and improve conversion efficiency. When: Core utilization rate: When the three-winding coupling inductor is used, the current on the tertiary side of the coupling inductor is charged to the capacitor ^ of the third-side circuit 104 when it is turned on, which is similar to the working principle of the traditional forward commutation cry. When the power semiconductor switch S is turned off, the energy stored in the inductor passes through the secondary side of the coupled inductor, releases energy to the load end, and then charges the capacitor C2 of the secondary side circuit 103. This working principle is similar to that of a traditional flyback converter Based on the above, under the full-range operation of the three-winding light-coupling inductor, the utilization ratio of the coupled inductor iron powder core is increased. 4. The leakage inductance of the coupled inductor reduces the problem of reverse recovery of the diode at the output terminal: When the power semiconductor switch of the primary circuit 102 is turned off, the diode at the wheel output terminal is turned on-the slope of the pole current is the leakage inductance function of the coupled inductor. Its current is reduced to zero and cut off, which reduces the problem of reverse recovery, which does not cause reverse current surges, reduces component heating and power noise, and thereby improves conversion efficiency. 5. Closed edge, control mechanism 106: DC input of general DC input circuit 2: The voltage K is easy to change with the load, and the DC output voltage of the DC output circuit 105 can be rushed by the closed-loop control mechanism 106. &. [Embodiment] ° FIG. 2 shows the high-efficiency circuit with reduced switching withstand voltage disclosed in the present invention = an equivalent circuit of a step-up ratio converter, in which the three-winding light-winding inductor uses an ideal transformer and excitation of Inductance & equivalent leakage inductance ^ indicates that, the E number of this ideal transformer is%,%, and%, and its ratios ~ and% can be expressed as follows: (1) (2) the capacitance C2 and the three 'assumed two The secondary side circuit η2, Ν2 丨 Νγ η3 defines the primary side-span voltage to be Ϊ239136-the capacitance q of the human-side circuit 1G4 is large enough to be regarded as a constant voltage source, and its voltage is dagger 2 and dagger 3 ′ and the DC input circuit 1 〇 1 Simplified to a constant voltage source g. FIG. 3 shows the voltage and current waveform timings of the converter disclosed in the present invention. FIG. 4 shows the working mode of the present invention, which is explained as follows: Mode 1 [~ G]:

…當時間戶6時,功率半導體開關S導通,二極體从、Α 逆偏,一極體£>3導通,此時直流輸入電壓透過耦合電感對 三次侧電路104之電容q充電,經由克希荷夫電壓電流定 律可推導出電容充電電流^、激磁電感電流^及輕合電 感一次側電流仏之變化率如下所示: ^1=沾-m仏":、 dt n3\ (3)… When the time household 6 is turned on, the power semiconductor switch S is turned on, the diodes are reverse biased from A, and the first pole £ & 3 is turned on. At this time, the DC input voltage charges the capacitor q of the tertiary-side circuit 104 through the coupling inductor, Kirchhoff's law of voltage and current can be used to derive the rate of change of the capacitor charging current ^, the magnetizing inductor current ^, and the light-inductance primary-side current 仏 as follows: ^ 1 ==-m 仏 ":, dt n3 \ (3 )

UC3-VS dt n,Lm (4) djjA^ (^ + n3)Vs-VC3 dt —' (5) 且激磁電感上電壓UC3-VS dt n, Lm (4) djjA ^ (^ + n3) Vs-VC3 dt — '(5) and the voltage on the magnetizing inductor

(6) n3 模式-中’直流輸入電μ對激磁電感4、輕合電感漏感」 二次側電路104之電容c3充電,儲存能量於激磁電感1 漏感4及電容c3中。 模式一-[〜<2 I : 開闕兩端電壓 ’二極體^逆 當時間時,功率半導體開關S截止, 4上升至G—FC2-厂C3,二極體A及Z)2導通 15 1239136 偏,激磁電感及耦合電感漏感上之電流,流經二次側電路 103之電容q及三次側電路1〇4之電容^ ,對負載釋放能 量;理想變壓器透過磁耦合的方式,將激磁電感上能量傳 導至理想變壓器二次側%,變壓器二次侧%之電流亦流向 直流輸出電路105,對負載釋出能量。利用克希荷夫電壓 定律,可推導出電壓之關係式如下:(6) n3 mode-Medium ’DC input μ is used to charge the magnetizing inductor 4 and the leakage inductance.” The capacitor c3 of the secondary circuit 104 is charged, and the energy is stored in the leakage inductance 4 of the magnetizing inductor 1 and the capacitor c3. Mode 1-[~ < 2 I: When the voltage across the switch is' diode ^ inverse time, the power semiconductor switch S is turned off, 4 rises to G-FC2-factory C3, and diodes A and Z) 2 are turned on 15 1239136 The bias, magnetizing and coupling inductance leakage currents flow through the capacitor q of the secondary-side circuit 103 and the capacitor 104 of the tertiary-side circuit ^ to release energy to the load; ideally, the transformer uses magnetic coupling to The energy on the excitation inductor is conducted to the ideal transformer secondary side%, and the current on the secondary side% of the transformer also flows to the DC output circuit 105 to release energy to the load. Using Kirchhoff's voltage law, the relationship of voltage can be derived as follows:

Vds(() + VC2+VC3=V〇 ⑺ VC2=^2^Nl(t) ⑻ vL^(0 = vNl(t)-^(V^ hVu(0^K X (9) l + «2 此時開關上之耐壓為Vds (() + VC2 + VC3 = V〇⑺ VC2 = ^ 2 ^ Nl (t) ⑻ vL ^ (0 = vNl (t)-^ (V ^ hVu (0 ^ KX (9) l + «2 at this time The withstand voltage on the switch is

Vds (0 = vs- VNI (t) ~ VLk (t) = V〇-VC2-K:3 (10)Vds (0 = vs- VNI (t) ~ VLk (t) = V〇-VC2-K: 3 (10)

<K 由式(10)可得知,本換流器具減低開關耐壓之效能,有助 於選取低耐壓低導通損失之半導體開關元件,以提升換流 器之轉換效率。利用上述之激磁電感4及耦合電感漏感4 上電壓’可推導出電流變化率如下: ^L: (^C2 \ (11) dt —(r ) n2Lm dt :n2(-V0 + Vs+VC3) + (l + n2)VC2 n2 (12) dt =n2 (V0 ~Vs-VC3)-(Un2+Lk/Lm)VC7 n22 Lk (13) (14) 1239136 宇=u2(-k+r+d+(i+^fC2 at 1 2 τ «2 4 模式 n22Lm [G〜6】: 當時間户6時,二次侧電路103之電容C2放電電流遞 減至零值’ ,激磁電感之能量透過理想變壓器, 對二次侧電路ι〇3之電容c2充電,因此電容c2之電流呈現 負值,其電流變化率如式(14)所表示。另一方面,三次側 電路104之電容ς則持續對負載放電,其電流變化率可由 式(12)所表示’與之串聯路徑之電流隨時間遞減。 模式四[6〜纟4】: 當時間户6時,耦合電感一次侧之電流遞減至零值, Ζ·Ζ1 (纟3 ) - 0耗合電感之所儲存之能量以麵合電感二次側電流 所呈現,此時二極體Α逆偏,電流‘遞減至零值,此電流 截止速率如式(12)所表示,可減輕因輸出端二極體D。逆向 回復所產生電流突波之問題,而激磁電感上所儲存之能量 則持續對二次侧電路103之電容Q充電,激磁電感上之電 流變化率如(11)式所表示,激磁電感之電流呈線性遞減,二 次侧電路103之電容C2充電電流變化率為 ^ diD2 = VC2 dt dt 一 n22 Lm (15) 一次側電路l〇3之二極體電流心2與激磁電感之電流k呈比 例關係,二極體電流k亦呈線性遞減之函數。因漏感之電 流為零,電流變化率亦為零,因此漏感上之電壓為零值, 1239136 使得功率半導體開關s電壓降低,該功率半導體開關之兩 端電壓值可表示為 (16)< K It can be known from formula (10) that the efficiency of the switching device in reducing the withstand voltage of the switch helps to select a semiconductor switching element with a low withstand voltage and a low conduction loss, so as to improve the conversion efficiency of the converter. Using the above voltages of the excitation inductance 4 and the coupling inductance leakage inductance 4, the current change rate can be derived as follows: ^ L: (^ C2 \ (11) dt — (r) n2Lm dt: n2 (-V0 + Vs + VC3) + (l + n2) VC2 n2 (12) dt = n2 (V0 ~ Vs-VC3)-(Un2 + Lk / Lm) VC7 n22 Lk (13) (14) 1239136 Yu = u2 (-k + r + d + ( i + ^ fC2 at 1 2 τ «2 4 mode n22Lm [G ~ 6]: When the time is 6, the discharge current of the capacitor C2 of the secondary circuit 103 decreases to zero '. The energy of the magnetizing inductance passes through the ideal transformer. The capacitor c2 of the secondary circuit ι03 is charged, so the current of the capacitor c2 shows a negative value, and the current change rate is represented by equation (14). On the other hand, the capacitor Π of the tertiary circuit 104 continuously discharges the load, which The current change rate can be expressed by the formula (12), and the current of the series path decreases with time. Mode 4 [6 ~ 纟 4]: When the time is 6, the current of the primary side of the coupled inductor decreases to zero, ZZ · Z1 (纟 3)-0 The stored energy of the consuming inductor is represented by the secondary side current of the face-to-face inductor. At this time, the diode A is reverse biased and the current 'decreases to zero. The current cut-off rate is as shown in equation (12). All It can alleviate the problem of the current surge caused by the output diode D. Reverse recovery, and the energy stored on the field inductor continues to charge the capacitor Q of the secondary circuit 103, and the current change rate on the field inductor As shown by formula (11), the current of the magnetizing inductor decreases linearly, and the change rate of the charging current of the capacitor C2 of the secondary circuit 103 is ^ diD2 = VC2 dt dt-n22 Lm (15) The two poles of the primary circuit 103 The body current core 2 is proportional to the current k of the magnetizing inductor, and the diode current k is a linear decreasing function. Because the leakage current is zero and the current change rate is zero, the voltage on the leakage inductance is zero. , 1239136 reduces the voltage of the power semiconductor switch s, and the voltage value across the power semiconductor switch can be expressed as (16)

Vds (0 = K ^ VNl (0 假設所有元件均為理想情況下,二次側電路1〇3之電 容電壓匕2及三次侧電路1〇4之電容電壓K分別可表示為 KC2 = -《2 (’), tx&lt;t &lt;tA (17) VC3=(l + n3)Vs (18)Vds (0 = K ^ VNl (0 Assuming all components are ideal, the capacitor voltage K2 of the secondary side circuit 103 and the capacitor voltage K of the tertiary side circuit 104 can be expressed as KC2 =-<2 ('), Tx &lt; t &lt; tA (17) VC3 = (l + n3) Vs (18)

令功率半導體開關S導通之責任週期為d,利用式(6)、式 (9)、式(17)、式(18)及激磁電感上在一週期内之平均電壓為 零,可推導出昇壓比例如下:Let the duty cycle for turning on the power semiconductor switch S be d, and use formula (6), formula (9), formula (17), formula (18) and the average voltage of the magnetizing inductor in a cycle to be zero, which can be deduced The compression ratio is as follows:

K I — d d f- l-d (19) 由式(19)可得知,此電路之昇壓比例高於傳統昇壓式換流 器,可藉由調整匝數比彌補傳統昇壓式換流器昇壓比例之 不足。 圖5表示本發明所揭示之具減低開關耐壓效能之高效 率高昇壓比換流器實施例之一,採用之低壓電源為美國 H_Power公司所生產之燃料電池PowerPEMTM_PS25〇,此燃 料電池之額定輸出功率為250瓦特,額定輸出電壓為28伏特。本 實施例配合燃料電池輸出之電壓電流規格以及直流輸出電 路105輸出400伏特直流電壓,適當選取本發明所揭示具 減低開關耐壓效能之高效率高昇壓比換流器元件,功率半 導體開關 S選用 IRFPS4710 (100V,1^(〇&gt;0二 14mQ),具有 較低之導通阻抗,有利於減低導通損失,大幅提升換流器 1239136 之轉換效率,二極體A選用蕭特基二極體SR20100,亦可 減少其導通跨壓以利於提升效率,二極體/¾及A選用為 SFA1608,並聯緩震電路RCD於二極體乃2及乃3兩端,以降 低二極體逆偏時,因二極體之寄生電容與耦合電感二次側 及三次側之漏感諧振所造成之電壓突波,閉迴路控制機制 106使用TL494脈波寬度調變控制晶片,功率半導體開關 元件頻率操作於100kHz,輸出功率為20〜300瓦特,本實 施例詳細之規格如下:KI — dd f- ld (19) It can be known from equation (19) that the boost ratio of this circuit is higher than that of the traditional boost converter, and the traditional boost converter can be compensated by adjusting the turns ratio. Insufficient compression ratio. FIG. 5 shows one of the embodiments of the high-efficiency and high-boost converter with reduced switching withstand voltage efficiency disclosed by the present invention. The low-voltage power source used is a fuel cell PowerPEMTM_PS25 produced by the American company H_Power. The rated output of this fuel cell The power is 250 watts and the rated output voltage is 28 volts. In this embodiment, in accordance with the voltage and current specifications of the fuel cell output and the 400 volt DC voltage output by the DC output circuit 105, a high-efficiency and high-boost converter element disclosed in the present invention with reduced switching withstand voltage performance is appropriately selected. The power semiconductor switch S is selected IRFPS4710 (100V, 1 ^ (〇 &gt; 0 to 14mQ), has a low on-resistance, which is beneficial to reduce the on-conduction loss, and greatly improves the conversion efficiency of the converter 1239136. Diode A uses a Schottky diode SR20100 It can also reduce its on-state voltage to improve efficiency. The diode / ¾ and A are selected as SFA1608. The parallel damping circuit RCD is at the ends of the diodes 2 and 3 to reduce the reverse bias of the diode. Due to the voltage surge caused by the parasitic capacitance of the diode and the leakage inductance resonance of the secondary and tertiary sides of the coupling inductor, the closed-loop control mechanism 106 uses a TL494 pulse width modulation control chip, and the frequency of the power semiconductor switching element is operated at 100 kHz. The output power is 20 ~ 300 watts. The detailed specifications of this embodiment are as follows:

Vi :27〜38V V。 :400V K :534〜8000Ω c2 :4.75 //F C3 :4.75 β F Q :2200 //F C〇 :100 //F A :10.7 //H Lk :0.6 //H n2 :6.33 n3 :5Vi: 27 ~ 38V V. : 400V K: 534 ~ 8000Ω c2: 4.75 // F C3: 4.75 β F Q: 2200 // F C〇: 100 // F A: 10.7 // H Lk: 0.6 // H n2: 6.33 n3: 5

本發明所揭示之具減低開關耐壓效能之高效率高昇壓 比換流器實施例之一,操作於輸出功率300瓦特時,量測 之效率為94.1%,並記錄實測波形響應如下所述。圖6表 示功率半導體開關S之電壓及電流實測波形,圖中顯示出 該功率半導體開關截止時寄生電容充電,兩端電壓上升, 19 1239136 由於線路漏感之影響,開關電壓具有震盪之現象,穩定時 此電壓約為60伏特。圖7表示耦合電感一次側電流/Z1、耦 合電感二次側電流zD2及耦合電感三次側電流實測波 形,圖中顯示出耦合電感一次側及二次側電流在耦合電感 内能量傳遞時之響應,以及耦合電感三次側對電容C3之充 電電流。圖8 (a)、(b)與⑷分別表示二極體认、Z)2與Z)3之 電壓電流波形,由圖8 (a)顯示出二極體A在截止時,幾無 反向電流突波,有效減緩其逆向回復之問題。 圖9表示直流輸出電壓匕、直流輸出電流忍與燃料電 池之直流輸入電流/,·,在空載輸出功率0瓦特至滿載輸出功 率300瓦特間負載變化時之響應,在配合閉迴路控制機制 106及高頻操作下,燃料電池之直流輸入電流及直流輸出 電路105之輸出電壓之漣波很小,使燃料電池穩定工作並 輸出直流電壓400伏特。 圖10表示本發明所揭示之具減低開關耐壓效能之高 效率高昇壓比換流器實施例之一,採用燃料電池為直流輸 入電壓,操作於不同輸出功率時所對應之轉換效率,最高 轉換效率大於95%。 圖11表示本發明所揭示之具減低開關耐壓效能之高 效率高昇壓比換流器另一較佳實施例之方塊圖,其中包含 一直流輸入電路101 :直流輸入電壓R及輸入濾波電容6所 構成;直流輸入電壓G與濾波電容&lt;^並聯相接,可降低直 流輸入電壓K漣波;——次側電路102 : —個耦合電感一次 侧A及一個功率半導體開關S所構成;耦合電感一次側A與 1239136 體開相接,# 截止控制耦合電4一女 θ千¥體開關$導通/ 雷踗^久側Α之此置儲存及釋放,·一二次側 i:c:^ 再偕同並=容?感ΐΓ側W2串聯相接, 辑、上極體::電路104: 一個綱感三 個—極體乃3及一個電容c3所構成 】路丄:個電容c,個電感々及一個二極❹α所構 一直、:於^式為電容4、二極料與電感4串聯相接; 負載Γ戶L盖Ϊ路105: 一個二極體D°、輸出遽波電容仏及 、、載二斤構成’二極體Z)0連接遽波電容c。之正端,同時濾 波電谷C;亦與負載 &lt; 並聯相接;—閉迴路控制機制106 : 由電麼命令與直流輸出電壓F〇迴授比較產生誤差值,經比 例=分控制、脈波寬度調變及驅動放大電路,輸出為可調 整責任週期比之驅動訊號Vg,觸發及截止功率半導體開關 X。一次側電路102、二次側電路103、三次側電路1〇4與 輔助電路1104之結合方式係以耦合電感一次側心之正端連 接輔助電路1104電容Q之負端,輔助電路11〇4電容c之 正端與輔助電路1104二極體仏輸出端接點處連接耦^電 感三次側4之負端,耦合電感一次侧A之負端與功率半導 體開關^汲極接點處連接輔助電路11〇4二極體a輸入端與 輔助電路1104電感夂之負端接點處,輔助電路11〇4電感夂 之正端連接三次侧電路104電容q之負端,三次側電路1〇: 二極體A之輸出端與三次側電路104電容q之正端接點處 21 1239136 連接耦合電感二次侧4之正端與二次側電路l〇3電容6之 · 負端接點處。圖1與圖11最大不同處在於輔助電路1104, 輔助電路1104之電容Ca具再提高直流輸出電路105之輸出 電壓,以及吸收線路中洩漏電感造成功率半導體開關S突 波電壓之功能;當功率半導體開關S截止時,耦合電感一 次側低壓大電流經輔助電路1104之二極體从對電容C;充 電,該電容並吸收一次側電路102線路中洩漏電感之能 量,以減緩功率半導體開關S峰值電壓震盪情形。另一方 面,由於耦合電感一次側電流絕大部分對電容充電,降 籲 低流經直流輸出電路105之二極體仏電流峰值,此電流路 徑亦經輔助電路1104之電感A,該電感目的在於減小電流 爬升速率,加強降低直流輸出電路105之二極體電流峰 值功能,並使此電流較為平均,降低導通損失。 圖12表示本發明所揭示之具減低開關耐壓效能之高 效率高昇壓比換流器另一較佳實施例,採用燃料電池做為 直流輸入電壓,直流輸出電壓400V及輸出功率300W時之 實測波形;圖12(a)為直流輸出電路105之二極體A電壓及 鲁 電流,相較於圖8(a)之電流波形,圖12(a)顯示出電流峰值 明顯降低且平均,此電流路徑導至直流輸出電路105高壓 側,該較佳之實施例具有高電壓低電流及低電壓大電流特 性,充分運用元件之特性及容量,使輸出電壓及電流漣波 減低;圖12(b)為輔助電路1104之二極體電壓及電流, 顯示出當功率半導體開關S截止時,耦合電感大部分流經 輔助電路1104之二極體A,對輔助電路1104之電容(^充 22 1239136 電。 - 雖然本發明已以前述較佳實施例揭示,然其並非用以 限定本發明,任何熟習此技藝者,再不脫離本發明之精神 和範圍内,當可作各種之變動與修改,因此本發明之保護 範圍當視後附之申請專利範圍所界定者為準。 【圖式簡單說明】 圖1本發明之具減低開關耐壓效能之高效率高昇壓比換 流器方塊圓。 圖2本發明之具減低開關耐壓效能之高效率高昇壓比換 _ 流器等效電路圖。 圖3本發明之具減低開關耐壓效能之高效率高昇壓比換 流器,電壓及電流之波形時序。 圖4本發明之具減低開關耐壓效能之高效率高昇壓比換 流器,電路工作模式圖。 圖5本發明之具減低開關耐壓效能之高效率高昇壓比換 流器實施例之一,使用燃料電池為電源供應之電路 圖。 ® 圖6本發明之具減低開關耐壓效能之高效率高昇壓比換 流器實施例之一,功率半導體開關S跨壓4與電流心之 實測波形。 圖7本發明之具減低開關耐壓效能之高效率高昇壓比換 流器實施例之一,耦合電感一次側電流z_zl、耦合電感 二次側電流及耦合電感三次側電流zD3之實測波 形0 23 1239136 圖8本發明之具減低開關耐壓效能之高效率高昇壓比換 流器實施例之一,二極體電壓電流實測波形:(a)直 流輸出電路之二極體跨壓與電流心;(b)二次側 電路之二極體Z)2跨壓vD2與電流zD2 ; (c)三次側電路之 二極體Z)3跨壓vD3與電流zD3。 圖9本發明之具減低開關耐壓效能之高效率高昇壓比換 流器實施例之一,直流輸出電壓匕、直流輸出電流忍 與燃料電池之直流輸入電流/,·在負載變化時之暫態實 測波形。 圖10本發明之具減低開關耐壓效能之高效率高昇壓比換 流器實施例之一,操作於不同輸出功率對應之轉換效 率。 圖11本發明之具減低開關耐壓效能之高效率高昇壓比換 流器另一較佳實施例之方塊圖。 圖12本發明之具減低開關耐壓效能之高效率高昇壓比換 流器另一較佳實施例,二極體電壓電流實測波形:⑻ 直流輸出電路之二極體A跨壓與電流k ; (b)輔助 電路之二極體Ζ)α跨壓與電流心。 圖式主要部分之編號代表意義如下: 101 :直流輸入電路 102 : —次側電路 103 :二次側電路 104 :三次側電路 105 :直流輸出電路 24 1239136 106 :閉迴路控制機制 · 1104 :輔助電路 G:直流輸入電壓 :直流輸入電流 q :直流輸入電路之濾波電容 夕:功率半導體開關 ··半導體開關之驅動訊號 A :耦合電感一次側 乙:耦合電感二次侧 ⑩ 尽:耦合電感三次側 C2 :二次側電路之電容 D2 :二次侧電路之二極體 C3 :三次侧電路之電容 Z)3 :三次侧電路之二極體 A :直流輸出電路之二極體 C;:直流輸出電路之濾波電容 足:直流輸出電路之負載 ® G :直流輸出電壓 八:直流輸出電流 Ca :輔助電路之電容 A:輔助電路之二極體 A:輔助電路之電感 25One of the embodiments of the high-efficiency and high-boost-ratio converter with reduced switching withstand voltage efficiency disclosed by the present invention operates at an output power of 300 watts, the measured efficiency is 94.1%, and the measured waveform response is recorded as follows. Figure 6 shows the measured voltage and current waveforms of the power semiconductor switch S. The figure shows that the parasitic capacitance is charged when the power semiconductor switch is turned off, and the voltage at both ends rises. 19 1239136 Due to the effect of line leakage inductance, the switching voltage has the phenomenon of oscillation and stability. This voltage is about 60 volts. Figure 7 shows the measured waveforms of the coupled inductor primary current / Z1, the coupled inductor secondary current zD2, and the coupled inductor tertiary current. The figure shows the response of the coupled inductor primary and secondary currents during the energy transfer in the coupled inductor. And the charging current of the coupling inductor C3 to the capacitor C3. Figures 8 (a), (b) and 表示 show the voltage and current waveforms of diodes, Z) 2 and Z) 3, respectively. Figure 8 (a) shows that diode A has almost no reverse direction when it is turned off. The current surge effectively reduces the problem of reverse recovery. Figure 9 shows the response of the DC output voltage, DC output current tolerance, and DC input current of the fuel cell when the load changes between 0 watts of no-load output power and 300 watts of full-load output power, in cooperation with the closed-loop control mechanism 106 Under high-frequency operation, the ripple of the DC input current of the fuel cell and the output voltage of the DC output circuit 105 is small, which enables the fuel cell to work stably and output a DC voltage of 400 volts. FIG. 10 shows one of the embodiments of the high-efficiency and high-boost-ratio converter with reduced switching withstand voltage efficiency disclosed by the present invention, which uses a fuel cell as a DC input voltage and operates at different output powers corresponding to the conversion efficiency, the highest conversion Efficiency is greater than 95%. FIG. 11 shows a block diagram of another preferred embodiment of a high-efficiency and high-boost converter with reduced switching withstand voltage efficiency disclosed in the present invention, which includes a DC input circuit 101: a DC input voltage R and an input filter capacitor 6 The DC input voltage G is connected in parallel with the filter capacitor &lt; ^, which can reduce the DC input voltage K ripple;-the secondary circuit 102: a coupling inductor primary side A and a power semiconductor switch S; coupling The primary side A of the inductor is connected to the body of 1239136, # cut-off control coupling electric 4 a female θ thousand ¥ body switch $ on / thunder ^ storage and release of this side A, the primary side i: c: ^ Then, parallel connection = capacitance? Inductance Γ side W2 is connected in series, series, upper pole :: circuit 104: a sense of three-the pole body is 3 and a capacitor c3] circuit: a capacitor c, an inductor 々 and a two-pole ❹α have been constructed as follows: In the formula, capacitor 4 is used, and the two-pole material is connected in series with inductor 4; the load Γ is covered by the circuit 105: a diode D °, the output 遽 wave capacitor 仏, and The two diodes are used to form a 'diode Z) 0 connected to the chirped wave capacitor c. The positive terminal is simultaneously filtering the electric valley C; it is also connected in parallel with the load &lt;; closed-loop control mechanism 106: an error value is generated by comparing the electric command with the DC output voltage F0 feedback, and the proportional = minute control, pulse The wave width modulation and driving amplifier circuit outputs the driving signal Vg with adjustable duty cycle ratio, which triggers and cuts off the power semiconductor switch X. The combination of the primary circuit 102, the secondary circuit 103, the tertiary circuit 104 and the auxiliary circuit 1104 is to connect the positive terminal of the primary side of the coupled inductor to the negative terminal of the capacitor Q of the auxiliary circuit 1104 and the auxiliary circuit 104 capacitor. The positive terminal of c is connected to the auxiliary circuit 1104 at the output terminal of the diode, the negative terminal of the inductor three side 4, and the negative terminal of the primary side A of the coupled inductor is connected to the auxiliary circuit 11 at the drain terminal of the power semiconductor switch. 〇4 The junction of the input terminal of the diode a and the negative terminal of the auxiliary circuit 1104 inductor ,, the positive terminal of the auxiliary circuit 1104 is connected to the negative terminal of the capacitor q of the tertiary side circuit 104, and the tertiary side circuit 10: The output end of the body A and the positive terminal contact point 21 of the capacitor q of the tertiary circuit 104 are connected to the positive terminal 21 of the coupling inductor secondary side 4 and the negative terminal point of the capacitor 103 of the secondary side circuit 103. The biggest difference between FIG. 1 and FIG. 11 lies in the auxiliary circuit 1104. The capacitance Ca of the auxiliary circuit 1104 further increases the output voltage of the DC output circuit 105, and absorbs the leakage inductance in the line to cause the power semiconductor switch S surge voltage; when the power semiconductor When the switch S is turned off, the low voltage and large current of the primary side of the coupled inductor is charged from the capacitor C through the diode of the auxiliary circuit 1104, and the capacitor absorbs the energy of the leakage inductance in the circuit of the primary circuit 102 to slow down the peak voltage of the power semiconductor switch S Shock situation. On the other hand, since most of the primary side current of the coupled inductor charges the capacitor, it reduces the peak value of the current flowing through the diode of the DC output circuit 105. This current path also passes the inductance A of the auxiliary circuit 1104. The purpose of this inductance is to Reduce the current climbing rate, strengthen the function of reducing the peak value of the diode current of the DC output circuit 105, make the current more even, and reduce the conduction loss. FIG. 12 shows another preferred embodiment of the high efficiency and high boost ratio converter with reduced switching withstand voltage efficiency disclosed by the present invention. The fuel cell is used as a DC input voltage, a DC output voltage of 400V and an output power of 300W. Figure 12 (a) is the voltage and current of diode A of the DC output circuit 105. Compared with the current waveform of Figure 8 (a), Figure 12 (a) shows that the peak value of the current is significantly reduced and averaged. This current The path leads to the high-voltage side of the DC output circuit 105. This preferred embodiment has high-voltage low-current and low-voltage large-current characteristics. The characteristics and capacity of the components are fully used to reduce the output voltage and current ripple; Figure 12 (b) is The voltage and current of the diode of the auxiliary circuit 1104 shows that when the power semiconductor switch S is turned off, most of the coupling inductance flows through the diode A of the auxiliary circuit 1104, and the capacitance of the auxiliary circuit 1104 (^ 22 22 1239136 electricity.- Although the present invention has been disclosed in the foregoing preferred embodiments, it is not intended to limit the present invention. Any person skilled in the art can make various changes without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the present invention shall be subject to the definition of the scope of the attached patent application. [Brief description of the figure] Figure 1 The square block circle of the high efficiency and high boost ratio converter with reduced switch withstand voltage performance of the present invention Figure 2 Equivalent circuit diagram of high efficiency and high boost ratio converter with reduced switch withstand voltage performance according to the present invention. Figure 3 High efficiency and high boost ratio converter with reduced switch withstand voltage performance according to the present invention, voltage and current Waveform timing. Figure 4 The high efficiency and high boost ratio converter with reduced switching withstand voltage performance of the present invention, circuit working mode diagram. Figure 5 The high efficiency and high boost ratio converter with reduced switch withstand voltage performance of the present invention. One of the embodiments is a circuit diagram using a fuel cell as a power source. ® Figure 6 One of the embodiments of the high efficiency and high boost ratio converter with reduced switching withstand voltage performance of the present invention, the power semiconductor switch S spans the voltage 4 and the current core The measured waveforms. Figure 7 One of the embodiments of the high efficiency and high boost ratio converter with reduced switching withstand voltage performance of the present invention, the coupled inductor primary side current z_zl, the coupled inductor secondary side current and the coupled current Measured waveform of the tertiary side current zD3 0 23 1239136 Figure 8 One of the embodiments of the high efficiency and high boost ratio converter with reduced switching withstand voltage performance of the present invention, the measured waveform of the diode voltage and current: (a) of the DC output circuit Diode cross-voltage and current center; (b) Diode Z of the secondary-side circuit) 2 Cross-voltage vD2 and current zD2; (c) Diode Z- of the tertiary-side circuit) Cross-voltage vD3 and current zD3. Figure 9 One of the embodiments of the high efficiency and high boost ratio converter with reduced switching withstand voltage performance of the present invention, the DC output voltage, DC output current tolerance and DC input current of the fuel cell State measured waveform. Fig. 10 is one of the embodiments of the high efficiency and high boost ratio converter with reduced switching withstand voltage performance of the present invention, which operates at the conversion efficiency corresponding to different output powers. FIG. 11 is a block diagram of another preferred embodiment of the high-efficiency and high-boost-ratio converter with reduced switching withstand voltage performance of the present invention. Figure 12 another embodiment of the present invention has a high efficiency and high boost ratio converter with reduced switching withstand voltage performance, the diode voltage and current measured waveform: 跨 DC output circuit diode A across voltage and current k; (b) Diode Z) α of auxiliary circuit and voltage core and current core. The numbers of the main parts of the figure represent the following meanings: 101: DC input circuit 102:-Secondary side circuit 103: Secondary side circuit 104: Tertiary side circuit 105: DC output circuit 24 1239136 106: Closed-loop control mechanism1104: Auxiliary circuit G: DC input voltage: DC input current q: Filter capacitor of DC input circuit Xi: Power semiconductor switch ·· Semiconductor switch driving signal A: Coupling inductor primary side B: Coupling inductor secondary side 尽 End: Coupling inductor tertiary side C2 : Capacitance of the secondary circuit D2: Diode of the secondary circuit C3: Capacitance of the tertiary circuit Z) 3: Diode of the tertiary circuit A: Diode C of the DC output circuit;: DC output circuit The filter capacitor is sufficient: the load of the DC output circuit ® G: the DC output voltage eight: the DC output current Ca: the capacitor of the auxiliary circuit A: the diode of the auxiliary circuit A: the inductance of the auxiliary circuit 25

Claims (1)

1239136 拾、申請專利範圍: 1. 一種具減低開關耐壓效能之高效率高昇壓比換流器,其 中包含 一直流輸入電路:直流輸入電壓及輸入濾波電容所構 成;直流輸入電壓與濾波電容並聯相接,可降低直流輸 入電壓漣波; 一一次側電路:一個搞合電感一次側及一個功率半導體 開關所構成;耦合電感一次側與功率半導體開關串聯相 接,藉由功率半導體開關導通/截止控制耦合電感一次 _ 側之能量儲存及釋放; 一二次側電路:一個耦合電感二次側、一個二極體及一 個電容所構成;耦合電感二次側與二極體串聯相接,再 偕同並聯電容; 一三次側電路:一個耦合電感三次側、一個二極體及一 個電容所構成;耦合電感三次侧與二極體串聯相接,再 偕同並聯電容; 一直流輸出電路:一個二極體、輸出濾波電容及負載所 籲 構成;二極體連接濾波電容之正端,同時濾波電容亦與 負載並聯相接, 一閉迴路控制機制:由電壓命令與直流輸出電壓迴授比 較產生誤差值,經比例積分控制、脈波寬度調變及驅動 放大電路,輸出為可調整責任週期比之驅動訊號,觸發 及戴止功率半導體開關; 一次側電路之功率半導體開關導通時,先將直流輸入電 26 1239136 壓之能量儲存於一次側電路之耦合電感一次側,以高激 磁電流型式儲存,並透過耦合電感將直流輸入電壓源之 能量以變壓器原理傳送至三次側電路之電容中;當一次 側電路之功率半導體開關截止時,將直流輸入電壓、耦 合電感一次側、二次側電路之電容以及三次侧電路之電 容四者串聯之能量,於直流輸出電路之二極體導通時, 以電流型式傳導至直流輸出電路,提昇換流器之直流輸 出電壓;此時二次側電路之電容及三次側電路之電容承 受大部分直流輸出電路之跨壓,直流輸出電壓與該跨壓 之差值,即為一次側電路之功率半導體開關兩端之電 壓,該電壓遠小於直流輸出電壓,故一次侧電路之功率 半導體開關具低耐壓之效能;耦合電感一次侧電流開始 下降逐漸變為零過程中,因鐵粉芯磁通連續特性,表現 於耦合電感二次側電流由零交越上升,接近峰值時,開 始對二次側電路之電容充電; 其特徵為具有高昇壓比之特性,並且充分利用耦合電感 二次側及耦合電感三次側所建立之電壓值,大幅提高直 流輸出電壓位準;運用三繞組之耦合電感,提昇高頻磁 性元件鐵粉芯之利用率;具減低開關耐壓效能,可降低 一次側電路之功率半導體開關之耐壓規格,即可選用較 低導通阻抗之MOSFET,降低導通損失;輸出端可省略 濾波電感;直流輸出電路使用之二極體為低壓,低導通 電壓之蕭特基二極體,可降低導通損失;電路具低壓側 大電流,高壓侧低電流特性,可充分使用元件之規格與 1239136 容量,因此效率高於習用電路。 2. 如申請專利範圍第1項所述之具減低開關耐壓效能之高 效率高昇壓比換流器,其中直流輸入電路之電容,其材 質為一般電解電容或超電容,可吸收高頻諧波能量之成 份,穩定直流輸入電壓。 3. 如申請專利範圍第1項所述之具減低開關耐壓效能之高 效率高昇壓比換流器,其中直流輸出電路之電容,主要 功能為吸收來自二次側電路瞬間充電電流引起高頻諧 波能量之成份,並穩定直流輸出電路之輸出電壓。 4. 如申請專利範圍第1項所述之具減低開關耐壓效能之高 效率高昇壓比換流器,其中一次侧電路、二次側電路及 三次側電路之耦合電感能量傳遞原理,係將耦合電感一 次側線圈化分成三個階段提昇電壓;第一階段,當功率 半導體開關導通時,一次側電路之耦合電感一次側充 電,並透過變壓器操作原理,於三次側電路之二極體順 偏時,對該電路之電容充電;第二階段,當功率半導體 開關截止時,二次側電路之二極體順偏,儲存於耦合電 感一次側之能量,依照磁通不滅定理,以電流型式對負 載釋放能量;第三階段,功率半導體開關仍為截止時, 儲存於耦合電感一次側之剩餘磁通能量,依照磁通不滅 定理,對二次側電路之電容充電。 5. 如申請專利範圍第1項所述之具減低開關耐壓效能之高 效率高昇壓比換流器,其中一次側電路、二次側電路與 三次側電路結合,具減低開關耐壓效能,限制一次側電 28 !239136 路最大電壓;其結合方式係以鉍入+A ^ 7八你以耦合電感一次侧之正端連 · 接轉合電感三次侧之負端凄 心_合電感一次側之負端與功 '、+—導體開關及極接點處連接三次側電路電容之負 端,三次側電路二極體之輸出端與三次侧電路電容之正 $接點處連接輕合電感二次側之正端與二次侧電路電 各之負端接點處。 6· ^申請專利範圍第i項所述之具減低開關耐壓效能之 N效率南昇壓比換流器,其中直流輸入電壓源,係蓄電 f、太陽光電池、直流風力發電機及交流風力發電機整 φ 流為直流電源,作為電源供應。 7·:申睛士利範圍第&quot;員所述之具減低開關耐壓效能之 回效率间昇壓比換流器,其中直流輸入電壓源,可以使 用兩者或兩者以上不同電源供應,控制該電源輸入功率 之比例,以提尚整體直流電源輸出功率。 8· 一種具減低開關耐壓效能之高效率高昇壓比換流器,其 中包含 W ~ :直流輸入電路··直流輸入電壓及輸入濾波電容所構 · 成,直流輸入電壓與濾波電容並聯相接,可降低直流輸 入電壓漣波; 一次側電路··一個耦合電感一次側及一個功率半導體 開關所構成;耦合電感一次側與功率半導體開關串聯相 接’藉由功率半導體開關導通/截止控制耦合電感一次 側之能量儲存及釋放; 一一次側電路··一個耦合電感二次侧、一個二極體及一 29 1239136 個電容所構成;耦合電感二次側與二極體串聯相接,再 偕同並聯電容; 一三次側電路:一個耦合電感三次側、一個二極體及一 個電容所構成;耦合電感三次側與二極體串聯相接,再 偕同並聯電容; 一輔助電路:一個電容、一個電感及一個二極體所構 成;其連接方式為電容、二極體與電感串聯相接; 一直流輸出電路:一個二極體、輸出濾波電容及負載所 構成;二極體連接濾波電容之正端,同時濾波電容亦與 負載並聯相接, 一閉迴路控制機制:由電壓命令與直流輸出電壓迴授比 較產生誤差值,經比例積分控制、脈波寬度調變及驅動 放大電路,輸出為可調整責任週期比之驅動訊號,觸發 及截止功率半導體開關; 其特徵為具有高昇壓比之特性,並且充分利用耦合電感 二次側及耦合電感三次側所建立之電壓值,大幅提高直 流輸出電壓位準;運用三繞組之耦合電感,提昇高頻磁 性元件鐵粉芯之利用率;具減低開關耐壓效能,可降低 一次側電路之功率半導體開關之耐壓規格,即可選用較 低導通阻抗之MOSFET,降低導通損失;輸出端可省略 濾波電感;直流輸出電路使用之二極體為低壓,低導通 電壓之蕭特基二極體,可降低導通損失;電路具低壓側 大電流,高壓側低電流特性,可充分使用之元件規格與 容量,因此效率高於習用電路;輔助電路使用之二極體 1239136 為低壓,低導通電壓之蕭特基二極體,可降低導通損 1 失;輔助電路之電容使該換流裝置具有再提高昇壓比之 功能;輔助電路之電容及二極體串聯方式之組合,具有 減少線路上洩漏電感對開關造成電壓突波之功能;輔助 電路之電容、二極體及電感串聯方式之組合具有減低直 流輸出電路之二極體電流峰值及平均該電流之功能。 9. 如申請專利範圍第8項所述之具減低開關耐壓效能之高 效率高昇壓比換流器,其中直流輸入電路之電容,其材 質為一般電解電容或超電容,可吸收高頻諧波能量之成 _ 份,穩定直流輸入電壓。 10. 如申請專利範圍第8項所述之具減低開關耐壓效能之高 效率高昇壓比換流器,其中一次側電路、二次側電路、 三次側電路與輔助電路之結合,具減低開關耐壓效能, 限制一次側電路最大電壓;其結合方式係以耦合電感一 次側之正端連接輔助電路電容之負端,輔助電路電容之 正端與輔助電路二極體輸出端接點處連接耦合電感三 次側之負端,耦合電感一次侧之負端與功率半導體開關 · 汲極接點處連接輔助電路二極體輸入端與輔助電路電 感之負端接點處,輔助電路電感之正端連接三次側電路 電容之負端,三次侧電路二極體之輸出端與三次側電路 電容之正端接點處連接耦合電感二次側之正端與二次 側電路電容之負端接點處。 11. 如申請專利範圍第8項所述之具減低開關耐壓效能之 高效率高昇壓比換流器,其中直流輸入電壓源,係蓄電 31 1239136 池、太陽光電池、直流風力發電機及交流風力發電機整 流為直流電源,作為電源供應。 ΐ2.=申請專利範圍第8項所述之具減低開關耐壓效能之 高效率高昇壓比換流器,其中直流輸入電壓源,可以使 用兩者或兩者以上不同電源供應、,控制該電源輸入功率 之比例,以提高整體直流電源輸出功率。1239136 Patent application scope: 1. A high-efficiency, high-boost converter with reduced switching withstand voltage performance, which includes a DC input circuit: a DC input voltage and an input filter capacitor; the DC input voltage is connected in parallel with the filter capacitor Connected to reduce the ripple of DC input voltage; Primary circuit: a combination of the primary side of the inductor and a power semiconductor switch; the primary side of the coupled inductor is connected in series with the power semiconductor switch, and the power semiconductor switch is turned on / The cutoff controls the energy storage and release of the primary side of the coupled inductor; the primary and secondary circuits: a secondary side of the coupled inductor, a diode, and a capacitor; the secondary side of the coupled inductor is connected in series with the diode, and then偕 Same parallel capacitors; one-to-three-side circuit: a coupled inductor tertiary side, one diode, and one capacitor; the three-side of the coupled inductor is connected in series with the diode, and then the same parallel capacitor; one DC output circuit: one two The polar body, the output filter capacitor and the load are called; the diode is connected to the positive end of the filter capacitor At the same time, the filter capacitor is also connected in parallel with the load. A closed loop control mechanism: the error value is generated by comparing the voltage command with the DC output voltage feedback. After proportional integral control, pulse width modulation and driving the amplifier circuit, the output is adjustable responsibility. The driving signal of the cycle ratio triggers and stops the power semiconductor switch. When the power semiconductor switch of the primary circuit is turned on, the energy of the DC input 26 1239136 voltage is stored in the primary side of the coupled inductor of the primary circuit. Store and transfer the energy of the DC input voltage source to the capacitor of the tertiary circuit through the principle of the transformer through the coupling inductor; when the power semiconductor switch of the primary circuit is turned off, the DC input voltage, the coupling inductor primary and secondary circuits The energy of the four capacitors in series with the capacitor of the tertiary circuit is conducted to the DC output circuit in a current mode when the diode of the DC output circuit is turned on, and the DC output voltage of the converter is increased. Capacitors and capacitors of the tertiary circuit withstand most DC output The voltage across the circuit, the difference between the DC output voltage and this voltage is the voltage across the power semiconductor switch of the primary circuit. This voltage is much smaller than the DC output voltage, so the power semiconductor switch of the primary circuit has a low withstand voltage. In the process that the primary side current of the coupled inductor starts to decline and gradually becomes zero, due to the continuous characteristics of the iron powder core, the secondary side current of the coupled inductor rises from zero crossing, and when it approaches the peak, it starts to the secondary side circuit. Capacitance charging; It is characterized by a high step-up ratio, and fully utilizes the voltage value established by the secondary side of the coupled inductor and the tertiary side of the coupled inductor to greatly improve the DC output voltage level; using the three-winding coupled inductor to increase the Frequency magnetic component iron powder core utilization rate; with reduced switching withstand voltage performance, can reduce the power semiconductor switch withstand voltage specifications of the primary circuit, you can choose a lower on-resistance MOSFET to reduce the conduction loss; filtering can be omitted at the output Inductance; the Schottky diode used in the DC output circuit is low voltage and low on-voltage, which can reduce the conduction Loss; low voltage side circuit having a large current, high-voltage low-side current characteristic of the element can be sufficiently used Specifications 1,239,136 and capacity, and therefore more efficient than conventional circuit. 2. The high efficiency and high boost ratio converter with reduced switching withstand voltage performance as described in item 1 of the scope of the patent application, where the capacitor of the DC input circuit is made of general electrolytic capacitor or super capacitor, which can absorb high frequency resonance The component of wave energy stabilizes the DC input voltage. 3. The high-efficiency and high-boost converter with reduced switching withstand voltage performance as described in item 1 of the scope of patent application, where the capacitance of the DC output circuit is mainly to absorb the high-frequency caused by the instantaneous charging current from the secondary circuit. The component of harmonic energy and stabilize the output voltage of the DC output circuit. 4. The high-efficiency and high-boost ratio converter with reduced switching withstand voltage performance as described in item 1 of the scope of patent application, in which the principle of coupled inductor energy transfer of the primary circuit, secondary circuit, and tertiary circuit is the principle The primary coil of the coupled inductor is divided into three stages to boost the voltage. In the first stage, when the power semiconductor switch is turned on, the coupled inductor of the primary circuit is charged on the primary side, and the diode of the tertiary circuit is forward biased through the principle of transformer operation. In the second stage, when the power semiconductor switch is turned off, the diode of the secondary circuit is forward-biased, and the energy stored in the primary side of the coupled inductor is stored in the current mode in accordance with the immortality theorem. The load releases energy; in the third stage, when the power semiconductor switch is still off, the residual magnetic flux energy stored in the primary side of the coupled inductor is charged in accordance with the law of magnetic flux immortality. 5. High efficiency and high boost ratio converter with reduced switching withstand voltage performance as described in item 1 of the scope of patent application, in which the primary side circuit, secondary side circuit and tertiary side circuit are combined to reduce switching withstand voltage performance, Limit the maximum voltage on the primary side 28! 239136; the combination is based on bismuth + A ^ 7 8 You connect the positive side of the primary side of the coupled inductor · Connect the negative side of the tertiary side of the switching inductor The negative terminal and work ', + —conductor switch and pole contact are connected to the negative terminal of the tertiary-side circuit capacitor, the output terminal of the tertiary-side circuit diode and the positive $ -contact of the tertiary-side circuit capacitor are connected to the light-on inductor 2. The positive terminal of the secondary side and the negative terminal of each of the secondary circuit circuits. 6. ^ The N-efficiency southern boost ratio converter with reduced switching withstand voltage performance as described in item i of the scope of the patent application, where the DC input voltage source is a storage battery f, a solar cell, a DC wind turbine, and an AC wind turbine. The entire φ current of the motor is a DC power supply as a power supply. 7 ·: The step-up ratio converter with reduced return voltage efficiency as described by the member of Shen Jingshili's range, with DC input voltage source, can use two or more different power supplies, Control the ratio of the input power of the power supply to improve the output power of the overall DC power supply. 8 · A high-efficiency, high-boost converter with reduced switching withstand voltage performance, which includes W ~: DC input circuit ·· DC input voltage and input filter capacitor are constructed, and the DC input voltage is connected in parallel with the filter capacitor , Can reduce the DC input voltage ripple; primary circuit ·· a coupling inductor primary side and a power semiconductor switch; the coupled inductor primary side and the power semiconductor switch are connected in series' by the power semiconductor switch on / off control coupling inductance Energy storage and release on the primary side; Primary circuit ... One coupling inductor secondary side, one diode and 29 1239136 capacitors; the secondary side of the coupling inductor is connected in series with the diode, and then different Parallel capacitors; a tertiary circuit: a coupled inductor tertiary side, a diode, and a capacitor; the tertiary side of the coupled inductor is connected in series with the diode, and then the same parallel capacitor; an auxiliary circuit: a capacitor, a It consists of an inductor and a diode; the connection method is that the capacitor, the diode and the inductor are connected in series; Current output circuit: a diode, an output filter capacitor and a load; the diode is connected to the positive end of the filter capacitor, and the filter capacitor is also connected in parallel with the load. A closed loop control mechanism: the voltage command and the DC output voltage The feedback comparison produces an error value. After proportional integral control, pulse width modulation and driving amplifier circuit, the output is a driving signal with adjustable duty cycle ratio, which triggers and cuts off the power semiconductor switch. It is characterized by a high boost ratio. And make full use of the voltage value established on the secondary side of the coupled inductor and the tertiary side of the coupled inductor to greatly improve the DC output voltage level; use the three-winding coupled inductor to improve the utilization rate of the high-frequency magnetic element iron powder core; reduce the switching resistance Voltage efficiency can reduce the withstand voltage specifications of the power semiconductor switch of the primary circuit. You can choose a MOSFET with a lower on-resistance to reduce the conduction loss; the output terminal can omit the filter inductor; the diode used in the DC output circuit is low voltage, low Schottky diode with on-voltage, which can reduce the conduction loss; Current, high-voltage side low current characteristics, can fully use the specifications and capacity of components, so the efficiency is higher than conventional circuits; the diode 1239136 used in the auxiliary circuit is a low voltage, low on-voltage Schottky diode, which can reduce the conduction loss 1 loss; the capacitance of the auxiliary circuit makes the converter have the function of further increasing the boost ratio; the combination of the capacitance of the auxiliary circuit and the series connection of the diodes has the function of reducing the voltage surge caused by the leakage inductance on the line; the auxiliary The combination of the capacitor, diode and inductor series of the circuit has the function of reducing the peak value of the diode current of the DC output circuit and averaging the current. 9. The high-efficiency and high-boost ratio converter with reduced switching withstand voltage performance as described in item 8 of the scope of patent application, where the capacitor of the DC input circuit is made of general electrolytic capacitor or super capacitor, which can absorb high-frequency harmonics. Constituent of the wave energy, stabilize the DC input voltage. 10. The high-efficiency and high-boost ratio converter with reduced switching withstand voltage performance as described in item 8 of the scope of the patent application, wherein the combination of the primary circuit, the secondary circuit, the tertiary circuit and the auxiliary circuit has a reduced switch The withstand voltage performance limits the maximum voltage of the primary circuit; its combination is that the positive terminal of the primary side of the coupling inductor is connected to the negative terminal of the auxiliary circuit capacitor, and the positive terminal of the auxiliary circuit capacitor is connected to the auxiliary circuit diode output terminal connection The negative terminal of the third side of the inductor, the negative terminal of the primary side of the coupling inductor is connected to the power semiconductor switch and the drain contact to the auxiliary circuit diode input terminal and the negative terminal of the auxiliary circuit inductor, and the positive terminal of the auxiliary circuit inductor is connected The negative terminal of the tertiary-side circuit capacitor, the output terminal of the tertiary-side circuit diode, and the positive-terminal contact of the tertiary-side circuit capacitor connect the positive end of the secondary side of the coupling inductor and the negative-terminal contact of the secondary-side circuit capacitor. 11. The high-efficiency, high-boost converter with reduced switching withstand voltage performance as described in item 8 of the scope of the patent application, where the DC input voltage source is a power storage 31 1239136 battery, solar cell, DC wind turbine and AC wind The generator is rectified into a DC power source as a power supply. ΐ2. = High efficiency and high boost ratio converter with reduced switching withstand voltage performance as described in item 8 of the scope of patent application, where the DC input voltage source can use two or more different power supplies to control the power supply Input power ratio to increase the overall DC power output. 3232
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Cited By (3)

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TWI467203B (en) * 2012-03-27 2015-01-01 Mitsubishi Electric Corp Method for diagnosing life of power storage device
CN113839557A (en) * 2021-08-24 2021-12-24 深圳航天科技创新研究院 Wide voltage range boost conversion topology
US11437844B1 (en) 2021-09-07 2022-09-06 Aeris Hospitality Solutions, LLC Booster for energy storage device

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TWI399911B (en) * 2009-10-05 2013-06-21 Univ Nat Cheng Kung Self-oscillating flyback power converter with snubber
TWI466423B (en) * 2012-01-19 2014-12-21 Univ Chienkuo Technology High boost power converter

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI467203B (en) * 2012-03-27 2015-01-01 Mitsubishi Electric Corp Method for diagnosing life of power storage device
CN113839557A (en) * 2021-08-24 2021-12-24 深圳航天科技创新研究院 Wide voltage range boost conversion topology
CN113839557B (en) * 2021-08-24 2024-04-09 深圳航天科技创新研究院 Boost conversion topology with wide voltage range
US11437844B1 (en) 2021-09-07 2022-09-06 Aeris Hospitality Solutions, LLC Booster for energy storage device

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