1237847 玖、發明說明： 【發明所屬之技術領域】 本發明是有關於一種具有電容元件之晶片結構及形 成電容元件於晶片上之方法’且特別是有關於一種電容$ 件配置在保護層處的晶片結構及其所對應之形成電容充件 於晶片之保護層處的方法。 【先前技術】 資訊產品在工商社會所扮演的角色已愈來愈重驾， 隨著資訊產品的推陳出新，尤其現在的電路設計均導入整 合的槪念，因此下一代的單一晶片往往比前一代的單〜晶 片整合有更多的功能。在整合之後’不但電路體積可以输 減，而且大部分信號間的傳遞僅在單一晶片內，因此可以 縮減信號間傳遞的路徑，而具有較高的電性效能。 一般而言，電路設計均會涵蓋有電容元件的設計， 一般係將部份之電容元件配置在晶片的內部或是在印刷電 路板上。當欲將電容元件配置在晶片的內部時，一般是利 用半導體製程，包括物理氣相沈積、化學氣相沈積及微影 蝕刻等製程，在製作晶片內的電路時，便直接形成電容元 件於晶片之基底上，而此種作法必須在晶片之基底處挪出 部份的空間，容置電容元件，因此會佔用形成電子元件的 面積，尤其在現今形成電子元件之單位成本日益高昂的時 代，將電容元件設置在基底上是不具效率性的作法。另外， 由於電容元件係配置在靠近基底處’因此電容元件所貯存 10966twf.doc/008 4 1237847 的電荷會干擾位在電容元件周圍處的電子元件，嚴重時會 使得電子元件運作錯誤’爲了避免上述的情況發生，電容 元件配置於晶片內的密度並不能甚高，且電容元件必須製 作得很小，如此電容元件所能貯存的電荷量會甚低。再者， 由於基底上配置有許多電子元件及線路，因此在受到這些 電子元件及線路的限制下，使得位在基底上的電容元件不 易作大幅度地修改。或者，亦可以藉由物理氣相沈積、化 學氣相沈積及微影蝕刻等製程，將電容元件形成在位於基 底上的細線路積層中。 再者’當電容元件形成在印刷電路板上時，一般是 利用表面黏著技術將電容元件接合到印刷電路板上。然 而’在此種作法下，晶片與電容元件之間的繞線距離會相 隔甚遠’ 一旦當晶片內之電子元件在瞬間缺電的狀態下， 配置在印刷電路板上的電容元件並不能即時地供應電源給 電子元件’而會有一段延遲時間，故此種作法並不能提供 高效能的電路配置。 另外’在最新的技術中，還提出將電容元件配置在 晶片之保護層上的槪念，如美國專利第6,3〇3,423號、第 6,455,885 號、第 M89,647 號、第 6,489,656 號及第 6,515,369 號中所述。 【發明內容】 因此本發明目的之一就是提供一種具有電容元件之 晶片結構及形成電容元件於晶片上之方法，由於電容元件 10966twf.doc/008 1237847 係配置在靠近保護層的位置’因此可以將晶片之基底保留 更多的空間來配置電子元件。 本發明目的之一*就是提供一^種具有電容兀件之晶片 結構及形成電容元件於晶片上之方法’由於電容元件係配 置在遠離晶片之基底處’因此可以避免電容元件所貯存之 電荷干擾到位在晶片之基底上的電子元件。 本發明目的之三就是提供一種具有電容元件之晶片 結構及形成電容元件於晶片上之方法’由於電容元件係配 置在靠近保護層處，且電子元件並不會形成在保護層的位 置，因此在保護層處可以有較大的空間來形成電容元件’ 故可以形成具有較大電容値之電谷兀件於晶片上’且電谷 元件的尺寸也易於修正， 本發明目的之四就是提供一種具有電容元件之晶片 結構及形成電容元件於晶片上之方法，由於電容元件之電 容介電層是利用前段之半導體製程所完成，因此可以精確 地控制電容介電層的厚度，如此電容元件之電容値便可以 精確地控制。 在敘述本發明之前，先對空間介詞的用法做界定’ 所謂空間介詞“上，，係指兩物之空間關係係爲可接觸或不 可接觸均可。舉例而言，A物在B物上，其所表達的意思 係爲A物可以直接配置在B物上，A物有與B物接觸； 或者A物係配置在B物上的空間中，A物沒有與B物接 觸。 爲達成本發明之上述及其他之目的，提出一種形成 10966twf.doc/008 6 1237847 電容元件於晶片上之方法，首先形成一第一電極到一晶片 之一介電層上，然後形成一保護層到介電層上及第一電極 上。接下來，形成一保護層開口貫穿保護層，藉以暴露出 第一電極，之後形成一電容介電層到保護層開口所暴露出 之第一電極上。然後，形成一第二電極到電容介電層上。 爲達成本發明之上述及其他之目的，還提出一種具 有電容元件之晶片結構，包括一基底、一積層、一第一電 極、一保護層、一電容介電層及一第二電極。基底具有多 個電子元件，配置在基底之表層。積層位在基底上，積層 具有多層介電層、多層線路層及多個導電孔洞，介電層係 依序疊層在基底上，線路層係分別位在相鄰之介電層之 間，相鄰之線路層係透過導電孔洞電性連接，而線路層係 與電子元件電性連接。第一電極位在積層上，而保護層位 在積層上，且保護層具有一保護層開口，暴露出第一電極。 電容介電層位在保護層開口所暴露出之第一電極上，而第 二電極位在電容介電層上。 綜上所述，本發明之具有電容元件之晶片結構及形 成電容元件於晶片上之方法，由於電容元件係配置在保護 層的附近位置，因此可以將晶片之基底保留更多的空間來 配置電子元件，且可以避免電容元件所貯存之電荷干擾到 位在晶片之基底上的電子元件。另外，由於電容元件係配 置在保護層上下附近，且電子元件並不會形成在保護層的 位置，因此在保護層處可以有較大的空間來形成電容元 件，故可以形成具有較大電容値之電容元件於晶片上，且 10966twf.doc/008 7 1237847 電容元件的尺寸也易於修正。再者，由於電容元件之電容 介電層是利用前段之半導體製程所完成，因此可以精確地 控制電容介電層的厚度，如此電容元件之電容値便可以精 確地控制。 爲讓本發明之上述和其他目的、特徵、和優點能更 明顯易懂，下文特舉較佳實施例，並配合所附圖式，作詳 細說明如下： 【實施方式】 第一賓施朝 第1A圖到第1N圖繪不依照本發明第一較佳實施例 之晶片上製作電容元件之剖面示意圖。請先參照第1A圖 所示，在晶圓廠中，形成比如是電晶體或金屬氧化半導體 之多個電子元件112到基底110之表層，其中基底110的 材質比如是矽。接著要依序形成多層介電層122、124、126、 128及多層線路層132、134、136到基底110上，藉以形 成一積層120，其中介電層122係依序疊層在基底上，而 線路層係分別位在相鄰之介電層之間，而相鄰的線路層 132、134、136可以透過導電孔洞123、125使其電性連接， 而線路層132、134、136可以與電子元件112電性連接。 另外，還形成電容元件之第一電極152到積層120之介電 層128上，而第一電極152比如是利用物理氣相沈積的方 式沈積鋁或鋁合金而成，或是亦可以利用陰刻法 (Damascene)的方式沈積銅或銅合金而成，其中第一電極 10966twf.doc/008 8 1237847 152的厚度dl比如介於〇·〇5微米到2微米之間。之後， 還形成一保護層140到積層120上，保護層140會覆蓋第 一電極152，而藉由保護層140可以防止環境中的水氣、 雜質、移動離子或過渡金屬元素進入到晶片1〇〇內。 接下來要定義保護層開口的位置，請參照第1Β圖到 第1D圖，其係先形成比如是光阻之一罩蔽層182到保護 層140上，並利用微影的方式，將光罩上的一圖案轉移到 罩蔽層182，使得罩蔽層182在第一電極152的位置形成 一開口 183，暴露出保護層140，如第1Β圖所示。接著利 用罩蔽層182作爲蝕刻罩蔽，蝕刻位在罩蔽層182之開口 183下的保護層140，藉以形成貫穿保護層140之保護層 開口 142，其中保護層開口 142暴露出第一電極152，如 第1C圖所示。之後，還要將罩蔽層182從保護層140上 去除，如第1D圖所不。 請參照第1Ε圖，接下來可以形成一電容介電層154 到保護層開口 142所暴露出之第一電極152上及保護層140 上，其中電容介電層154的厚度d2比如介於0.005微米到 2微米之間。 電容介電層154比如可以利用下列數種方式形成： 第一種：電容介電層154係以化學氣相沈積的方式， 沈積四乙院基氧石夕甲院（tetraethylorthosilicate，TEOS)、 氧矽化合物、氮矽化合物、氮氧矽化合物、五氧化二鉬 (Ta205)、鈦酸緦（SrTi03)或鈦酸緦鋇（BST)而成； 第二種：電容介電層154係以物理氣相沈積的方式， 10966twf.doc/008 9 1237847 沈積五氧化二鉅（Ta205)、鈦酸緦（SrTi03)或鈦酸緦鋇（BST) 而成； 第三種：係先以化學氣相沈積的方式沈積矽到第一 電極152上之後，再以熱氧化法的方式使所沈積的矽與氧 進行化學反應，藉以形成氧矽化合物，此氧矽化合物係作 爲電容介電層154的材質。 如上所述，電容介電層154可以是上述任一材質的 單層結構，或者電容介電層154亦可以是上述部份材質所 構成之複合層結構。 接下來，去除部份之電容介電層，藉以暴露出晶片 之接點的位置，使得外界線路可以與晶片之接點接合。其 作法比如有兩種，第一種是僅保留形成在第一電極上的電 容介電層，而將其餘部份之電容介電層去除；第二種是將 電容介電層一整層地保留在保護層上，而僅在晶片之接點 的位置形成開口，藉以暴露出晶片之接點。在本實施例中， 係以第一種作法作說明。請參照第1F圖到第1H圖，其係 先形成比如是光阻之一罩蔽層184到電容介電層154上， 並利用微影的方式，將光罩上的一圖案轉移到罩蔽層184， 使得罩蔽層184形成有暴露區域185，暴露出電容介電層 154,如第1F圖所示。接著利用罩蔽層184作爲蝕刻罩蔽， 以濕蝕刻或是乾蝕刻的方式蝕刻位在罩蔽層184之暴露區 域185下的電容介電層154,在鈾刻電容介電層154之後， 保護層140會暴露於外，且電容介電層154形成有一開口 155 ’暴路出第一電極152，定義爲電容接點151，如第ig 10966twf.doc/008 10 1237847 圖所示。之後’還要將罩蔽層184從電容介電層154上去 除，如第1H圖所示。 接下來’要進行製作連接線路及電容元件之第二電 極之製程’請參照第II圖到第1M圖，首先比如利用濺鍍 的方式，形成~黏著層172到電容介電層154上、保護層 140上及電容接點151上，如第II圖所示，其中黏著層172 係由下列部份或全部之金屬，鈦、鈦鎢合金、鈦氮化合物、 鉻銅合金及鉻，所構成之單層結構或多層結構。接著，形 成比如是光阻之一罩蔽層186到黏著層172上，並利用微 影的方式，將光罩上的一圖案轉移到罩蔽層186，使得罩 蔽層186形成有開口 187、188，暴露出黏著層172，其中 開口 187係定義出與第一電極152連接之連接線路的圖 案，而開口 188係定義出電容元件之第二電極的圖案，如 第1J圖所示。接下來，比如利用電鍍的方式，形成一金 屬層174到位在罩蔽層186之開口 187、188下的黏著層172 上，其中金屬層174之結構係由下列部份或全部之金屬， 銅、鎳及金，所構成之單層結構或多層結構，如第1K圖 所示，舉例而言，第二電極比如是由鈦層及銅層由下而上 地疊合而成；或是由鈦層、銅層及鎳層由下而上地疊合而 成；或是由鈦層、銅層、鎳層及金層由下而上地疊合而成； 或是由鈦鎢合金層及金層由下而上地疊合而成。之後’還 要將罩蔽層186從黏著層172上去除，而暴露出黏著層 172，如第1L圖所示。接下來，還要再去除暴露於外的黏 著層172，如此連接線路158及電容元件150之第二電極 10966twf.doc/008 11 1237847 156便製作完成，如第1M圖所示，而電容元件150之第 二電極156的厚度d3比如是介於1微米到50微米之間。 其中連接線路158可以透過電容介電層154之開口 155與 電容元件150之第一電極152電性連接，連接線路158及 電容元件150之第二電極156係分別由不同區域之黏著層 172及金屬層174所構成。 最後，請參照第1N圖，可以形成一絕緣層190到保 護層140上，其中絕緣層190會覆蓋電容元件150及連接 線路158，藉以保護電容元件150及連接線路158，其中 絕緣層190之材質係爲聚醯亞胺、苯基環丁烯、聚亞芳香 基醚、多孔性介電材質或彈性體等。 在本發明中，由於電容元件150係配置在靠近保護 層140的位置，因此可以將晶片100之基底11〇保留更多 的空間來配置電子元件Π2，且在保護層140處可以有較 大的空間來形成電容元件150，故可以形成具有較大電容 値之電容元件150於晶片1〇〇上，且電容元件150的尺寸 也易於修正。另外，由於電容元件150係配置在遠離晶片 100之基底110處，因此可以避免電容元件150所貯存之 電荷干擾到位在晶片100之基底110上的電子元件112。 此外，由於電容元件150之電容介電層154是利用前段之 半導體製程所完成，因此可以精確地控制電容介電層154 的厚度，如此電容元件150之電容値便可以精確地控制。 第一實施例 10966twf.doc/008 12 1237847 然而本發明製作電容元件的製程並不限於第一實施 例，亦可以是如第二實施例所述，請參照第2A圖到第2E 圖，其繪示依照本發明第二較佳實施例之晶片上製作電容 元件之剖面示意圖。第2A圖係接續第1H圖之製程，其 中若是本實施例中的標號與第一實施例一樣者，則表示在 本實施例中所指明的構件係雷同於在第一實施例中所指明 的構件，在此便不再贅述。 在定義電容介電層之形狀後，可以形成一絕緣層286 到保護層140上，其中絕緣層286比如是感光性材質，此 時可以利用微影的方式，將光罩上的一圖案轉移到絕緣層 286，使得絕緣層286形成有開口 287、288，其中開口 287 係定義出連接線路的圖案，而暴露出第一電極152之電容 接點151;開口 288係定義出電容元件之第二電極的圖案， 而暴露出電容介電層154，如第2A圖所示。接下來可以 利用濺鍍的方式，形成一黏著層272到絕緣層286上，且 黏著層272還形成到位在絕緣層286之開口 287、288下 的電容介電層154上及電容接點151上，如第2B圖所示’ 其中黏著層272係由下列部份或全部之金屬，鈦、鈦鎢合 金、鈦氮化合物、鉻銅合金及鉻，所構成之單層結構或多 層結構。接下來，比如利用電鍍的方式，形成一金屬層274 到黏著層272上，且金屬層274會塡入到絕緣層286之開 口 287、288中，其中金屬層274之結構係由下列部份或 全部之金屬，銅、鎳及金，所構成之單層結構或多層結構， 如第2C圖所示，舉例而言，第二電極比如是由鈦層及銅 10966twf.doc/008 13 1237847 層由下而上地疊合而成；或是由鈦層、銅層及鎳層由下而 上地疊合而成；或是由鈦層、銅層、鎳層及金層由下而上 地疊合而成；或是由鈦鎢合金層及金層由下而上地疊合而 成；或是由鉻層、鉻銅合金層及銅層由下而上地疊合而成。 接下來，可以利用化學機械硏磨(Chemical Mechanical Polishing，CMP)的方式，去除位在絕緣層286之開口 287、 288外的金屬層274及黏著層272，直到絕緣層286之上 表面暴露於外才停止化學機械硏磨的動作，如第2D圖所 示。其中連接線路258可以透過電容介電層154之開口 155 與電容元件250之第一電極152電性連接，連接線路258 及電容元件250之第二電極256係分別由不同區域之黏著 層272及金屬層274所構成。 最後，請參照第2E圖，可以形成一絕緣層290到絕 緣層286上，其中絕緣層290會覆蓋電容元件250及連接 線路258，藉以保護電容元件250及連接線路258。 此外，絕緣層286、290之材質比如是聚醯亞胺、苯 基環丁烯、聚亞芳香基醚、多孔性介電材質或彈性體等。 第三賓施莫 然而本發明製作電容元件的製程並不限於第一實施 例及第二實施例，亦可以是如第三實施例所述，請參照第 3A圖到第3E圖，其繪示依照本發明第三較佳實施例之晶 片上製作電容元件之剖面示意圖。第3A圖係接續第1H 圖之製程，其中若是本實施例中的標號與第一實施例一樣 10966twf.doc/008 14 1237847 綜上所述，本發明至少具有下列優點·· 1·本發明之具有電容元件之晶片結構及形成電容元件 於晶片上之方法，由於電容元件係配置在靠近保護層的位 置，因此可以將晶片之基底保留更多的空間來配置電子元 件。 2·本發明之具有電容元件之晶片結構及形成電容元件 於晶片上之方法，由於電容元件係配置在遠離晶片之基底 處，因此可以避免電容元件所貯存之電荷干擾到位在晶片 之基底上的電子元件。 3.本發明之具有電容元件之晶片結構及形成電容元件 於晶片上之方法，由於電容元件係配置在靠近保護層處， 且電子元件並不會形成在保護層的位置，因此在保護層處 可以有較大的空間來形成電容元件，故可以形成具有較大 電容値之電容元件於晶片上，且電容元件的尺寸也易於修 正， 4·本發明之具有電容元件之晶片結構及形成電容元件 於晶片上之方法，由於電容元件之電容介電層是利用前段 之半導體製程所完成，因此可以精確地控制電容介電層的 厚度，如此電容元件之電容値便可以精確地控制。 雖然本發明已以較佳實施例揭露如上，然其並非用 以限定本發明，任何熟習此技藝者，在不脫離本發明之精 神和範圍內，當可作各種之更動與潤飾，因此本發明之隔 離範圍當視後附之申請專利範圍所界定者爲準。 10966twf.doc/008 16 1237847 【圖式簡單說明】 第1A圖到第1N圖繪示依照本發明第一較佳實施例 之晶片上製作電容元件之剖面示意圖。 第2A圖到第2E圖繪示依照本發明第二較佳實施例 之晶片上製作電容元件之剖面示意圖。 第3A圖到第3E圖繪示依照本發明第三較佳實施例 之晶片上製作電容元件之剖面示意圖。 【圖式標示說明】 100 :晶片 110 :基底 112 :電子元件 120 :積層 122 :介電層 123 :導電孔洞 124 :介電層 125 :導電孔洞 126 :介電層 128 :介電層 132 :線路層 134 :線路層 136 :線路層 140 :保護層 142 :保護層開口 150 :電容元件 151 :電容接點 152 :第一電極 154 :電容介電層 155 :開口 156 :第二電極 158 :連接線路 172 :黏著層 174 :金屬層 182 :罩蔽層 183 ··開口 184 :罩蔽層 185 :暴露區域 10966twf.doc/008 171237847 发明 Description of the invention: [Technical field to which the invention belongs] The present invention relates to a wafer structure having a capacitor element and a method for forming a capacitor element on a wafer ', and more particularly to a capacitor element disposed at a protective layer. The chip structure and the corresponding method for forming a capacitor charge at the protective layer of the chip. [Previous technology] The role of information products in the industrial and commercial society has become more and more important. With the introduction of information products, especially the current circuit design has introduced the idea of integration, so the single chip of the next generation is often more than the previous generation. Single-chip integration has more functions. After integration ', not only the circuit volume can be reduced, but most of the transmission between signals is only in a single chip, so the path between signals can be reduced, and it has higher electrical performance. Generally speaking, the design of a circuit will include the design of a capacitive element. Generally, a part of the capacitive element is arranged inside the chip or on a printed circuit board. When the capacitor element is to be arranged inside the wafer, a semiconductor process is generally used, including processes such as physical vapor deposition, chemical vapor deposition, and lithographic etching. When the circuit in the wafer is fabricated, the capacitor element is directly formed on the wafer. On the substrate, this method must free up some space at the substrate of the wafer to accommodate the capacitive element, so it will take up the area to form the electronic component, especially in the era when the unit cost of forming the electronic component is increasingly high. It is not efficient to place the capacitive element on the substrate. In addition, since the capacitive element is arranged near the substrate, the electric charge stored in the capacitive element 10966twf.doc / 008 4 1237847 will interfere with the electronic components located around the capacitive element, and in severe cases will cause the electronic components to operate incorrectly. It happens that the density of the capacitor element in the chip cannot be very high, and the capacitor element must be made small, so the amount of charge that the capacitor element can store will be very low. In addition, since many electronic components and circuits are arranged on the substrate, it is difficult for the capacitive elements located on the substrate to be greatly modified under the restrictions of these electronic components and circuits. Alternatively, the capacitor element can be formed in a thin circuit layer on a substrate by processes such as physical vapor deposition, chemical vapor deposition, and lithographic etching. Furthermore, when the capacitor element is formed on a printed circuit board, the capacitor element is generally bonded to the printed circuit board using a surface adhesion technique. However, 'In this way, the winding distance between the chip and the capacitor will be far apart.' Once the electronic components in the chip are in a state of instantaneous power loss, the capacitors placed on the printed circuit board cannot be instantaneous. There will be a delay time when power is supplied to the electronic components, so this method cannot provide a high-performance circuit configuration. In addition, in the latest technology, the idea of disposing a capacitor element on the protective layer of a wafer is also proposed, such as U.S. Patent Nos. 6,303,423, 6,455,885, M89,647, 6,489,656, and No. 6,515,369. [Summary of the Invention] Therefore, one of the objectives of the present invention is to provide a wafer structure with a capacitor element and a method for forming a capacitor element on a wafer. Since the capacitor element 10966twf.doc / 008 1237847 is arranged near the protective layer, it can be The substrate of the wafer leaves more space for electronic components. One of the objectives of the present invention is to provide a chip structure with a capacitor element and a method for forming a capacitor element on the wafer. 'Since the capacitor element is disposed at a substrate far from the wafer,' the interference of charges stored in the capacitor element can be avoided. Electronic components in place on the substrate of the wafer. The third object of the present invention is to provide a wafer structure with a capacitor element and a method for forming a capacitor element on a wafer. 'Since the capacitor element is disposed near the protective layer, and the electronic element is not formed in the protective layer, The protective layer can have a large space to form a capacitor element, so an electric valley element having a larger capacitance can be formed on the wafer, and the size of the electric valley element is also easy to modify. The fourth object of the present invention is to provide The chip structure of the capacitor element and the method for forming the capacitor element on the wafer. Since the capacitor dielectric layer of the capacitor element is completed by the previous semiconductor process, the thickness of the capacitor dielectric layer can be accurately controlled. It can be precisely controlled. Before describing the present invention, the use of space prepositions is defined. The so-called "space prepositions" means that the spatial relationship between the two objects is accessible or inaccessible. For example, the A object is on the B object. What it means is that object A can be directly placed on object B, and object A is in contact with object B; or in the space where object A is disposed on object B, object A is not in contact with object B. In order to achieve the invention For the above and other purposes, a method for forming a 10966twf.doc / 008 6 1237847 capacitor element on a wafer is proposed. First, a first electrode is formed on a dielectric layer of a wafer, and then a protective layer is formed on the dielectric layer. Next, a protective layer opening is formed through the protective layer to expose the first electrode, and then a capacitor dielectric layer is formed on the first electrode exposed by the protective layer opening. Then, a protective layer is formed. The second electrode is on the capacitor dielectric layer. In order to achieve the above and other objects of the present invention, a wafer structure with a capacitor element is also provided, which includes a substrate, a build-up layer, a first electrode, a protective layer, and a capacitor. A dielectric layer and a second electrode. The substrate has a plurality of electronic components arranged on the surface layer of the substrate. The layer is located on the substrate, and the layer has multiple dielectric layers, multiple circuit layers, and multiple conductive holes. The dielectric layers are in sequence Laminated on the substrate, the circuit layers are located between adjacent dielectric layers, the adjacent circuit layers are electrically connected through conductive holes, and the circuit layers are electrically connected to electronic components. The first electrode is located at And the protective layer is located on the laminated layer, and the protective layer has a protective layer opening to expose the first electrode. The capacitor dielectric layer is located on the first electrode exposed by the protective layer opening and the second electrode is located on On the capacitor dielectric layer. In summary, according to the present invention, the wafer structure with a capacitor element and the method for forming a capacitor element on the wafer, since the capacitor element is arranged near the protective layer, the substrate of the wafer can be kept more More space for electronic components, and can avoid the stored charge of the capacitors from interfering with the electronic components on the substrate of the chip. In addition, because the capacitors are configured to protect Near the top and bottom of the layer, and the electronic components are not formed in the protective layer position, so there can be a large space at the protective layer to form a capacitive element, so a capacitive element with a larger capacitance can be formed on the chip, and 10966twf .doc / 008 7 1237847 The size of the capacitor element is also easy to modify. Furthermore, because the capacitor dielectric layer of the capacitor element is completed by the previous semiconductor process, the thickness of the capacitor dielectric layer can be precisely controlled. Capacitance can be precisely controlled. In order to make the above and other objects, features, and advantages of the present invention more comprehensible, the following describes the preferred embodiment in detail with the accompanying drawings, as follows: [Implementation [Mode] The first Binsch diagrams No. 1A to No. 1N are schematic cross-sectional diagrams of manufacturing a capacitor element on a wafer that is not in accordance with the first preferred embodiment of the present invention. Please refer to FIG. 1A, in a wafer fab, a plurality of electronic components 112, such as transistors or metal oxide semiconductors, are formed on the surface layer of the substrate 110, and the material of the substrate 110 is, for example, silicon. Next, a plurality of dielectric layers 122, 124, 126, 128 and a plurality of circuit layers 132, 134, 136 are sequentially formed on the substrate 110 to form a build-up layer 120. The dielectric layer 122 is sequentially stacked on the substrate. The circuit layers are respectively located between adjacent dielectric layers, and the adjacent circuit layers 132, 134, and 136 can be electrically connected through the conductive holes 123 and 125, and the circuit layers 132, 134, and 136 can be connected to each other. The electronic component 112 is electrically connected. In addition, a first electrode 152 of the capacitor element is formed on the dielectric layer 128 of the build-up layer 120, and the first electrode 152 is formed by depositing aluminum or an aluminum alloy using a physical vapor deposition method, or an etching method may also be used. The thickness of the first electrode 10966twf.doc / 008 8 1237847 152 is, for example, between 0. 05 microns and 2 microns. After that, a protective layer 140 is formed on the build-up layer 120. The protective layer 140 will cover the first electrode 152, and the protective layer 140 can prevent water vapor, impurities, mobile ions or transition metal elements from entering the wafer 1 through the protective layer 140. 〇 Within. Next, to define the position of the opening of the protective layer, please refer to FIG. 1B to FIG. 1D, which firstly forms a masking layer 182, such as a photoresist, onto the protective layer 140, and uses a lithography method to cover the photomask. The above pattern is transferred to the masking layer 182, so that the masking layer 182 forms an opening 183 at the position of the first electrode 152, exposing the protective layer 140, as shown in FIG. 1B. Then, the masking layer 182 is used as an etching mask, and the protective layer 140 located under the opening 183 of the masking layer 182 is etched to form a protective layer opening 142 penetrating the protective layer 140, wherein the protective layer opening 142 exposes the first electrode 152 As shown in Figure 1C. After that, the masking layer 182 is removed from the protective layer 140, as shown in FIG. 1D. Referring to FIG. 1E, a capacitor dielectric layer 154 can be formed on the first electrode 152 and the protective layer 140 exposed by the protective layer opening 142, where the thickness d2 of the capacitor dielectric layer 154 is, for example, 0.005 micrometers. To 2 microns. The capacitor dielectric layer 154 can be formed by using the following methods, for example: The first type: The capacitor dielectric layer 154 is deposited by chemical vapor deposition, and tetraethylorthosilicate (TEOS), silicon oxide Compounds, nitrogen silicon compounds, silicon oxynitride compounds, molybdenum pentoxide (Ta205), thorium titanate (SrTi03) or barium titanate (BST); the second type: the capacitor dielectric layer 154 is based on a physical vapor phase Deposition method, 10966twf.doc / 008 9 1237847 Deposited by pentoxide (Ta205), osmium titanate (SrTi03) or barium osmium titanate (BST); the third type: first by chemical vapor deposition After silicon is deposited on the first electrode 152, the deposited silicon is chemically reacted with oxygen by a thermal oxidation method to form an oxygen silicon compound, which is used as the material of the capacitor dielectric layer 154. As described above, the capacitor dielectric layer 154 may be a single-layer structure made of any of the above materials, or the capacitor dielectric layer 154 may also be a composite layer structure made of the above-mentioned partial materials. Next, a part of the capacitor dielectric layer is removed to expose the positions of the contacts of the chip, so that external circuits can be bonded to the contacts of the chip. For example, there are two methods. The first method is to keep only the capacitor dielectric layer formed on the first electrode, and remove the remaining capacitor dielectric layer. The second method is to make the capacitor dielectric layer a whole layer of ground. Remaining on the protective layer, only openings are formed at the contacts of the wafer to expose the contacts of the wafer. In this embodiment, the first method is used for description. Please refer to FIG. 1F to FIG. 1H, which firstly form a masking layer 184, such as a photoresist, on the capacitor dielectric layer 154, and use a lithography method to transfer a pattern on the mask to the masking Layer 184, so that the masking layer 184 is formed with an exposed area 185, and the capacitive dielectric layer 154 is exposed, as shown in FIG. 1F. Then, the masking layer 184 is used as an etching mask, and the capacitive dielectric layer 154 located under the exposed area 185 of the masking layer 184 is etched by wet etching or dry etching. The layer 140 is exposed to the outside, and the capacitor dielectric layer 154 is formed with an opening 155 ′ that bursts out of the first electrode 152 and is defined as the capacitor contact 151, as shown in the figure ig 10966twf.doc / 008 10 1237847. After that, the masking layer 184 is removed from the capacitor dielectric layer 154, as shown in FIG. 1H. Next, "to perform the process of manufacturing the second electrode of the connection line and the capacitor element" please refer to Figures II to 1M. First, for example, by using sputtering, an ~ adhesive layer 172 is formed on the capacitor dielectric layer 154 and protected. On layer 140 and capacitor contact 151, as shown in FIG. II, the adhesive layer 172 is composed of some or all of the following metals, titanium, titanium tungsten alloy, titanium nitrogen compound, chromium copper alloy, and chromium. Single-layer structure or multi-layer structure. Next, a masking layer 186, such as a photoresist, is formed on the adhesive layer 172, and a pattern on the photomask is transferred to the masking layer 186 by lithography, so that the masking layer 186 is formed with an opening 187, 188, the adhesive layer 172 is exposed. The opening 187 defines the pattern of the connection line connected to the first electrode 152, and the opening 188 defines the pattern of the second electrode of the capacitor element, as shown in FIG. 1J. Next, for example, a metal layer 174 is formed on the adhesive layer 172 under the openings 187 and 188 of the masking layer 186 by electroplating. The structure of the metal layer 174 is composed of some or all of the following metals, copper, A single-layer structure or a multi-layer structure composed of nickel and gold, as shown in FIG. 1K. For example, the second electrode is made of, for example, a titanium layer and a copper layer stacked from bottom to top; or titanium Layer, copper layer and nickel layer are stacked from bottom to top; or titanium layer, copper layer, nickel layer and gold layer are stacked from bottom to top; or titanium tungsten alloy layer and gold Layers are stacked from bottom to top. After that, the masking layer 186 is removed from the adhesive layer 172, and the adhesive layer 172 is exposed, as shown in FIG. 1L. Next, the adhesive layer 172 exposed to the outside is removed, so that the connection line 158 and the second electrode of the capacitor element 150 10966twf.doc / 008 11 1237847 156 are completed, as shown in FIG. 1M, and the capacitor element 150 The thickness d3 of the second electrode 156 is, for example, between 1 micrometer and 50 micrometers. The connection line 158 can be electrically connected to the first electrode 152 of the capacitor element 150 through the opening 155 of the capacitor dielectric layer 154. The connection line 158 and the second electrode 156 of the capacitor element 150 are respectively composed of an adhesive layer 172 and a metal in different regions. Layer 174. Finally, referring to FIG. 1N, an insulating layer 190 can be formed on the protective layer 140, where the insulating layer 190 covers the capacitor element 150 and the connection line 158, thereby protecting the capacitor element 150 and the connection line 158. The material of the insulating layer 190 is The system is polyimide, phenylcyclobutene, polyarylene ether, porous dielectric material, or elastomer. In the present invention, since the capacitor element 150 is disposed near the protective layer 140, the substrate 110 of the wafer 100 can be reserved with more space for the electronic component Π2, and a larger one can be provided at the protective layer 140. The capacitor element 150 is formed in a space, so a capacitor element 150 having a larger capacitance can be formed on the wafer 100, and the size of the capacitor element 150 is also easy to modify. In addition, since the capacitor element 150 is disposed away from the substrate 110 of the wafer 100, it is possible to prevent the charges stored in the capacitor element 150 from interfering with the electronic element 112 on the substrate 110 of the wafer 100. In addition, since the capacitor dielectric layer 154 of the capacitor element 150 is completed by the previous semiconductor process, the thickness of the capacitor dielectric layer 154 can be precisely controlled, so that the capacitance of the capacitor element 150 can be accurately controlled. First Embodiment 10966twf.doc / 008 12 1237847 However, the manufacturing process of the capacitor element according to the present invention is not limited to the first embodiment, but may also be as described in the second embodiment. Please refer to FIG. 2A to FIG. 2E. A schematic cross-sectional view of a capacitor element fabricated on a wafer according to a second preferred embodiment of the present invention. FIG. 2A is a process following FIG. 1H. If the reference numerals in this embodiment are the same as those in the first embodiment, it means that the components specified in this embodiment are the same as those specified in the first embodiment. The components will not be repeated here. After defining the shape of the capacitor dielectric layer, an insulating layer 286 can be formed on the protective layer 140. The insulating layer 286 is, for example, a photosensitive material. At this time, a pattern on the photomask can be transferred to The insulating layer 286 is such that the insulating layer 286 is formed with openings 287 and 288. The opening 287 defines the pattern of the connection line and exposes the capacitor contact 151 of the first electrode 152. The opening 288 defines the second electrode of the capacitive element. The capacitor dielectric layer 154 is exposed, as shown in FIG. 2A. Next, an adhesive layer 272 can be formed on the insulating layer 286 by sputtering. The adhesive layer 272 is also formed on the capacitor dielectric layer 154 and the capacitor contact 151 under the openings 287 and 288 of the insulating layer 286. As shown in FIG. 2B ', wherein the adhesive layer 272 is a single-layer structure or a multilayer structure composed of some or all of the following metals, titanium, titanium-tungsten alloy, titanium-nitrogen compound, chromium-copper alloy, and chromium. Next, for example, a metal layer 274 is formed on the adhesive layer 272 by electroplating, and the metal layer 274 is inserted into the openings 287 and 288 of the insulating layer 286. The structure of the metal layer 274 is as follows: All metals, copper, nickel, and gold, have a single-layer structure or a multilayer structure, as shown in Figure 2C. For example, the second electrode is made of, for example, a titanium layer and copper. 10966twf.doc / 008 13 1237847 Stacked from bottom to top; or stacked from bottom to top with titanium, copper, and nickel layers; or stacked from bottom to top with titanium, copper, nickel, and gold It is formed by stacking titanium-tungsten alloy layer and gold layer from bottom to top; or by stacking chromium layer, chromium-copper alloy layer and copper layer from bottom to top. Next, a chemical mechanical polishing (CMP) method can be used to remove the metal layer 274 and the adhesive layer 272 outside the openings 287 and 288 of the insulating layer 286 until the upper surface of the insulating layer 286 is exposed to the outside. Only then stop the chemical mechanical honing operation, as shown in Figure 2D. The connection line 258 can be electrically connected to the first electrode 152 of the capacitor element 250 through the opening 155 of the capacitor dielectric layer 154. The connection line 258 and the second electrode 256 of the capacitor element 250 are composed of an adhesive layer 272 and a metal in different regions, respectively. Consists of layers 274. Finally, referring to FIG. 2E, an insulating layer 290 can be formed on the insulating layer 286. The insulating layer 290 covers the capacitor element 250 and the connection line 258, thereby protecting the capacitor element 250 and the connection line 258. The materials of the insulating layers 286 and 290 are, for example, polyimide, phenylcyclobutene, polyarylene ether, porous dielectric material, or elastomer. Third Binschmo However, the manufacturing process of the capacitor element according to the present invention is not limited to the first embodiment and the second embodiment, and may also be as described in the third embodiment. Please refer to FIG. 3A to FIG. 3E. A schematic cross-sectional view of a capacitor element fabricated on a wafer according to a third preferred embodiment of the present invention. FIG. 3A is a process following FIG. 1H. If the reference numerals in this embodiment are the same as those in the first embodiment 10966twf.doc / 008 14 1237847 In summary, the present invention has at least the following advantages. A wafer structure with a capacitor element and a method for forming a capacitor element on a wafer. Since the capacitor element is arranged near the protective layer, more space can be reserved on the substrate of the wafer to arrange the electronic element. 2. The wafer structure with the capacitor element and the method for forming the capacitor element on the wafer according to the present invention, since the capacitor element is disposed away from the substrate of the wafer, the charges stored by the capacitor element can be prevented from interfering with the substrate on the wafer substrate. Electronic component. 3. The wafer structure with the capacitor element and the method for forming the capacitor element on the wafer of the present invention, because the capacitor element is arranged near the protective layer, and the electronic element is not formed at the protective layer position, so it is at the protective layer. Capacitive elements can be formed with a large space, so a capacitive element with a large capacitance can be formed on the wafer, and the size of the capacitive element is also easy to modify. 4. The wafer structure with a capacitive element and the formation of a capacitive element of the present invention The method on the wafer, because the capacitive dielectric layer of the capacitive element is completed by the previous semiconductor process, the thickness of the capacitive dielectric layer can be precisely controlled, so that the capacitance of the capacitive element can be accurately controlled. Although the present invention has been disclosed as above with preferred embodiments, it is not intended to limit the present invention. Any person skilled in the art can make various modifications and retouches without departing from the spirit and scope of the present invention. Therefore, the present invention The isolation scope shall be determined by the scope of the attached patent application. 10966twf.doc / 008 16 1237847 [Brief description of the drawings] Figures 1A to 1N are schematic cross-sectional views of a capacitor element fabricated on a wafer according to the first preferred embodiment of the present invention. Figures 2A to 2E are schematic cross-sectional views of a capacitor element fabricated on a wafer according to a second preferred embodiment of the present invention. 3A to 3E are schematic cross-sectional views of a capacitor element fabricated on a wafer according to a third preferred embodiment of the present invention. [Schematic description] 100: wafer 110: substrate 112: electronic component 120: build-up layer 122: dielectric layer 123: conductive hole 124: dielectric layer 125: conductive hole 126: dielectric layer 128: dielectric layer 132: wiring Layer 134: circuit layer 136: circuit layer 140: protective layer 142: protective layer opening 150: capacitor element 151: capacitor contact 152: first electrode 154: capacitor dielectric layer 155: opening 156: second electrode 158: connection line 172: Adhesive layer 174: Metal layer 182: Masking layer 183 · Opening 184: Masking layer 185: Exposed area 10966twf.doc / 008 17