1236795 九、發明說明： 【發明所屬之技術領域】 本案係關於一種解調器，尤其是關於一種用於植入式生 物神經微電刺激系統之無電容ASK解調器。 【先前技術】 在習知的幅度鍵控（Amplitude Shift Keying，ASK)解調變 技術上’大致分為非同步（Non-coherent)檢波及同步 (Coherent)檢波兩種方式。典型的非同步檢波器架構，是由 整*态（Rectifier)、低通遽波器（L〇w-pass Filter)和電壓比較 器（Voltage Comparator)所組成。ASK調變訊號經過整流器 整流後可獲得正半週訊號，再經過低通濾波器後將可獲得 正半週成號的包絡線，接著用電壓比較器去判別訊號的準 位，可重現基頻訊號。 典型的同步檢波器架構是由平方定律器（Square_law Circuit)、低通濾波器和電壓比較器所組成。平方定律器需 要搭配額外的振盪器（0sciUat〇r)和鎖相迴路（phase L〇ck Loop)等電路來達成其功能。ASK調變訊號輸入平方定律器 打，先由振盪器所產生的振盪頻率與ASK調變訊號的載波 頻率耦合，再經過鎖相迴路後使前述兩頻率弦波達到同頻 率和同相位，從而解調出ASK調變訊號的包絡線。低通濾 波器可以濾除前述包絡線訊號的高頻部分，使之經過電壓 比較器後’解調變訊號的波形更形理想。 比較同步和非同步檢波的兩種ASK解調器架構，可以發 現它們各有優缺點。整流解調器為非同步檢波電路，其優 96280.doc 1236795 點是電路簡單，但是波形較容易受到雜訊mip卜 在因素干擾；相對地平方定律解調器為同步檢波電路，載 波訊號與振幅調變訊制同步，也就是必彡！同頻率及同相 位’雖，然效果較好但是其電路亦比較複雜。而且這兩種傳 統檢波方式皆有—個共有的缺點，就是必須使用低通遽波 器過滤載波頻率來獲得包絡線訊號，以致需要加入大尺寸 的電容（如美國專利US55326w、US6255901、us63〇7428)， 這對積體電路成本來說是一個重大缺點，尤其是對於植入 式生醫晶片（如美國專利US6402689、US656i97〇)更為不利。 口此貫有必要&供一種創新且富進步性之解調器，以 解決上述問題。 【發明内容】 本發明目的在於提供一種解調器，其包含：一包絡線偵 測為及一電壓比較器。該包絡線偵測器具有複數個電晶 體，用以接收ASK調變訊號，並將該ASK調變訊號之高準 位及低準位分別鎖定在不同的電壓範圍，以產生與該ask 調變訊號相對應之一第一準位包絡線及一第二準位包絡 線。該電壓比較器具有一史密特觸發器及一輸出反相器。 該史密特觸發器用以判別該第一準位包絡線及該第二準位 包絡線，以產生一反相之ASK解調變訊號。該輸出反相器 用以將該反相之ASK解調變訊號還原成一 ASK解調變訊 號。 本發明之解調器係以電晶體組成，完全不需使用電容 器，可減少晶片佈局面積，以縮小晶片之整體面積。因此， 96280.doc 1236795 本發明之解調器可應用於系統單晶片或植入式生物晶片 中〇 【實施方式】 圖1為本發明之解調器10之架構示意圖及訊號處理流程 圖。本發明之解調器10包含：一包絡線偵測器2〇及一電壓 比較器40。該包絡線偵測器20接收一 ASK調變訊號 (45X一S/G)。當該包絡線偵測器20輸入的ASK調變訊號 (dSK—S/G)為低準位時，該包絡線偵測器20之輸出訊號 (£7νΤ—57(7)的振幅範圍為vL2i〜VL22，為一第一準位包絡線。 反之’當該包絡線偵測器20輸入之ASK調變訊號（」狀_57(7) 為向準位時，則該包絡線偵測器2〇輸出訊號的振 幅範圍為Vh^-Vh22，為一第二準位包絡線。該第一準位包 絡線與為該第二準位包絡線之關係是 VL21<VH2J<VL22<VH22。 當該電壓比較器40接收到從該包絡線偵測器2〇的輸出訊 號57G)時，若五A^F-S/G<VH2di]判別為低準位（L〇w)， 此時電壓比較器40之輸出訊號。反之，若 五A^F—S/C^Vl22則判別為高準位（High)，此時電壓比較器4〇 輸出訊號/57G=VDD。 參考圖2所示，本發明之解調器1 〇包含：一包絡線偵測器 20及一電壓比較器4〇。該包絡線偵測器2〇具有複數個電晶 體，用以接收該ASK調變訊號，並將該ASK調變訊號之高 準位及低準位分別鎖定在不同的電壓範圍，以產生與該 ASK調變訊號相對應之一第一準位包絡線及一第二準位包 96280.doc 1236795 絡線。 包絡線偵測器20包含複數個電晶體及電阻，其中PM203 是包絡線偵測器20的起始裝置，當電路電源導電時使包絡 線偵測20能夠馬上進入工作區。 該包絡線偵測器20包含三P型金氧半場效電晶體 PM2(H、PM202、PM203、二N型金氧半場效電晶體NM201、 NM202及一電阻Rs。其中，一第一 P型金氧半場效電晶體 PM203作為該包絡線偵測器21之起始裝置（Start_up)，用以 於一電源供應器開啟而所有電晶體電流為零時，該第一 P 型金氧半場效電晶體PM203即提供包絡線偵測20—個通電 路徑，啟動該包絡線偵測器20並使其正常工作。 一第二P型金氧半場效電晶體PM202及一第一N型金氧半 場效電晶體NM201，兩者各其源極與閘極相連接而分別構 成二個等效二極體（參考圖3之D301及D302)。一第三P型金 氧半場效電晶體PM201、一第二N型金氧半場效電晶體 NM202及該電阻Rs分別耦合至二個等效二極體，係與該電 壓比較器40之一等效輸入電容，形成一等效充放電電路， 用以依據該輸入之ASK調變訊號之電壓準位之不同作充電 或放電，並產生相對應之該第一準位包絡線及該第二準位 包絡線。 圖3為圖2之該包絡線偵測器20的等效電路圖，係由電晶 體PM301、NM301和二極體D301、D302與電阻Rs及電容負 載Q所組成。其中，圖3之電晶體PM301、NM301係等於圖2 之電晶體PM2(H、NM2(H。圖3之二極體D301和D302分別是 96280.doc 12367951236795 IX. Description of the invention: [Technical field to which the invention belongs] This case relates to a demodulator, and in particular to a capacitorless ASK demodulator for an implanted biological nerve microelectric stimulation system. [Prior technology] In the conventional Amplitude Shift Keying (ASK) demodulation technology, it is roughly divided into two methods: non-coherent detection and coherent detection. A typical asynchronous detector architecture consists of a Rectifier, a Low Pass Filter, and a Voltage Comparator. The ASK modulation signal is rectified by a rectifier to obtain a positive half-cycle signal. After passing through a low-pass filter, a positive half-cycle envelope is obtained. Then a voltage comparator is used to determine the signal level, which can reproduce the base. Frequency signal. A typical synchronous detector architecture is composed of a square-law circuit (Square_law Circuit), a low-pass filter, and a voltage comparator. The square law needs to be matched with additional oscillator (0sciUat〇r) and phase locked loop (phase lock loop) circuits to achieve its function. The ASK modulation signal is input to the square law. The oscillation frequency generated by the oscillator is coupled with the carrier frequency of the ASK modulation signal, and then the two frequency sine waves reach the same frequency and the same phase after the phase-locked loop. Recall the envelope of the ASK modulation signal. The low-pass filter can filter out the high-frequency part of the envelope signal, so that the waveform of the demodulated signal after passing through the voltage comparator is more ideal. Comparing the two ASK demodulator architectures for synchronous and asynchronous detection, we can see that each has its own advantages and disadvantages. The rectifier and demodulator is a non-synchronous detection circuit. Its advantages are 96280.doc 1236795. The circuit is simple, but the waveform is more likely to be interfered by noise mip factors. The law of relative squares is a synchronous detection circuit. The carrier signal and amplitude are Modulation system synchronization is also necessary! Although the same frequency and the same phase ', although the effect is better, the circuit is also more complicated. Moreover, both of these two traditional detection methods have a common disadvantage, that is, the carrier frequency must be filtered by using a low-pass chirp to obtain the envelope signal, so that large-size capacitors (such as US patents US55326w, US6255901, us63〇7428) need to be added. ), Which is a major disadvantage for the cost of integrated circuits, especially for implantable biomedical chips (such as US patents US6402689, US656i97〇). It is always necessary to & provide an innovative and progressive demodulator to solve the above problems. SUMMARY OF THE INVENTION An object of the present invention is to provide a demodulator, which includes: an envelope detection device and a voltage comparator. The envelope detector has a plurality of transistors for receiving the ASK modulation signal, and locking the high level and the low level of the ASK modulation signal to different voltage ranges to generate the modulation with the ask. The signal corresponds to a first level envelope and a second level envelope. The voltage comparator has a Schmitt trigger and an output inverter. The Schmitt trigger is used to discriminate the first level envelope and the second level envelope to generate an inverted ASK demodulation signal. The output inverter is used to restore the inverted ASK demodulated signal into an ASK demodulated signal. The demodulator of the present invention is composed of a transistor, and no capacitor is needed at all, which can reduce the layout area of the chip and reduce the overall area of the chip. Therefore, the demodulator of the present invention 96280.doc 1236795 can be applied to a system single chip or an implanted biochip. [Embodiment] FIG. 1 is a schematic diagram of a demodulator 10 and a signal processing flowchart of the present invention. The demodulator 10 of the present invention includes: an envelope detector 20 and a voltage comparator 40. The envelope detector 20 receives an ASK modulation signal (45X-S / G). When the ASK modulation signal (dSK-S / G) input by the envelope detector 20 is at a low level, the amplitude of the output signal (£ 7νΤ-57 (7) of the envelope detector 20 is vL2i ~ VL22 is a first level envelope. Conversely, when the ASK modulation signal ("_57 (7)" input by the envelope detector 20 is a level, the envelope detector 2 〇The amplitude range of the output signal is Vh ^ -Vh22, which is a second level envelope. The relationship between the first level envelope and the second level envelope is VL21 < VH2J < VL22 < VH22. When the When the voltage comparator 40 receives an output signal 57G from the envelope detector 20, if five A ^ FS / G < VH2di] is judged to be a low level (L0w), then the voltage comparator 40 Output signal. On the other hand, if five A ^ F-S / C ^ Vl22 is judged to be a high level (High), then the voltage comparator 40 outputs the signal / 57G = VDD. Referring to FIG. 2, the solution of the present invention The modulator 10 includes an envelope detector 20 and a voltage comparator 40. The envelope detector 20 has a plurality of transistors for receiving the ASK modulation signal and modulating the ASK modulation signal. Signal The high level and the low level are locked in different voltage ranges to generate a first level envelope and a second level envelope 96280.doc 1236795 corresponding to the ASK modulation signal. Envelope The detector 20 includes a plurality of transistors and resistors, of which PM203 is the starting device of the envelope detector 20, which enables the envelope detector 20 to enter the working area immediately when the circuit power is conductive. The envelope detector 20 It includes three P-type MOSFETs PM2 (H, PM202, PM203, two N-type MOSFETs NM201, NM202, and a resistor Rs. Among them, a first P-type MOSFET is PM203 The start device (Start_up) of the envelope detector 21 is used to detect the envelope of the first P-type metal-oxide-semiconductor field-effect transistor PM203 when a power supply is turned on and all transistor currents are zero. 20—power-on paths to activate the envelope detector 20 and make it work normally. A second P-type metal-oxide-semiconductor half-effect transistor PM202 and a first N-type metal-oxide-semiconductor half-effect transistor NM201. The source and gate are connected to form two equivalent two Body (refer to D301 and D302 in Figure 3). A third P-type metal-oxide-semiconductor field-effect transistor PM201, a second N-type metal-oxide-semiconductor FET NM202, and the resistor Rs are coupled to two equivalent diodes, respectively. It is equivalent to one of the voltage comparators 40's input capacitance to form an equivalent charge / discharge circuit, which is used to charge or discharge according to the voltage level of the input ASK modulation signal, and generate the corresponding The first level envelope and the second level envelope. Fig. 3 is an equivalent circuit diagram of the envelope detector 20 of Fig. 2, which is composed of PM301, NM301 and diodes D301, D302, resistor Rs, and capacitive load Q. Among them, the transistors PM301 and NM301 in FIG. 3 are equal to the transistors PM2 (H, NM2 (H in FIG. 2). The diodes D301 and D302 in FIG. 3 are 96280.doc 1236795, respectively.
圖2中電晶體NM201和PM202的等效二極體，電容負載c是 圖2中電壓比較器40的等效輸入電容。以下根據輸入的ASK 调變訊號之高準位和低準位兩種情況，描述圖3的 動態操作原理： 情況一 ：ASK調變訊號為低準位，即ASK—SIG之振幅電壓 範圍為VL11〜VL12(參見圖1) 1. 假設該包絡線偵測器20首次接通電源，電容負載^沒有 電荷存在。當S/G的振幅電壓從vL11往VLi2增加時，若 ask^sig^env^sig<yx^0^ vD301<wth^x, (Vthp301^ vthn301 为別疋電晶體PM301和NM30 1的門權電壓），則二極體D3〇 i 和D302截止，電晶體NM301操作在載止區，電晶體pM3〇i 隨增加由截止區進入線性區，電容負載Ci因沒有電 荷無任何充放電，輸出為Vss。 2. 當Μ火一 S/G的振幅電壓繼續從vL11往VL12增加，若 乂狀一$/<?-·Κ_^/(7>ναρ3〇^Κ·;>ναη3()1，則二極體D301 和D302導通’電晶體ΡΜ301操作在飽和區，電晶體ΝΜ301 隨57G增加先由截止區進入線性區，再由後線性區進 入飽和區，電容負載Ci在此期間不斷充電，輸出 振幅電壓從Vs S往Vl22增加。 3·此時包絡線偵測器已經接通電源良久，電容負載Ci有電 荷存在。當的振幅電壓從vL1d±VL11降低時，若 57G—£WF—iS7G>Vthp3〇1a F^^^Vthi^oi ’ 則二極體D301 和D302導通，電晶體PM301操作在飽和區，電晶體NM301 隨降低由飽和區進入線性區，電容負載Ci在此期間 96280.doc 1236795 仍然充電，輸出振幅電壓從Vss往VL22增加，直至 最大值VL22。 4. 當的振幅電壓繼續從VL1jiVL11降低時，若 57G—五A^—67G<Vthp301 且 ，則二極體 D301 和D302截止，電晶體PM301先由飽和區進入線性區，再由 線性區進入截止區，電晶體NM301操作在截止區，電容負 載Ci在此期間放電，輸出訊號振幅電壓從VL22往 Vl21降低。 5. 當的振幅電壓從VL11往VL12增加時，若 5/6<¥邮3()1且6 如 <Vthn3〇i，則二極體 D301 和D302截止，電晶體NM301操作在載止區，電晶體PM301 .、 隨增加由截止區進入線性區，電容負載Ci在此期間 仍然放電，輸出訊號五振幅電壓從vl22往Vui降低， 直至最小值Vl2 1。 6. 當dlj/G的振幅電壓繼續從Vlii往vli2增加，若 MAT—S/G-五評—*S/G>Vthp3〇4b3(H>vthn3〇i，則二極體 D301 和D302導通，電晶體PM301操作在飽和區’電晶體1^1^301 隨尤__S/G增加先由截止區進入線性區，再由後線性區進 入飽和區，電容負載Ci在此期間不斷充電，輸出 振幅電壓從Vl2 1往Vl22增加。The equivalent diodes of the transistors NM201 and PM202 in FIG. 2, and the capacitive load c is the equivalent input capacitance of the voltage comparator 40 in FIG. 2. The following describes the dynamic operation principle of Figure 3 according to the input of the high level and low level of the ASK modulation signal: Case 1: The ASK modulation signal is at the low level, that is, the amplitude voltage range of ASK-SIG is VL11 ~ VL12 (see Figure 1) 1. Assume that the envelope detector 20 is powered on for the first time, and there is no charge in the capacitive load ^. When the amplitude voltage of S / G increases from vL11 to VLi2, if ask ^ sig ^ env ^ sig < yx ^ 0 ^ vD301 < wth ^ x, (Vthp301 ^ vthn301 is the gate voltage of the PM301 and NM30 1 transistors ), The diodes D30i and D302 are turned off, the transistor NM301 operates in the stop region, and the transistor pM3〇i enters the linear region from the cutoff region with increasing. The capacitive load Ci has no charge and no charge and discharge, and the output is Vss . 2. When the amplitude and voltage of M Huoyi S / G continues to increase from vL11 to VL12, if it is like $ / <?-· Κ _ ^ / (7 > ναρ3〇 ^ κ · > ναη3 () 1, then The diodes D301 and D302 are turned on. The transistor PM301 operates in the saturation region. With the increase of 57G, the transistor NM301 first enters the linear region from the cut-off region and then enters the saturation region from the post-linear region. The capacitive load Ci is continuously charged during this period, and the output amplitude The voltage increases from Vs S to Vl22. 3. At this time, the envelope detector has been powered on for a long time, and the capacitive load Ci has a charge. When the amplitude voltage decreases from vL1d ± VL11, if 57G— £ WF—iS7G > Vthp3 〇1a F ^^^ Vthi ^ oi ', the diodes D301 and D302 are turned on, the transistor PM301 operates in the saturation region, and the transistor NM301 decreases from the saturation region into the linear region as the capacitor loads Ci during this period 96280.doc 1236795 remains When charging, the output amplitude voltage increases from Vss to VL22 to the maximum value VL22. 4. When the amplitude voltage continues to decrease from VL1jiVL11, if 57G—Five A ^ —67G <Vthp301 and the diodes D301 and D302 are turned off, the electricity Crystal PM301 first enters the linear region from the saturation region and then from the linear region In the cut-off area, the transistor NM301 operates in the cut-off area, and the capacitive load Ci discharges during this period, and the output signal amplitude voltage decreases from VL22 to Vl21. 5. When the amplitude voltage increases from VL11 to VL12, if 5/6 < ¥ post 3 () 1 and 6 If < Vthn3〇i, the diodes D301 and D302 are cut off, the transistor NM301 operates in the stop region, and the transistor PM301. The increase from the cutoff region into the linear region, the capacitive load Ci is here During the period of discharge, the output signal five-amplitude voltage decreases from vl22 to Vui until the minimum value Vl2 1. 6. When the dlj / G amplitude voltage continues to increase from Vlii to vli2, if MAT-S / G- 五 Comment- * S / G > Vthp3〇4b3 (H > vthn3〇i, then the diodes D301 and D302 are turned on, and the transistor PM301 operates in the saturation region 'transistor 1 ^ 1 ^ 301 with the increase of __S / G first from the cut-off region to the linear region Then, from the back linear region to the saturation region, the capacitive load Ci is continuously charged during this period, and the output amplitude voltage increases from Vl2 1 to Vl22.
7·自情況一之ό進入情況一之3，週而復始，直至ASK_SIG 從低準位變成高準位。 情況二：ASK調變訊號為高準位，即之振幅電壓 範圍為VH11〜H12(參見圖1) 96280-doc -10 * 1236795 1 ·假設包絡線偵測器首次接通電源，電容負載Ci沒有電荷 存在。當MKJ/G的振幅電壓從乂幻1往Vh12增加時’若 Mr—S/G-五肝一 5/σ<νί}ιρ3()1 且 训 <Vthn3〇i，則二極體 D301 和D302截止，電晶體NM301操作在載止區，電晶體PM301 隨增加由截止區進入線性區，電容負載Ci因沒有電 荷無任何充放電，輸出^VG_*S/G為Vss。 2. 當的振幅電壓繼續從VHii往VHi2增加’若 一S/G-五肝_57G>Vthp301i6術〉Vthn3〇l，則二極體 D301 和D302導通，電晶體PM301操作在飽和區’電晶體1^301 隨增加先由截止區進入線性區，再由後線性區進 入飽和區，電容負載Ci在此期間不斷充電，輸出五#F-S/G 振幅電壓從V s s往V Η 2 2增加。 3. 此時包絡線偵測器已經接通電源良久’電容負載Ci有電 荷存在。當」的振幅電壓從VH12往νΗΠ降低時’若 滞F-57G>Vthp3()4K㈣7>Vthn3〇i，則二極體D301 和D302導通，電晶體PM301操作在飽和區，電晶體1^1^301 隨降低由飽和區進入線性區，電容負載ci在此期間 仍然充電，輸出五A^_*S7G振幅電壓從Vss往VH22增加’直至 最大值Vh22。 4. 當的振幅電壓繼續從Vhi2往VH11降低時，若 ，則二極體 D301 和D302截止，電晶體PM301先由飽和區進入線性區，再由 線性區進入截止區，電晶體NM301操作在截止區，電容負 載Ci在此期間放電，輸出訊號五振幅電壓從VH22往 96280.doc 1236795 V Η 2 1降低。 5_當57G的振幅電壓從VHl分υ , 一 Hl1住VH12增加時，若7 · Since case one has entered case one three, it has been repeated until ASK_SIG has changed from a low level to a high level. Case 2: ASK modulation signal is high level, that is, the amplitude voltage range is VH11 ~ H12 (see Figure 1) 96280-doc -10 * 1236795 1 · Assuming the envelope detector is powered on for the first time, the capacitive load Ci is not The charge exists. When the amplitude and voltage of MKJ / G increases from V1 to Vh12, 'If Mr-S / G-Five liver-1 5 / σ < νί} ιρ3 () 1 and training < Vthn3〇i, then the diodes D301 and When D302 is turned off, the transistor NM301 operates in the stop region. As the transistor PM301 increases, it enters the linear region from the cutoff region. The capacitive load Ci has no charge and no charge and discharge, and the output ^ VG_ * S / G is Vss. 2. When the amplitude voltage continues to increase from VHii to VHi2, 'If one S / G-Five liver_57G> Vthp301i6 operation> Vthn301, the diodes D301 and D302 are turned on, and the transistor PM301 operates in the saturation region. 1 ^ 301 With the increase from the cut-off region to the linear region, and then from the linear region to the saturation region, the capacitive load Ci is continuously charged during this period, and the output five # FS / G amplitude voltage increases from V ss to V Η 2 2. 3. At this time, the envelope detector has been powered on for a long time. The capacitive load Ci has a charge. When the "amplitude voltage" decreases from VH12 to νΗΠ ', if hysteresis F-57G > Vthp3 () 4K & 7 > Vthn30i, diodes D301 and D302 are turned on, transistor PM301 operates in the saturation region, and transistor 1 ^ 1 ^ 301 decreases from the saturation region to the linear region, and the capacitive load ci is still charged during this period, and the output five A ^ _ * S7G amplitude voltage increases from Vss to VH22 'until it reaches the maximum value Vh22. 4. When the amplitude voltage continues to decrease from Vhi2 to VH11, if the diodes D301 and D302 are turned off, the transistor PM301 first enters the linear region from the saturation region, and then enters the cutoff region from the linear region. The transistor NM301 operates at the cutoff. In this period, the capacitive load Ci discharges during this period, and the output signal five-amplitude voltage decreases from VH22 to 96280.doc 1236795 V Η 2 1. 5_ When the amplitude voltage of 57G is divided from VHl, and Hl1 and VH12 increase, if
ASK SIG-ENV 一 一 thp301 Vthn3()1，則二極體 D301 和D302截止’電晶體NM3〇1操作在栽止區，電晶體_〇1 隨撒，G增加由截止區進入線性區，電容負載。在此期間 仍然放電，輸出訊號五A^_WG振幅電屋從Vh22往Vh2i降低， 直至最小值VH21。 6·當S/G的振幅電壓繼續從v 斗、，以丄 ^ V Η 1 1在V η 1 2增加，右 …Vthn3〇i，則二極體D3〇1 和D302導通’電晶體PM3〇1操作在飽和區，電晶體NM301 隨JSi：一以G增加先由截止區進入線性區，再由後線性區進 入飽和區’電容負載Ci在此期間不斷充電，輸出五 振幅電壓從V Η 2 1往V Η 2 2增加。ASK SIG-ENV one thp301 Vthn3 () 1, then diodes D301 and D302 are cut off. Transistor NM3〇1 operates in the stop region. Transistor _〇1 increases with the increase from the cutoff region to the linear region. The capacitance load. During this period, it still discharges, and the output signal five A ^ _WG amplitude electric house decreases from Vh22 to Vh2i to the minimum value VH21. 6. · When the amplitude voltage of S / G continues to increase from V 、, 1 ^ V Η 1 1 increases at V η 1 2 and right ... Vthn3〇i, then diodes D3〇1 and D302 turn on 'transistor PM3. 1Operation in the saturation region, the transistor NM301 follows JSi: one increases by G, first enters the linear region from the cut-off region, and then enters the saturation region from the post-linear region. The capacitive load Ci continuously charges during this period, and outputs a five-amplitude voltage from V Η 2 1 increases to V Η 2 2.
7·自情況二之6進入情況二之3，週而復始，直至ASK 一 SIG 從高準位變成低準位。 圖4為電壓比較器40之電路及其輪入輸出轉態示意圖。該 電壓比較器40具有一史密特觸發器41及一輸出反相器42。 該史密特觸發器41用以接收該包絡線偵測器20輸出之輸出 訊號五7VT_*S/G，判別該第一準位包絡線（VL2i〜Vl22)及該第二 準位包絡線（Vh21〜Vh22) ’以產生一反相之ASK解調變訊 號。該輸出反相器42用以將該反相之ASK解調變訊號還原 成一 ASK解調變訊號（D五MOD_S/G)。 該史密特觸發器41包含複數個電晶體PM401、PM402、 PM403、NM401、NM402、NM403，其將自包絡偵測器 20 96280.doc 12 1236795 輸出的訊號£WF_*S7G判別成高準位或低準位的反相ASK解 調變訊號。該輸出反相器42包含二電晶體PM404及 NM404，將由該史密特觸發器41輸出之該反相ASK解調變 訊號還原成同相的ASK解調變訊號乃五。 該史密特觸發器41具有一第一輸入電位（VSPH)及一第二 輸入電位（VSPL)，該第一輸入電位與該第二輸入電位之電位 差為一遲滯電壓，該遲滯電壓必須涵蓋該第一準位包絡線 及該第二準位包絡線重叠的電壓範圍，以產生該反相的 ASK解調變訊號。 以下根據由該包絡線偵測器20輸入的包絡線訊號 五之大小共八種情況，描述圖4的動態操作原理： 情況一 .Vthn402 >^\^_5/(7〇~4()2是電晶體NM402的門檻 電壓） 此時電晶體PM401、PM402與NM403操作在飽和區，電晶 體PM403、NM401與NM402操作在截止區；圖4中節點電壓 Vx = VdD-Vthn403(Vthn403是電晶體NM403的門植電壓）和 VZ=VDD; Vz經過輸出反相器42後’得到輸出乃五 十月況 *— · Vthn402<^*Y厂—Vthn40 1 + Vx(Vthn40 1 和 Vthn402 分 別是電晶體NM401和NM402的門檻電壓） 此時電晶體PM4(M、PM402、NM402與NM403操作在飽和 區，電晶體PM403與NM401操作在截止區；圖4中節點電壓7. From case two to six, case two to three, iterate and repeat, until ASK one SIG changes from high to low. FIG. 4 is a schematic diagram of the circuit of the voltage comparator 40 and its turn-in and output transitions. The voltage comparator 40 includes a Schmitt trigger 41 and an output inverter 42. The Schmitt trigger 41 is used to receive an output signal 5 7VT_ * S / G output from the envelope detector 20, and discriminate the first level envelope (VL2i ~ Vl22) and the second level envelope ( Vh21 ~ Vh22) 'to generate an inverted ASK demodulation signal. The output inverter 42 is used to restore the inverted ASK demodulated signal into an ASK demodulated signal (D_MOD_S / G). The Schmitt trigger 41 includes a plurality of transistors PM401, PM402, PM403, NM401, NM402, NM403, which judges the signal output from the envelope detector 20 96280.doc 12 1236795 to a high level or Low level inverted ASK demodulation signal. The output inverter 42 includes two transistors PM404 and NM404. The inverting ASK demodulation signal output from the Schmitt trigger 41 is restored to an in-phase ASK demodulation signal. The Schmitt trigger 41 has a first input potential (VSPH) and a second input potential (VSPL). The potential difference between the first input potential and the second input potential is a hysteresis voltage, and the hysteresis voltage must cover the A voltage range where the first level envelope and the second level envelope overlap to generate the inverted ASK demodulation signal. The following describes the dynamic operation principle of FIG. 4 according to a total of eight cases of the envelope signal five input by the envelope detector 20: Case 1. Vthn402 > ^ \ ^ _ 5 / (7〇 ~ 4 () 2 Is the threshold voltage of the transistor NM402) At this time, the transistors PM401, PM402 and NM403 are operating in the saturation region, and the transistors PM403, NM401 and NM402 are operating in the cutoff region; the node voltage Vx = VdD-Vthn403 in Figure 4 (Vthn403 is the transistor NM403 Gate voltage) and VZ = VDD; Vz's output is 50 months after the output inverter 42 * — · Vthn402 < ^ * Y factory—Vthn40 1 + Vx (Vthn40 1 and Vthn402 are transistor NM401 respectively And NM402 threshold voltage) At this time, the transistor PM4 (M, PM402, NM402 and NM403 operate in the saturation region, and the transistor PM403 and NM401 operate in the cutoff region; the node voltage in Figure 4
Vx<V〇d —Vth403(Vthn403是電晶體NM403的門植電壓）和 Vz=vdd; Vz經過輸出反相器42後’得到輸出 情況三：幻VK」S7G=Vthn401+Vx=VSPH(Vthn401 是電晶體 96280.doc -13- 1236795 NM401的門檻電壓） 此時電晶體PM401、PM402與NM402操作在飽和區，電晶 體PM403與NM401由截止區進入飽和區，電晶體NM402由 飽和區進入截止區；圖4中節點電壓vx«>〇和Vz=VDD + 〇; 乂2經過輸出反相器42後，得到輸出+ 。 情況四：£A/T_^/G>Vthn401+vx=VSPH(Vthn401 是電晶體 NM401的門檻電壓） 此時電晶體 PM401、PM402、PM403、NM401 與 NM403 操作在飽和區，電晶體NM402操作在截止區；圖4中節點電 壓Vx=0和Vz=0 ; Vz經過輸出反相器42後，得到輸出 DEMOD一SIG=VOO 〇 情況五：五A^J/G〉VDD-vthp401(vthp401是電晶體PM401的 門檻電壓） 此時電晶體PM403、NM401與NM402操作在飽和區，電 晶體PM401、PM402與NM403操作在截止區；圖4中節點電 壓Vy=Vthp4〇3(VthP4〇3是電晶體PM403的門楹電塵）和Vz=0 ; 丫2經過輸出反相器42後，得到輸出DEMO/)—67(?=VDD。 情況六·· VDD-Vthf^oi’Z/VT—S/G^Vthj^M+V/VthMiH* Vthp4〇2分別是電晶體PM401和PM402的門檻電壓） 此時電晶體PM4(H、PM403、NM401與NM402操作在飽和 區’電晶體PM402與NM403操作在截止區；圖4中節點電壓 vy〉vthp403(vthp4()3是電晶體PM403 的門檻電壓）和 vz=0 ; Vz 經過輸出反相器42後，得到輸出D五MOD S/G=V 。Vx < V〇d-Vth403 (Vthn403 is the gate voltage of transistor NM403) and Vz = vdd; Vz 'gets the output situation after output inverter 42: Magic VK "S7G = Vthn401 + Vx = VSPH (Vthn401 is Transistor 96280.doc -13- 1236795 NM401 threshold voltage) At this time, transistors PM401, PM402 and NM402 are operating in the saturation region, transistors PM403 and NM401 enter the saturation region from the cutoff region, and the transistor NM402 enters the cutoff region from the saturation region; In FIG. 4, the node voltages vx «> 〇 and Vz = VDD + 〇; 乂 2 After the output inverter 42 is passed, an output + is obtained. Case 4: £ A / T _ ^ / G > Vthn401 + vx = VSPH (Vthn401 is the threshold voltage of the transistor NM401) At this time, the transistors PM401, PM402, PM403, NM401 and NM403 operate in the saturation region, and the transistor NM402 operates at the cutoff 4; the node voltages Vx = 0 and Vz = 0 in Figure 4; Vz passes the output inverter 42 to get the output DEMOD_SIG = VOO 〇 Case 5: Five A ^ J / G> VDD-vthp401 (vthp401 is a transistor Threshold voltage of PM401) At this time, the transistors PM403, NM401, and NM402 are operating in the saturation region, and the transistors PM401, PM402, and NM403 are operating in the cut-off region; the node voltage Vy = Vthp4〇3 in Figure 4 (VthP4〇3 is the transistor PM403 Gate dust) and Vz = 0; ya 2 gets the output DEMO /) — 67 (? = VDD after passing through the output inverter 42. Case 6 · VDD-Vthf ^ oi'Z / VT-S / G ^ Vthj ^ M + V / VthMiH * Vthp4〇2 are the threshold voltages of the transistors PM401 and PM402, respectively. At this time, the transistor PM4 (H, PM403, NM401 and NM402 operate in the saturation region; the transistors PM402 and NM403 operate in the cutoff region; The node voltage vy> vthp403 (vthp4 () 3 is the threshold voltage of the transistor PM403) and vz = 0 in FIG. 4; After the output inverter 42 is passed through Vz, the output D is MOD. S / G = V.
— DD 情況七：幻VTJ/G^Vthp^+VfVspLXVthMM 是電晶體 96280.doc -14- 1236795 PM402的門檻電壓） 此時電晶體PM401、NM401與NM402操作在飽和區，電 晶體PM402與NM403由截止區進入飽和區，電晶體pM4〇3 由飽和區進入截止區；圖4中節點電壓Vy + VDD和 Vz=0今VDD ; Vz經過輸出反相器402後，得到輸出 DEMOD_SIG=VjyD今 〇。 情況八：£7VT—iS7G>Vthp4〇2+Vy=VSpL(Vthp402 是電晶體 PM402的門檻電壓） 此時電晶體 PM401、PM402、NM401、NM402與 NM403 操作在飽和區，電晶體PM403操作在截止區；圖4中節點電 壓Vy=VDD和VZ=VDD ; Vz經過輸出反相器402後，得到輸 出 i)五MOZ)_57G=0。 圖5顯示本發明之無電容ASK解調器以台灣積體電路公 司之0.35 //m 2P4M CMOS製程佈局後所作的模擬，在載 波頻率為2 MHz、資料傳輸率為1〇 Kbit/s的ASK調變訊號時 之輸入輸出波形。 因此，本發明之解調器係以電晶體組成，完全不需使用 電容器，可減少晶片佈局面積，以縮小晶片之整體面積。 本發明之解調器除了可應用於系統單晶片或植入式生物晶 片中（例如：植入式生物神經微電刺激器的ASK解調變），亦 可應用於無線通訊中ASK調變系統之訊號解調變。 【圖式簡單說明】 圖1係本發明之解調器之訊號處理流程圖； 圖2係本發明之解調器架構示意圖； 96280.doc -15- 1236795 圖3係本發明之包絡線偵測器之等效電路圖； 圖4係本發明之電壓比較器電路及其輸入輸出轉態示意 圖；及 圖5係本發明之解調器模擬之輸入輸出波形示意圖。 【主要元件符號說明】 10 本發明之解調器 20 包絡線偵測器 31 包絡線偵測器等效電路 40 電壓比較器 41 史密特觸發器 42 輸出反相器 Ci 電壓比較器之等效輸入電容 Rs 電阻 ASK—SIG ASK調變訊號 ENV—SIG 包絡線偵測器輸出訊號 DEMOD—SIG 解調器輸出訊號 96280.doc 16-— DD Case 7: The magic VTJ / G ^ Vthp ^ + VfVspLXVthMM is the threshold voltage of the transistor 96280.doc -14- 1236795 PM402) At this time, the transistors PM401, NM401 and NM402 are operating in the saturation region, and the transistors PM402 and NM403 are turned off The transistor pM403 enters the cut-off region from the saturation region; the node voltages Vy + VDD and Vz = 0 and VDD in Figure 4; Vz passes the output inverter 402 to obtain the output DEMOD_SIG = VjyD and 〇. Case 8: £ 7VT—iS7G> Vthp4〇2 + Vy = VSpL (Vthp402 is the threshold voltage of the transistor PM402) At this time, the transistors PM401, PM402, NM401, NM402 and NM403 operate in the saturation region, and the transistor PM403 operates in the cutoff region ; The node voltages Vy = VDD and VZ = VDD in FIG. 4; after passing through the output inverter 402, Vz obtains output i) five MOZ) _57G = 0. FIG. 5 shows the simulation of the capacitorless ASK demodulator of the present invention after the layout of 0.35 // m 2P4M CMOS process of Taiwan Semiconductor Manufacturing Company, with ASK at a carrier frequency of 2 MHz and a data transmission rate of 10 Kbit / s. Input and output waveforms when modulating signals. Therefore, the demodulator of the present invention is composed of a transistor and does not need a capacitor at all, which can reduce the layout area of the chip and reduce the overall area of the chip. The demodulator of the present invention can be applied to a system single chip or an implanted biochip (for example, the ASK demodulation of an implanted biological nerve microelectric stimulator), and it can also be applied to the ASK modulation system in wireless communication. Signal demodulation. [Schematic description] Figure 1 is a signal processing flowchart of the demodulator of the present invention; Figure 2 is a schematic diagram of the demodulator structure of the present invention; 96280.doc -15-1236795 Figure 3 is the envelope detection of the present invention Fig. 4 is a schematic diagram of the voltage comparator circuit of the present invention and its input-output transition state; and Fig. 5 is a schematic diagram of the input-output waveform simulated by the demodulator of the present invention. [Description of Symbols of Main Components] 10 Demodulator of the present invention 20 Envelope detector 31 Envelope detector equivalent circuit 40 Voltage comparator 41 Schmitt trigger 42 Output inverter Ci Voltage comparator equivalent Input capacitor Rs Resistance ASK—SIG ASK modulation signal ENV—SIG Envelope detector output signal DEMOD—SIG Demodulator output signal 96280.doc 16-