CN210380804U

CN210380804U - Signal isolation transmission circuit based on capacitor

Info

Publication number: CN210380804U
Application number: CN201920720487.9U
Authority: CN
Inventors: 朱金桥
Original assignee: Shanghai Guestgood Electronics Co ltd
Current assignee: Shanghai Xianji Integrated Circuit Co ltd
Priority date: 2019-05-20
Filing date: 2019-05-20
Publication date: 2020-04-21
Anticipated expiration: 2029-05-20

Abstract

A signal isolation transmission circuit based on capacitors is characterized in that an isolation capacitor group is respectively connected with a first signal transmission circuit and a second signal transmission circuit, the first signal transmission circuit and the second signal transmission circuit respectively comprise a signal input module and a signal output module, when the first signal transmission circuit works in an input mode, the second signal transmission circuit works in an output mode, when the second signal transmission circuit works in an input mode, the first signal transmission circuit works in an output mode, when the first signal transmission circuit works in the input mode, only the signal input module works, when the first signal transmission circuit works in the output module, only the signal output module works, the signal input module carries out duty ratio modulation on input signals, modulated signals with fixed frequency are output, the isolation capacitor group realizes signal isolation transmission, and the signal output module demodulates the modulated signals. The utility model discloses a special duty ratio modem carries out signal transmission to signal isolation transmission has been realized as signal isolation device with the condenser.

Description

Signal isolation transmission circuit based on capacitor

Technical Field

The utility model relates to an integrated circuit signal processing field especially relates to a transmission circuit is kept apart to signal based on electric capacity.

Background

Signals are often required to be isolated in electronic systems with different voltage domains so as to ensure indexes such as reliability and safety of the systems. The isolation of common digital signals is realized by devices such as a transformer, a photoelectric coupler, a Hall device and the like, but the isolation and conversion of analog signals are very difficult, and the analog signals are generally required to be converted into the digital signals and then transmitted through the digital isolation devices in an isolation way. In consideration of cost, reliability, device size and other factors, the photoelectric coupler is the most popular signal isolation device at present, and realizes electrical isolation between two voltage domains by means of optical transmission. However, the photocoupler has the characteristics of poor temperature characteristic, large power consumption, short aging period, difficulty in semiconductor process integration and the like, so that the photocoupler faces a plurality of application bottlenecks.

SUMMERY OF THE UTILITY MODEL

The utility model provides a transmission circuit is kept apart to signal based on electric capacity carries out signal transmission through special duty cycle modem to signal isolation transmission has been realized as signal isolation device with the condenser.

In order to achieve the above object, the utility model provides a signal isolation transmission circuit based on electric capacity contains: the circuit comprises a first signal transmission circuit, a second signal transmission circuit and an isolation capacitor set, wherein the first signal transmission circuit and the second signal transmission circuit are completely consistent in structure, and the isolation capacitor set is respectively connected with the first signal transmission circuit and the second signal transmission circuit;

the first signal transmission circuit and the second signal transmission circuit respectively comprise a signal input module and a signal output module, the first signal transmission circuit and the second signal transmission circuit can respectively work in an input mode and an output mode, when the first signal transmission circuit and the second signal transmission circuit work in the input mode, only the signal input module works, the signal output module does not work, when the first signal transmission circuit and the second signal transmission circuit work in the output mode, only the signal output module works, and the signal input module does not work;

when the first signal transmission circuit works in an input mode, the second signal transmission circuit works in an output mode, and when the second signal transmission circuit works in the input mode, the first signal transmission circuit works in the output mode;

the signal input module carries out duty ratio modulation on an input signal and outputs a modulation signal with fixed frequency;

the isolation capacitor bank realizes signal isolation transmission;

the signal output module demodulates the modulation signal.

The signal input module is a modulation circuit, the modulation circuit converts the high level of the input signal into the clock period of a first duty ratio, and converts the low level of the input signal into the clock period of a second duty ratio.

The first duty cycle is 75% and the second duty cycle is 25%; or the first duty cycle is 25% and the second duty cycle is 75%.

The modulation circuit comprises:

a signal modulation circuit to the input terminals of which a signal SIG _ INL and a reference clock signal CK0 are input and the output terminal of which outputs a modulation signal SIGX for duty-cycle modulation of the signal;

and the input end of the glitch filtering circuit inputs the modulation signal SIGX, and the output end of the glitch filtering circuit outputs two inverted fixed frequency modulation signals SIG _ ML and SIG _ MLB which are used for filtering the signal glitch.

The signal modulation circuit comprises:

the clock signal CK0 is processed by the frequency-dividing flip-flop to generate a frequency-dividing clock signal CK1, the reference clock signal CK0 AND the frequency-dividing clock signal CK1 are input to an AND gate to output a signal CK _ AND, the reference clock signal CK0 AND the frequency-dividing clock signal CK1 are input to an OR gate output signal CK _ OR, the input signal SIG _ INL is input to an inverter output signal SIG _ INB, AND the signals CK _ AND, CK _ OR, SIG _ INL AND SIG _ INB are commonly input to the 4-input AND gate, wherein the signal CK _ AND is ANDed with the signal SIG _ INB, the signal CK _ OR is ANDed with the signal SIG _ INL, AND the result of the two is OR to obtain a signal SIGX which is a transitional modulation signal.

The glitch filter circuit includes:

the circuit comprises a delay circuit, an exclusive-OR gate, a burr filtering trigger and a three-state buffer, wherein a reference clock signal CK0 passes through the delay circuit and then is input to the exclusive-OR gate together with a reference clock signal CK0, the exclusive-OR gate outputs a trigger signal TRIG, the trigger signal TRIG is connected to a clock signal end of the burr filtering trigger, a modulation signal SIGX is input to a data end of the burr filtering trigger, the falling edge of the trigger signal TRIG samples the state of the modulation signal SIGX, a forward output end of the burr filtering trigger outputs a signal SIG _ ML _ BUF to the three-state buffer, a reverse output end outputs a signal SIG _ MLB _ BUF to the three-state buffer, and a high-impedance output signal SIG _ ML and a high-impedance output signal SIG _ MLB are output through the three-state buffer.

The signal output module comprises a detection circuit and a demodulation circuit, wherein the input end of the detection circuit is connected with the isolation capacitor group, the output end of the detection circuit is connected with the input end of the demodulation circuit, the detection circuit converts a charge signal SIG _ MR coupled by the isolation capacitor group into a voltage signal SIG _ MRD, and the demodulation circuit demodulates the voltage signal SIG _ MRD to obtain a demodulation signal SIG _ OUTR.

The isolation capacitor bank comprises a first isolation capacitor which couples the modulated fixed frequency signal SIG _ ML to become a charge signal SIG _ MR.

The detection circuit comprises:

the positive input stage of the hysteresis comparator is connected with the first isolation capacitor, the charge signal SIG _ MR is input into the positive input stage, and the voltage signal SIG _ MRD is output from the output end of the hysteresis comparator;

one end of the first resistor is connected with the power supply, and the other end of the first resistor is connected with the positive input stage of the hysteresis comparator;

one end of the second resistor is connected with the positive input stage of the hysteresis comparator, and the other end of the second resistor is grounded;

one end of the third resistor is connected with the power supply, and the other end of the third resistor is connected with the negative input stage of the hysteresis comparator;

and one end of the fourth resistor is connected with the negative input stage of the hysteresis comparator, and the other end of the fourth resistor is grounded.

The detection circuit comprises:

one end of the fifth resistor is connected with the bias voltage signal VREFX, and the other end of the fifth resistor is connected with the positive input stage of the hysteresis comparator;

and one end of the sixth resistor is connected with the bias voltage signal VREFX, and the other end of the sixth resistor is connected with the negative input stage of the hysteresis comparator.

The isolation capacitor group comprises a first isolation capacitor and a second isolation capacitor, the first isolation capacitor couples the modulated fixed frequency signal SIG _ ML to form a charge signal SIG _ MR, and the second isolation capacitor couples the modulated fixed frequency signal SIG _ MLB to form a charge signal SIG _ MRB.

The detection circuit comprises:

a hysteresis comparator, the positive input stage of which is connected with the first isolation capacitor, the positive input stage of which is inputted with a charge signal SIG _ MR, the negative input stage of which is connected with the second isolation capacitor, the negative input stage of which is inputted with a charge signal SIG _ MRB, and the output end of which is outputted with a voltage signal SIG _ MRD;

The detection circuit comprises:

The demodulation circuit comprises:

a high level time shift circuit, an input terminal of which inputs the delayed voltage signal SIG _ MRD _ DLY and an output terminal of which outputs a high level time shift voltage signal VH, for converting a high level time amount into a voltage amount VH;

a low level time-to-voltage conversion circuit, the input end of which inputs the delayed voltage signal SIG _ MRD _ DLY and the output end of which outputs a low level time-to-voltage conversion signal VL, the low level time-to-voltage conversion circuit being used for converting a low level time amount into a voltage amount VL;

the demodulation flip-flop circuit has an input terminal to which the high level time shift voltage signal VH and the low level time shift voltage signal VL are input, and an output terminal to which the demodulation signal SIG _ OUTR is output.

The high level time-to-voltage circuit comprises:

the source electrode of the current source transistor is connected with a power supply, the grid electrode of the current source transistor is connected with a bias voltage IBIAS, and the drain electrode of the current source transistor is connected with the source electrode of the switch transistor;

a switch transistor, the source electrode of which is connected with the drain electrode of the current source transistor, the grid electrode of which is connected with the output end of the phase inverter, and the drain electrode of which is connected with the high-level time conversion voltage signal VH;

a drain transistor, the source of which is connected with the high-level time conversion voltage signal VH, the gate of which is connected with the drain signal DISC, and the drain of which is grounded;

one end of the capacitor is connected with the high-level time conversion voltage signal VH, and the other end of the capacitor is grounded;

and an inverter having an input terminal connected to the delayed voltage signal SIG _ MRD _ DLY output from the delay circuit and an output terminal connected to the gate of the switching transistor.

The low level time-to-voltage circuit comprises:

a switch transistor, the source of which is connected with the drain of the current source transistor, the gate of which is connected with the delayed voltage signal SIG _ MRD _ DLY output by the delay circuit, and the drain of which is connected with the low level time conversion voltage signal VL;

a drain transistor, a source electrode of which is connected with the low level time conversion voltage signal VL, a grid electrode of which is connected with the drain signal DISC, and a drain electrode of which is grounded;

and one end of the capacitor is connected with the low-level time conversion voltage signal VL, and the other end of the capacitor is grounded.

The demodulation trigger circuit comprises:

the positive input end of the comparator is connected with a high-level time conversion voltage signal VH output by the high-level time conversion voltage circuit, the negative input end of the comparator is connected with a low-level time conversion voltage signal VL output by the low-level time conversion voltage circuit, and the output end of the comparator outputs a comparison signal DAT to the trigger; when VH > VL, the comparison signal DAT is high, and when VH < VL, the comparison signal DAT is low;

and the data input end D of the flip-flop is connected with the output end of the comparator, the trigger clock end C of the flip-flop is connected with the voltage signal SIG _ MRD, and the output end Q of the flip-flop outputs a demodulation signal SIG _ OUTR.

The utility model discloses a special duty ratio modem carries out signal transmission to signal isolation transmission has been realized as signal isolation device with the condenser. Use the condenser as isolation device, the characteristics of the condenser stability, low-cost, low-power consumption, the integration of being convenient for make the utility model has very good practicality.

Drawings

Fig. 1 is a circuit diagram of a first embodiment of a signal isolation transmission circuit based on a capacitor according to the present invention.

Fig. 2 is a diagram of the signal transmission circuit of fig. 1 when the first signal transmission circuit operates in an input mode and the second signal transmission circuit operates in an output mode.

Fig. 3 is a diagram of the signal transmission circuit of fig. 1 when the first signal transmission circuit operates in an output mode and the second signal transmission circuit operates in an input mode.

Fig. 4 is a circuit diagram of a second embodiment of a signal isolation transmission circuit based on a capacitor according to the present invention.

Fig. 5 is a diagram of the signal transmission circuit of fig. 4 when the first signal transmission circuit operates in an input mode and the second signal transmission circuit operates in an output mode.

Fig. 6 is a diagram of the signal transmission circuit of fig. 4 when the first signal transmission circuit operates in an output mode and the second signal transmission circuit operates in an input mode.

Fig. 7 is an operation waveform diagram of the modulation circuit of the present invention.

Fig. 8 is a typical circuit diagram of the modulation circuit of the present invention.

Fig. 9 is a waveform diagram of the internal operation of a typical circuit of the modulation circuit of the present invention.

Fig. 10 is a circuit diagram of a first embodiment of the detection circuit of the present invention.

Fig. 11 is an operation waveform diagram of the first embodiment of the detection circuit of the present invention.

Fig. 12 is a circuit diagram of a second embodiment of the detection circuit of the present invention.

Fig. 13 is a circuit diagram of a third embodiment of the detection circuit of the present invention.

Fig. 14 is a circuit diagram of a fourth embodiment of the detection circuit of the present invention.

Fig. 15 is an internal typical circuit of the demodulation circuit of the present invention.

Fig. 16 is a demodulation waveform diagram of the demodulation circuit of the present invention.

Fig. 17 is a waveform diagram illustrating an internal operation of a typical circuit of the demodulation circuit according to the present invention.

Detailed Description

The preferred embodiment of the present invention will be described in detail below with reference to fig. 1 to 17.

As shown in fig. 1, the utility model provides a signal isolation transmission circuit based on electric capacity contains: the first signal transmission circuit 101, the second signal transmission circuit 102, and the first isolation capacitor 103 connected to the first signal transmission circuit 101 and the second signal transmission circuit 102, respectively.

The first signal transmission circuit 101 and the second signal transmission circuit 102 respectively include a signal input module and a signal output module, and the first signal transmission circuit 101 and the second signal transmission circuit 102 can respectively work in an input mode and an output mode, that is, the first signal transmission circuit 101 and the second signal transmission circuit 102 are both in a half-duplex working mode, the relationship between the first signal transmission circuit 101 and the second signal transmission circuit 102 is equivalent to the relationship between a master and a slave, the master can send information to the slave, and the slave can also send information to the master, thereby realizing the interaction of information between the master and the slave. When the first signal transmission circuit 101 works in the input mode, the second signal transmission circuit 102 works in the input mode, and the signals are transmitted from the second signal transmission circuit 102 to the first signal transmission circuit 102 in the input mode. By default, the first signal transmission circuit 101 and the second signal transmission circuit 102 are both in the output mode, and no signal is transmitted until the first signal transmission circuit 101 or the second signal transmission circuit 102 enters the input mode, and signal transmission is started.

Specifically, the first signal transmission circuit 101 includes a signal input module and a signal output module;

the signal input module comprises: a first modulation circuit 108, an input terminal of which is connected to the input signal SIG _ INL, an output terminal of which is connected to the first isolation capacitor 103, for converting the input signal SIG _ INL into an output signal SIG _ ML having a fixed frequency, the first modulation circuit 108 converting a high level of the input signal SIG _ INL into a clock period of a first specific duty ratio and converting a low level of the input signal SIG _ INL into a clock period of a second specific duty ratio;

the signal output module comprises:

a first detection circuit 104, an input terminal of which is connected to the first isolation capacitor 103, and an output terminal of which is connected to the first demodulation circuit 107, for converting the charge signal SIG _ ML coupled from the first isolation capacitor 103 into a voltage signal SIG _ MLD;

the first demodulation circuit 107 has an input terminal connected to the first detection circuit 104, and an output terminal outputting a demodulation signal SIG _ OUTL, and is configured to demodulate the voltage signal SIG _ MLD output by the first detection circuit 104 to obtain the demodulation signal SIG _ OUTL.

Similarly, the second signal transmission circuit 102 includes a signal input module and a signal output module;

the signal input module comprises: a second modulation circuit 109 having an input terminal connected to the input signal SIG _ INR and an output terminal connected to the first isolation capacitor 103, for converting the input signal SIG _ INR into an output signal SIG _ MR having a fixed frequency, wherein the second modulation circuit 109 converts a high level of the input signal SIG _ INR into a clock period of a first specific duty ratio and converts a low level of the input signal SIG _ INR into a clock period of a second specific duty ratio;

the signal output module comprises:

a second detection circuit 106, an input terminal of which is connected to the first isolation capacitor 103, and an output terminal of which is connected to the second demodulation circuit 105, for converting the charge signal SIG _ MR coupled from the first isolation capacitor 103 into a voltage signal SIG _ MRD;

the second demodulation circuit 105 has an input terminal connected to the second detection circuit 106, and an output terminal outputting a demodulation signal SIG _ OUTR for demodulating the voltage signal SIG _ MRD output from the second detection circuit 106 to obtain the demodulation signal SIG _ OUTR.

As shown in fig. 2, the unidirectional isolation transmission circuit is a unidirectional isolation transmission circuit from the first signal transmission circuit 101 to the second signal transmission circuit 102, the first signal transmission circuit 101 is in an input mode, only the first modulation circuit 108 operates, the second signal transmission circuit 102 is in an output mode, and only the second detection circuit 106 and the second demodulation circuit 105 operate. The first modulation circuit 108 converts the input signal SIG _ INL into a signal SIG _ ML having a fixed frequency, and converts a high level of the input signal SIG _ INL into a clock period of a first specific duty ratio and converts a low level of the input signal SIG _ INL into a clock period of a second specific duty ratio. The first isolation capacitor 103 is used to implement signal isolation, and couples the modulated fixed frequency signal SIG _ ML to become a charge signal SIG _ MR, which is input to the second signal transmission circuit 102. The second detection circuit 106 converts the charge signal SIG _ MR coupled through the first isolation capacitor 103 into a voltage signal SIG _ MRD, the voltage signal SIG _ MRD is input to the second demodulation circuit 105, and the second demodulation circuit 105 demodulates and restores the voltage signal SIG _ MRD and outputs a demodulated signal SIG _ OUTR.

As shown in fig. 3, the unidirectional isolation transmission circuit is provided from the second signal transmission circuit 102 to the first signal transmission circuit 101, the second signal transmission circuit 102 is in the input mode, only the second modulation circuit 109 operates, the first signal transmission circuit 101 is in the output mode, and only the first detection circuit 104 and the first demodulation circuit 107 operate. The second modulation circuit 109 converts the input signal SIG _ INR into a signal SIG _ MR having a fixed frequency, and converts a high level of the input signal SIG _ INR into a clock period of a first specific duty ratio and converts a low level of the input signal SIG _ INR into a clock period of a second specific duty ratio. The first isolation capacitor 103 is used to implement signal isolation, and couples the modulated fixed frequency signal SIG _ MR into a charge signal SIG _ ML, which is input to the first signal transmission circuit 101. The first detection circuit 104 converts the charge signal SIG _ ML coupled through the first isolation capacitor 103 into a voltage signal SIG _ MLD, the voltage signal SIG _ MLD is input to the first demodulation circuit 107, and the first demodulation circuit 107 demodulates and restores the voltage signal SIG _ MLD to output a demodulated signal SIG _ OUTL.

As can be seen from fig. 2 and 3, the signal isolation transmission from the first signal transmission circuit 101 to the second signal transmission circuit 102 is completely identical to the signal isolation transmission from the second signal transmission circuit 102 to the first signal transmission circuit 101.

The utility model discloses can transmit any kind of pulse signal, be a transmission circuit is kept apart to general half duplex's signal.

As shown in fig. 4, in another embodiment of the present invention, a second isolation capacitor 110 is added on the basis of the embodiment of fig. 1. When the first signal transmission circuit 101 is in the input mode, the first modulation circuit 108 outputs two fixed frequency modulation signals SIG _ ML and SIG _ MLB, where SIG _ ML and SIG _ MLB are a pair of complementary signals, that is, SIG _ MLB is the inverse of SIG _ ML signal, the first isolation capacitor 103 couples the modulated fixed frequency modulation signal SIG _ ML to become the charge signal SIG _ MR, and inputs the charge signal SIG _ MR to the second signal transmission circuit 102, and the second isolation capacitor 110 couples the modulated fixed frequency modulation signal SIG _ MLB to become the charge signal SIG _ MRB, and inputs the charge signal SIG _ MR to the second signal transmission circuit 102. When the second signal transmission circuit 102 is in the input mode, the second modulation circuit 109 outputs two fixed frequency modulation signals SIG _ MR and SIG _ MRB, where SIG _ MR and SIG _ MRB are a pair of complementary signals, that is, SIG _ MRB is the inverse of SIG _ MR signal, the first isolation capacitor 103 couples the modulated fixed frequency modulation signal SIG _ MR into the charge signal SIG _ ML, and inputs the charge signal SIG _ ML to the first signal transmission circuit 101, and the second isolation capacitor 110 couples the modulated fixed frequency modulation signal SIG _ MRB into the charge signal SIG _ MLB, and inputs the charge signal SIG _ MLB to the first signal transmission circuit 101. The two isolation capacitors are used for realizing the isolation transmission of signals between the first signal transmission circuit 101 and the second signal transmission circuit 102, and because the detection circuit can detect the differential potential of two-way signals, the two-way isolation capacitor scheme contributes to the stability and safety of signal detection.

As shown in fig. 5, the unidirectional isolation transmission circuit from the first signal transmission circuit 101 to the second signal transmission circuit 102 is a dual-capacitor isolation signal transmission circuit formed by adding a second isolation capacitor 110 to fig. 2, and the functions of the circuits in fig. 5 and fig. 2 are the same.

As shown in fig. 6, the unidirectional isolation transmission circuit from the second signal transmission circuit 102 to the first signal transmission circuit 101 is a dual-capacitor isolation signal transmission circuit formed by adding a second isolation capacitor 110 to fig. 3, and the functions of the circuits in fig. 6 and 3 are the same.

As shown in fig. 7, taking the unidirectional isolation transmission circuit from the first signal transmission circuit 101 to the second signal transmission circuit 102 as an example, the time period of the first specific duty ratio is 75% as an example, and the time period of the second specific duty ratio is 25% as an example. When the input signal SIG _ INL is a 100% high level signal, the input frequency of the modulation signal SIG _ ML is fixed and the duty ratio is constant at 75% of the clock period. When the input signal SIG _ INL is a pulse signal, the high level region of SIG _ INL is modulated to a clock period with a duty cycle of 75%, and the low level region of SIG _ INL is modulated to a clock period with a duty cycle of 25%. When the input signal SIG _ INL is a 100% low signal, the input frequency of the modulation signal SIG _ ML is fixed and the duty ratio is constant at 25% of the clock period.

As shown in fig. 8, the modulation circuit (the first modulation circuit 108 or the second modulation circuit 109) includes:

a signal modulation circuit 500 whose input terminals input a signal SIG _ INL and a reference clock signal CK0, and whose output terminal outputs a modulation signal SIGX for duty-cycle modulating a signal;

the glitch filtering circuit 506 has an input terminal to which the modulation signal SIGX is input, and an output terminal to which two fixed-frequency modulation signals SIG _ ML and SIG _ MLB are output, and is configured to filter a signal glitch.

Further, the signal modulation circuit 500 includes: the frequency-dividing flip-flop 501, the AND gate 502, the inverter 503, the AND gate 504 with 4 inputs, AND the OR gate 505, the reference clock signal CK0 generates the frequency-dividing clock signal CK1 after passing through the frequency-dividing flip-flop 501, the reference clock signal CK0 AND the frequency-dividing clock signal CK1 are input to the AND gate 502, the output signal CK _ AND is output after the reference clock signal CK0 AND the frequency-dividing clock signal CK1 are input to the OR gate 505, the output signal SIG _ INL is input to the inverter 503, the output signal SIG _ INB is output, AND the signals CK _ AND, CK _ OR, SIG _ INL, AND SIG _ INB are input to the AND gate 504 with 4 inputs in common, wherein the signal CK _ AND the signal SIG _ INB are anded, the signal CK _ OR AND the signal SIG _ INL are anded, AND the result of the two is OR, the signal SIGX is obtained, AND the signal SIGX is a transient modulation signal. Since the signal modulation circuit 500 is a combinational logic circuit and causes the transient modulation signal SIGX to generate glitches at the edges of the clock, the modulation signal SIGX is input to the glitch filter circuit 506.

The glitch filter circuit 506 includes: the delay circuit 507, the exclusive-or gate 508, the glitch filtering flip-flop 509, and the

tri-state buffers

510 and 511, the reference clock signal CK0 is input to the exclusive-or gate 508 together with the reference clock signal CK0 after passing through the delay circuit 507, the exclusive-or gate 508 outputs a trigger signal TRIG, the trigger signal TRIG is connected to a clock signal terminal of the glitch filtering flip-flop 509, the modulation signal SIGX is input to a data terminal of the glitch filtering flip-flop 509, and a falling edge of the trigger signal TRIG samples a state of the modulation signal SIGX, thereby filtering the glitch. The forward output terminal of the glitch filtering flip-flop 509 outputs a signal SIG _ ML _ BUF to the tri-state buffer 510, the reverse output terminal outputs a signal SIG _ MLB _ BUF to the tri-state buffer 511, the signal SIG _ ML _ BUF outputs a signal SIG _ ML through the tri-state buffer 510, the signal SIG _ MLB _ BUF outputs a signal SIG _ MLB through the tri-state buffer 511, and the tri-state buffer can enable the output terminal of the modulation circuit to be set to be high-impedance state output when the first signal transmission circuit 101 and the second signal transmission circuit 102 are in the input mode.

As shown in fig. 9, which is an operation waveform diagram of the modulation circuit in fig. 8, the first specific duty ratio is, for example, 75%, and the first specific duty ratio is, for example, 25%. Where CK0 is the reference clock of the entire modulation circuit, and CK1 is a divided-by-two signal of the clock signal CK 0. CK0 AND CK1 are connected to obtain a CK _ AND signal with a duty ratio of 25%, AND CK0 AND CK1 are connected to obtain a CK _ OR signal with a duty ratio of 75%. Through the selection of the and gate 504, when SIG _ INL is high, SIGX is CK _ OR, i.e., a 75% duty cycle signal is input; when SIG _ INL is low, SIGX — CK _ AND, i.e., outputs a 25% duty cycle signal. Therefore, the SIGX realizes 25% -75% modulation of the SIG _ INL signal, and since the SIGX signal is generated by a logic circuit and a glitch is easily generated at a clock signal's jump edge, the SIGX signal is glitch-filtered by the glitch-filtering circuit 506, wherein the delay circuit 507 and the xor gate 508 generate the trigger signal TRIG, the flip-flop 509 samples the SIGX signal using the falling edge of the TRIG signal as the trigger signal, and outputs glitchless 25% -75% modulation signals SIG _ ML and SIG _ MLB.

As shown in fig. 10, is a first embodiment of a detection circuit (either the first detection circuit 104 or the second detection circuit 106) that is suitable for use in the single isolation capacitance scheme shown in fig. 1. The detection circuit comprises:

a hysteresis comparator 701, a positive input stage of which is connected to the first isolation capacitor 103, the charge signal SIG _ MR is input to the positive input stage, and an output terminal of which outputs a voltage signal SIG _ MRD, wherein the hysteresis comparator 701 is configured to restore timing information of a signal before coupling;

a first resistor 702, one end of which is connected to the power supply and the other end of which is connected to the positive input stage of the hysteresis comparator 701;

a second resistor 703, one end of which is connected to the positive input stage of the hysteresis comparator 701 and the other end of which is grounded;

a third resistor 704, one end of which is connected to the power supply and the other end of which is connected to the negative input stage of the hysteresis comparator 701;

a fourth resistor 705 having one end connected to the negative input stage of the hysteresis comparator 701 and the other end connected to ground.

The first resistor 702 and the second resistor 703 provide a default level VX to the positive input of the hysteresis comparator 701, and the third resistor 704 and the fourth resistor 705 provide a default level VY to the negative input of the hysteresis comparator 701, where VX is VY.

As shown in fig. 11, which is an operation waveform diagram of the circuit in fig. 10, a rising edge of SIG _ ML may couple charges to SIG _ MR side, resulting in a voltage rise of SIG _ MR, and then a voltage recovery is achieved through two pull-up and pull-down resistors connected to SIG _ MR, and a falling edge of SIG _ ML may couple charges to SIG _ MR side, resulting in a voltage drop of SIG _ MR, and then a voltage recovery is achieved through two pull-up and pull-down resistors connected to SIG _ MR, so that a voltage waveform of SIG _ MR shown in fig. 11, through a voltage comparison function of a hysteresis comparator 701, recovers a duty ratio and other timing information of SIG _ ML at an output terminal SIG _ MRD of the hysteresis comparator 701.

As shown in fig. 12, is a second embodiment of a detection circuit that is suitable for use in the single isolation capacitance scheme shown in fig. 1. The detection circuit comprises:

a hysteresis comparator 901, the positive input stage of which is connected to the first isolation capacitor 103, the charge signal SIG _ MR is input to the positive input stage, and the voltage signal SIG _ MRD is output from the output terminal, wherein the hysteresis comparator 901 is configured to restore timing information of the signal before coupling;

a fifth resistor 902, one end of which is connected to the bias voltage signal VREFX, and the other end of which is connected to the positive input stage of the hysteresis comparator 901;

a sixth resistor 903, one end of which is connected to the bias voltage signal VREFX, and the other end of which is connected to the negative input stage of the hysteresis comparator 901.

The fifth resistor 902 and the sixth resistor 903 are connected to the bias voltage signal VREFX at the same time, so that the positive input and the negative input of the hysteresis comparator 901 are both equal to the reference voltage VREFX under the default condition.

As shown in fig. 13, is a third embodiment of a detection circuit that is suitable for use in the dual isolation capacitance scheme shown in fig. 4. The detection circuit comprises:

a hysteresis comparator 701, of which a positive input stage is connected to the first isolation capacitor 103, a positive input stage inputs the charge signal SIG _ MR, a negative input stage is connected to the second isolation capacitor 110, a negative input stage inputs the charge signal SIG _ MRB, and an output terminal outputs the voltage signal SIG _ MRD;

As shown in fig. 14, is a fourth embodiment of a detection circuit that is suitable for use in the dual isolation capacitance scheme shown in fig. 4. The detection circuit comprises:

a hysteresis comparator 901, of which a positive input stage is connected to the first isolation capacitor 103, a positive input stage inputs the charge signal SIG _ MR, a negative input stage is connected to the second isolation capacitor 110, a negative input stage inputs the charge signal SIG _ MRB, and an output terminal outputs the voltage signal SIG _ MRD;

As shown in fig. 15, the demodulation circuit (the first demodulation circuit 107 or the second demodulation circuit 105) includes:

a high level time conversion circuit 1111, an input terminal of which inputs the delayed voltage signal SIG _ MRD _ DLY and an output terminal of which outputs a high level time conversion voltage signal VH, the high level time conversion circuit 1111 for converting a high level time amount into a voltage amount VH;

a low level time shift circuit 1112, having an input terminal inputting the delayed voltage signal SIG _ MRD _ DLY and an output terminal outputting a low level time shift voltage signal VL, the low level time shift circuit 1112 being configured to shift an amount of low level time into an amount of voltage VL;

the demodulation flip-flop circuit 1113 has an input terminal to which the high-level time shift voltage signal VH and the low-level time shift voltage signal VL are input, and an output terminal to which the demodulation signal SIG _ OUTR is output.

Further, the high level time-to-voltage circuit 1111 includes:

a current source transistor 1101 having a source connected to the power supply, a gate connected to the bias voltage IBIAS, and a drain connected to the source of the switching transistor 1102;

a switch transistor 1102 having a source connected to the drain of the current source transistor 1101, a gate connected to the output terminal of the inverter 1114, and a drain connected to the high-level time-converted voltage signal VH;

a drain transistor 1103 having a source connected to the high level time conversion voltage signal VH, a gate connected to the drain signal DISC, and a drain grounded;

a capacitor 1104 having one end connected to the high level time conversion voltage signal VH and the other end grounded;

the inverter 1114 has an input terminal connected to the delayed voltage signal SIG _ MRD _ DLY output from the delay circuit, and an output terminal connected to the gate of the switching transistor 1102.

The low level time-to-voltage circuit 1112 comprises:

a current source transistor 1105 having a source connected to the power supply, a gate connected to the bias voltage IBIAS, and a drain connected to the source of the switch transistor 1106;

a switch transistor 1106 having a source connected to the drain of the current source transistor 1105, a gate connected to the delayed voltage signal SIG _ MRD _ DLY output from the delay circuit, and a drain connected to the low level time shift voltage signal VL;

a drain transistor 1107 having a source connected to the low level time-shift voltage signal VL, a gate connected to the drain signal DISC, and a drain grounded;

the capacitor 1108 has one end connected to the low level time-converted voltage signal VL and the other end grounded.

The demodulation trigger circuit 1113 comprises:

a comparator 1109 having a positive input terminal connected to the high-level time conversion voltage signal VH output from the high-level time conversion voltage circuit 1111, a negative input terminal connected to the low-level time conversion voltage signal VL output from the low-level time conversion voltage circuit 1112, and an output terminal outputting a comparison signal DAT to the flip-flop 1110; when VH > VL, the comparison signal DAT is high, and when VH < VL, the comparison signal DAT is low;

the flip-flop 1110 has a data input terminal D connected to the output terminal of the comparator 1109, a trigger clock terminal C connected to the voltage signal SIG _ MRD, and an output terminal Q outputting the demodulation signal SIG _ OUTR.

As shown in fig. 16, the modulated signal SIG _ MRD is restored to SIG _ OUTR by the demodulation circuit. Since the determination of the duty ratio of the current modulation chip by the demodulation circuit is expressed in the next cycle, there will be a delay of 1 modulation clock cycle from SIG _ MRD to SIG _ OUTR, that is, there will be a delay of one modulation clock cycle from SIG _ OUTR to SIG _ INL.

As shown in fig. 17, modulation signal SIG _ MRD is delayed by a delay T0 to generate modulation signal SIG _ MRD _ DLY, and the rising edge of SIG _ MRD _ DLY generates pulse signal DISC having a pulse width of T1. During a high level period of SIG _ MRD _ DLY, the switching transistor 1102 is turned on, the current source transistor 1101 charges the capacitor 1104, the VH voltage rises, the switching transistor 1106 is turned off, and the VL voltage is held; during the low level period of SIG _ MRD _ DLY, the switching transistor 1106 is turned on, the current source transistor 1105 charges the capacitor 1108, VL voltage rises, the switching transistor 1102 is turned off, and VH voltage is maintained; when the SIG _ MRD _ DLY signal is at 25% duty cycle, VH < VL is charged over 1 clock cycle, the comparator 1109 outputs DAT low, the rising edge of SIG _ MRD samples the DAT signal, and SIG _ OUTR output is low. When the SIG _ MRD _ DLY signal is at 75% duty cycle, with charging VH > VL over 1 clock cycle, comparator 1109 outputs DAT high, the rising edge of SIG _ MRD samples the DAT signal, and SIG _ OUTR output is high. Therefore, demodulation of the SIG _ MRD signal is realized, and since the demodulation signal SIG _ OUTR is used for demodulating the previous period of the SIG _ MRD signal, the period of delay is considered relative to the original input signal SIG _ INL.

While the present invention has been described in detail with reference to the preferred embodiments thereof, it should be understood that the above description should not be taken as limiting the present invention. Numerous modifications and alterations to the present invention will become apparent to those skilled in the art upon reading the foregoing description. Accordingly, the scope of the invention should be limited only by the attached claims.

Claims

1. A capacitance-based signal isolation transmission circuit, comprising: the circuit comprises a first signal transmission circuit, a second signal transmission circuit and an isolation capacitor set, wherein the first signal transmission circuit and the second signal transmission circuit are completely consistent in structure, and the isolation capacitor set is respectively connected with the first signal transmission circuit and the second signal transmission circuit;

the isolation capacitor bank realizes signal isolation transmission;

the signal output module demodulates the modulation signal.

2. The capacitance-based signal isolation transmission circuit of claim 1, wherein the signal input module is a modulation circuit that converts a high level of the input signal into a clock cycle of a first duty cycle and converts a low level of the input signal into a clock cycle of a second duty cycle.

3. The capacitance-based signal isolation transmission circuit of claim 2, wherein the first duty cycle is 75% and the second duty cycle is 25%; or the first duty cycle is 25% and the second duty cycle is 75%.

4. The capacitance-based signal isolation transmission circuit of claim 2, wherein the modulation circuit comprises:

5. The capacitance-based signal isolation transmission circuit of claim 4, wherein the signal modulation circuit comprises:

6. The capacitance-based signal isolation transmission circuit of claim 5, wherein the glitch filter circuit comprises:

7. The capacitance-based signal isolation transmission circuit as claimed in claim 1, wherein the signal output module comprises a detection circuit and a demodulation circuit, an input terminal of the detection circuit is connected to the isolation capacitor bank, an output terminal of the detection circuit is connected to an input terminal of the demodulation circuit, the detection circuit converts the charge signal SIG _ MR coupled from the isolation capacitor bank into a voltage signal SIG _ MRD, and the demodulation circuit demodulates the voltage signal SIG _ MRD to obtain a demodulated signal SIG _ OUTR.

8. The capacitance-based signal isolation transmission circuit of claim 7, wherein the isolation capacitor bank comprises a first isolation capacitor that couples the modulated fixed frequency signal SIG ML into the charge signal SIG MR.

9. The capacitance-based signal isolation transmitter circuit of claim 8, wherein the detection circuit comprises:

10. The capacitance-based signal isolation transmitter circuit of claim 8, wherein the detection circuit comprises:

11. The capacitance-based signal isolation transmission circuit of claim 7, wherein the isolation capacitor bank comprises a first isolation capacitor and a second isolation capacitor, the first isolation capacitor couples the modulated fixed frequency signal SIG ML to become the charge signal SIG MR, and the second isolation capacitor couples the modulated fixed frequency signal SIG MLB to become the charge signal SIG MRB.

12. The capacitance-based signal isolation transmitter circuit of claim 11, wherein the detection circuit comprises:

13. The capacitance-based signal isolation transmitter circuit of claim 11, wherein the detection circuit comprises:

14. The capacitance-based signal isolation transmission circuit as claimed in any one of claims 9, 10, 12, 13, wherein the demodulation circuit comprises:

15. The capacitance-based signal isolation transmission circuit of claim 14, wherein the high level time-to-voltage circuit comprises:

16. The capacitance-based signal isolation transmission circuit of claim 14, wherein the low level time to voltage conversion circuit comprises:

17. The capacitance-based signal isolation transmission circuit of claim 15 or 16, wherein the demodulation trigger circuit comprises: