TWI234792B - Capacitor composite circuit element and IC card multilayer capacitor - Google Patents

Capacitor composite circuit element and IC card multilayer capacitor Download PDF

Info

Publication number
TWI234792B
TWI234792B TW92131513A TW92131513A TWI234792B TW I234792 B TWI234792 B TW I234792B TW 92131513 A TW92131513 A TW 92131513A TW 92131513 A TW92131513 A TW 92131513A TW I234792 B TWI234792 B TW I234792B
Authority
TW
Taiwan
Prior art keywords
capacitor
film
thin film
dielectric
circuit
Prior art date
Application number
TW92131513A
Other languages
Chinese (zh)
Other versions
TW200410271A (en
Inventor
Yukio Sakashita
Hiroshi Funakubo
Original Assignee
Tdk Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Tdk Corp filed Critical Tdk Corp
Publication of TW200410271A publication Critical patent/TW200410271A/en
Application granted granted Critical
Publication of TWI234792B publication Critical patent/TWI234792B/en

Links

Classifications

    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06KGRAPHICAL DATA READING; PRESENTATION OF DATA; RECORD CARRIERS; HANDLING RECORD CARRIERS
    • G06K19/00Record carriers for use with machines and with at least a part designed to carry digital markings
    • G06K19/06Record carriers for use with machines and with at least a part designed to carry digital markings characterised by the kind of the digital marking, e.g. shape, nature, code
    • G06K19/067Record carriers with conductive marks, printed circuits or semiconductor circuit elements, e.g. credit or identity cards also with resonating or responding marks without active components
    • G06K19/07Record carriers with conductive marks, printed circuits or semiconductor circuit elements, e.g. credit or identity cards also with resonating or responding marks without active components with integrated circuit chips
    • G06K19/077Constructional details, e.g. mounting of circuits in the carrier
    • G06K19/07749Constructional details, e.g. mounting of circuits in the carrier the record carrier being capable of non-contact communication, e.g. constructional details of the antenna of a non-contact smart card
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01GCAPACITORS; CAPACITORS, RECTIFIERS, DETECTORS, SWITCHING DEVICES, LIGHT-SENSITIVE OR TEMPERATURE-SENSITIVE DEVICES OF THE ELECTROLYTIC TYPE
    • H01G4/00Fixed capacitors; Processes of their manufacture
    • H01G4/33Thin- or thick-film capacitors 
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01GCAPACITORS; CAPACITORS, RECTIFIERS, DETECTORS, SWITCHING DEVICES, LIGHT-SENSITIVE OR TEMPERATURE-SENSITIVE DEVICES OF THE ELECTROLYTIC TYPE
    • H01G4/00Fixed capacitors; Processes of their manufacture
    • H01G4/40Structural combinations of fixed capacitors with other electric elements, the structure mainly consisting of a capacitor, e.g. RC combinations

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Fixed Capacitors And Capacitor Manufacturing Machines (AREA)
  • Semiconductor Integrated Circuits (AREA)

Abstract

The capacitor composite circuit element of the present invention combines an inductor (30) and a capacitor (2). The capacitor (8) has a dielectric thin film (8). The dielectric thin film (8) is composed of a layer compound of bismuth having c-axis oriented substantially perpendicularly to the surface of a substrate for forming the thin film. The layer compound of bismuth has a composition formula represented by (Bi2O2)<2+>(Am-1BmO3m+1)<2-> or Bi2Am-1BmO3m+3, where the symbol m is a positive number, the symbol A is at least one element selected from Na, K, Pb, Ba, Sr, Ca and Bi, and the symbol B is at least one element selected from Fe, Co, Cr, Ga, Ti, Nb, Ta, Sb, V, Mo and W.

Description

1234792 五、發明說明(1) 【發明所屬之技術領域】 本發明係關於如内建於I「士 類,將電容器與除電容器Γ之ΙΙίΓ路元件等之 器複合電路元件。 電路要件予以複合化的電容 【先前技術】 電源ΐ或行動電話等電子機器中,内建著將來自商用 供應二:U電f ’轉換為電子機器所需要的電壓並進行 路:敕:雷敗源芬ί。通常此切換電源電路具有··切換電 ^整流電路、及平滑電路。 個別Γ骨ί路係由電感與電容器所構成’習知乃採用各自 的丄m感元件已知有如··在磁鐵芯上捲繞著捲線 間絲^ ϊ將磁鐵層與芯層交又層積多數層而將芯層在層 片電感元件。此外,電容器元件已知有如:將 電質層與内部電極層交叉層積的層積陶瓷電容器。 此外’隨LSI等的高積體化等,電子機器的小。型化亦 j的發展。在該等電子機器中’切換電源電路乃屬不可 缺。所以,便期望切換電源電路的小型化與薄型化。因 $切換電源電路中所採用的切換電路與整流電路,乃由半 導體7L件所構成,因此便可較輕易地小型化與薄型化。 ,是,平滑電路在習知技術中,因為乃分別形成電 几件與電容器元件,因此其小型化與薄型化頗為困難。 因而便有提案藉由薄膜形成方法,將電感元件盘電容 器元件一體形成的平滑電路元件(參照專利文獻i:日〃本專 利特開平9-2 1 3894號公報)。1234792 V. Description of the invention (1) [Technical field to which the invention belongs] The present invention relates to a composite circuit element such as a built-in IC, a capacitor, and a capacitor circuit except for a capacitor ΓΙΙΓΓ circuit element. Circuit elements are compounded Capacitors [Previous technology] Electronic devices such as power supplies or mobile phones have built-in voltage conversion from commercial supply II: U electricity f 'to electronic devices and carry out the circuit: 敕: thunderstorm source usually. Usually This switching power supply circuit includes a switching circuit, a rectifier circuit, and a smoothing circuit. Individual skeletal circuits are composed of inductors and capacitors. Around the winding wire ^ ϊ, the magnet layer and the core layer are intersected and a plurality of layers are laminated to form the core layer in the layer inductor element. In addition, the capacitor element is known as: a layer in which a dielectric layer and an internal electrode layer are cross-laminated Ceramic capacitors. In addition, with the increase in the size of LSIs and other electronic devices, the size of electronic devices has become smaller. In these electronic devices, switching power circuits is indispensable. Therefore, switching is expected. Miniaturization and thinning of the power supply circuit. Because the switching circuit and rectifier circuit used in the switching power supply circuit are composed of 7L semiconductors, it can be easily miniaturized and thinned. In the conventional technology, it is difficult to miniaturize and reduce the thickness because several electric parts and capacitor elements are formed separately. Therefore, there are proposals for a smooth circuit element in which an inductor element capacitor element is integrally formed by a thin film forming method ( Refer to Patent Document i: Japanese Patent Laid-Open No. 9-2 1 3894).

2030-5987-P(Nl).ptd 1234792 五、發明說明(2) 但是,專利文獻1等之中所記載的薄膜電晶體之介電 質層,因為採用PZT、PLZT、BST、Ta2 05等介電質薄膜,因 此溫度特性將有困難處,相對於使用溫度環境的變化’靜 電電容將發生頗大變化。譬如BST在1 20 °C時的靜電電容, 相較於20°C時的靜電電容之下,顯示出—1〇〇〇〜-4000ppm/ °C的溫度變化,溫度特性差劣。平滑電路元件亦使用於各 種溫度環境下,亦需要溫度特性優越。 再者’該等習知介電質薄膜若介電質薄膜厚度變薄 (譬如1 0Onm以下)的話,將產生介電率降低的傾向。此 外’該等習知介電質薄膜亦具有表面平滑性的困難點,若 介電質薄膜厚度變薄的話,亦將容易發生絕緣不良等問 || 題。換句話說,習知薄膜電容器因為若變薄的話,表面平 滑性將惡化,因此頗難將其他層進行多數層積,頗難將 ^ 容器與其他電路元件層積形成於基板上。 、、 再者,該等習知介電質薄膜,若介電質薄膜厚度 的話,譬如當施加100kV/cm電場之情況時,亦將有 = 容大幅降低的問題。 电電2030-5987-P (Nl) .ptd 1234792 V. Description of the invention (2) However, the dielectric layer of the thin-film transistor described in Patent Document 1 and the like, because of the use of PZT, PLZT, BST, Ta2 05 and other dielectrics Because of the electric thin film, the temperature characteristics will be difficult, and the capacitance will change considerably with the change of the use temperature environment. For example, the electrostatic capacitance of BST at 1 20 ° C shows a temperature change of -1000 to -4000 ppm / ° C compared to the electrostatic capacitance at 20 ° C, and the temperature characteristics are poor. Smooth circuit components are also used in various temperature environments, and they also need to have excellent temperature characteristics. Furthermore, if these conventional dielectric films are thinner (for example, less than 100 nm), the dielectric constant tends to decrease. In addition, these conventional dielectric films also have difficulties in surface smoothness. If the thickness of the dielectric film becomes thinner, problems such as poor insulation will also easily occur. In other words, conventional thin film capacitors have a problem in that if they become thin, the surface smoothness will be deteriorated. Therefore, it is difficult to laminate most other layers, and it is difficult to laminate a container and other circuit elements on a substrate. In addition, if the conventional dielectric film has a thickness of the dielectric film, for example, when an electric field of 100 kV / cm is applied, there will be a problem that the capacity will be greatly reduced. Electricity

再者,如非專利文獻丨:「鉍層狀結構強介電 粒子配向、與對其壓電、焦電材料的應用」竹中正f 1 大學工學博士論文(1 984)中第3章第23〜77頁所示 =、: 成式、或Bi2A B〇 式中的符號m係卜8正數,符號a係:心二b、 連多且Furthermore, as in non-patent literature 丨 "Alignment of bismuth layered ferroelectric particles and its application to piezoelectric and pyroelectric materials" Takenaka Masaru f 1 University Doctoral Dissertation (1 984) Chapter 3 Chapter As shown on pages 23 ~ 77 = ,: In the formula, or in the formula Bi2A B0, the symbol m is a positive number of 8 and the symbol a is: the heart is b.

Ca及=中至少選擇i種元素’符號B係自Fe、c〇、c::: ^ 'mv'MoM中至少選擇i種元素的組成aAt least i kinds of elements are selected in Ca and = ’The symbol B is a composition a where at least i kinds of elements are selected from Fe, co, c ::: ^ 'mv' MoM

1234792 五、發明說明(3) 物’ 法構成所獲得塊材鉍層狀化合物介電質。 物種ΐ (\獻^目關當/上述組成式所示組成 關係)而施行薄』之面=合物之C㈣ 壤,是否仍π祕、(吕如1 a m以下)的情況時,即便變 /尋疋乃了賦予較高介電率且低損失,廿讦烽俨氓雷:古 特性優越、耐壓提昇、介 1主失纟叮獲付漏電肌 亦優越之薄膜之事;均特性優越、表面平滑性 【發明内容】 本發明乃有雲於*卜錄告^ ^ 譬如可配設於1(:卡内部程目的在於提供-種屬於 變化仍少,且偏壓依;性:m、f ’即便高溫下特; 如將電感元件等電容5|之外 谷且低介電損失’譬 合化的電容器複I;:::的電路元件、與電容器予以複 本發明者便針對電容器中所採 其結晶構造進行深人鑽研m“目^ ¥貝4膜材賢興 化合物,而且將該人::發/見採用特定組成的祕層 供適於當作電容器複合電:;::::;:,藉此便!提 本發明者乃發現藉由對基板Φ ,&quot;谷為。換句活5兄, 較高介電率且低損失(tan=薄’亦仍能 優越,表面平滑性亦優越的介電質薄膜。羊血度特隹 本發明的電容器複合雷敗&amp; # ^ ^ ^ 電容器外之電路元件予以複人 、谷态、與除上述 十丁 ^複合化的電容器複合電路元件; 2030-5987-P(Nl).ptd 1234792 五、發明說明(4) 其特徵在於: 上述電容器係具右八 上述介電質薄膜係^電質薄膜; 用基板面的鉍層狀化^ C軸配向呈真正垂直於薄膜形成 該叙層狀二合物;=所構成; 或叫^几+3所示,上、=、、且成式:(Βΐ2〇2)2+(νΛ〇_)2-、 係自Na、Κ、Pb、Ba、s %級成式中的符號111係正數,符號A 號B係自Fe、c〇、、/、Ca及“中至少選擇1種元素,符 至少選擇1種元素。 δ、Ti、Nb、Ta、Sb、V、Mo及W中 本發明的電容器複合 型化與薄型化的電子機器=路70件’可内建於所有要求小 最好上述電路元件^ 電路使用。 ’、电感’上述電路元件係當作平滑 本發明的1C卡中, 本發明中,除電wπ建者上述電容器複合電路元件。 採用薄膜形成法,一二::的電路元件、與電容器,最好 最好上述介電質=於基板上。 最好上述電容器係=置於電極薄膜之間。 板上之下電極、形成上述形成於上述薄膜形成用基 形成於上述介電質薄膜 上之上述介電質薄膜、及 電極、介電質薄膜、、 電極的薄膜電容器。該等下 薄膜形成用基板表面上。〜極係利用薄膜形成法而形成於 上述基板並無特別限制, 非晶質材料、或聚為早、…晶材料,亦可由 亞版專合成樹脂等所構成。基板上所 麵 2030-5987-F(Nl).ptd $ 7頁 1234792 五、發明說明(5) =丄電:,最好形成於[1〇〇]方位。11由將下電極形 成於UOOj方位,便可將其上所形成構成介 層狀化合物的c軸,垂直配向於基板面。 、、、 再者,本發明的複合電路元件,最好在利用 之後而θθ片化。但是,本發明的複合電路元件, 树知基板)、或插座等其他電子機器附屬零件上。 本發明特別以鉍層狀化合物的c軸1〇〇%配向 基板面(即,鉍層狀化合物的C軸配向 直於 可未必C軸配向度為100%。最好上述為0 ’=,亦 向度為80%以上。 曰狀化a物的c軸配 最好構成上述鉍層狀化合物的組成 何數,尤以卜5任何數為佳。因為較容 ,”、 任 最好上述祕層狀化合物係含有稀土族 X Ce、Pr、Nd、Pm、Sm、Eu、Gd、Tb 素^由^ Y、La、1234792 V. Description of the invention (3) The material 'method constitutes the obtained bismuth layered compound dielectric. If the species ΐ (\ 献 ^ 目 关 当 / compositional relationship shown in the above composition formula) and the thin surface of the compound = the C 壤 soil of the compound, is it still π secret, (Lu Ru less than 1 am), even if / Xun Xun is a film that gives higher dielectric rate and low loss. It is a thin film with superior ancient characteristics, improved withstand voltage, and also has excellent leakage current. It has excellent characteristics, Surface smoothness [Content of the invention] The present invention is not uncommon. * For example, it can be configured at 1 (: the internal process of the card is intended to provide-a kind of change is still small, and the bias depends on; m: f 'Even at high temperatures; for example, capacitors such as inductive elements 5 | outer valleys and low dielectric loss', such as a capacitor complex I; ::: circuit elements, and capacitors are duplicated. The crystalline structure of the compound is studied in depth, and the compound is made of a compound material, and the person :: fat / see uses a specific composition of the secretory layer suitable for use as a capacitor composite electric:; ::::; : By this! The inventor of the present invention found that by comparing the substrate Φ, &quot; Gu Wei. In other words, live 5 brothers, compared High dielectric constant and low loss (tan = thin 'is still a dielectric film with superior surface smoothness. Sheep's blood degree is particularly important for the capacitor composite lightning failure of the present invention &amp;# ^ ^ ^ Circuit outside the capacitor The components are compound, valley, and capacitor composite circuit components in addition to the above-mentioned capacitors; 2030-5987-P (Nl) .ptd 1234792 V. Description of the invention (4) It is characterized in that the above-mentioned capacitors have the right eighth The above dielectric thin film is a dielectric thin film; the bismuth layered on the substrate surface is used to form the layered di-composite with the C-axis alignment being truly perpendicular to the thin film; The above, =, and the formula: (Βΐ2〇2) 2+ (νΛ〇_) 2-, is a symbol from the Na, K, Pb, Ba, s% grades 111 is a positive number, the symbol A number B Select at least one element from Fe, co, Ca, /, and Ca, and at least one element from the symbol. Δ, Ti, Nb, Ta, Sb, V, Mo, and W of the capacitor composite type of the present invention With a thin electronic device = 70 pieces of circuit 'can be built in all the requirements of the above circuit components ^ circuit use.', Inductance 'the above circuit components are smooth In the 1C card of the present invention, in the present invention, the above-mentioned capacitor composite circuit element is eliminated. The thin film formation method is adopted. One or two of the circuit elements and the capacitor are preferably the above-mentioned dielectric substance = on the substrate. It is preferable that the capacitor system is placed between the electrode films. The upper and lower electrodes, the above-mentioned dielectric film formed on the above-mentioned dielectric film formed on the above-mentioned film-forming base, and the electrode and the dielectric film are formed. Film capacitors for electrodes. On the surface of the substrate for forming the lower film. ~ The electrode is formed on the substrate by a thin film formation method. There is no particular limitation. Amorphous materials, or early, crystalline materials, can also be used. The sub-version is made of synthetic resin. All on the substrate 2030-5987-F (Nl) .ptd $ 7 pages 1234792 V. Description of the invention (5) = Electricity: It is best to be formed in the [100] orientation. 11 By forming the lower electrode in the UOOj orientation, the c-axis of the interlayer compound formed thereon can be aligned vertically to the substrate surface. It is preferable that the composite circuit element of the present invention is θθ sliced after use. However, the composite circuit element of the present invention may be mounted on other electronic equipment such as a socket, or a socket. In the present invention, the c-axis 100% of the bismuth layered compound is specifically aligned to the substrate surface (that is, the C-axis alignment of the bismuth layered compound is straighter than the C-axis alignment degree is 100%. Preferably, the above is 0 ′ =, also The degree of orientation is 80% or more. The c-axis arrangement of the compound a should preferably constitute the composition of the above-mentioned bismuth layered compound, especially any number of Bu 5. Because of its relatively high capacity, it is better to use the above-mentioned secret layer. Compounds containing rare earths X Ce, Pr, Nd, Pm, Sm, Eu, Gd, Tb

Yb、及Lu中至少選擇1種的元素)。y、〇、 r、Tm、 制4ΐ=!容器複合電路元件中所採用介電質薄膜之 衣xe方法並無特別限制,譬如 貝存膜之 晶、單斜晶等配向於[100]方 方晶、广方晶、斜方 (Βι2〇2)-(νιΒΛΒ+ι)2- . ^Bi ιΒ, ^ 5 ( 的符號m係正數’符號A係自示,上述組成式中 …選擇i種元素,符號B係自二二Select at least one element among Yb and Lu). y, 〇, r, Tm, system 4ΐ =! The method xe of the dielectric film used in the composite circuit element of the container is not particularly limited. For example, the crystals of monolayers and monoclinic crystals are aligned to the [100] square. Crystal, wide square crystal, orthorhombic (Βι2〇2)-(νιΒΛΒ + ι) 2-. ^ Bi ιΒ, ^ 5 (The symbol m is a positive number 'The symbol A is self-explanatory. In the above composition formula ... choose i elements , Symbol B is from two two

Nb、Ta、Sb、V、M〇m 中至 上〇 以 Ga、 選擇1種元素的叙層狀化合 2030-5987-P(Nl).ptd 1234792 五、發明說明(6) 物為主成分的介電質薄膜,便可進行製造。 上述組成的絲層狀化合物$ 祛^ θ ^ ^ ^ θ狀化口物呈C軸配向而構成的介電質 :=,二ίί變·,仍屬於較高介電率(譬如電容率超 ^伊Φ日杜二n tan 6為G. 02以下),漏電流特性優越(譬 :依電場強度5〇kV/cm所測得漏電流為i χ i η—以下, =率在1〇%以下)、提昇耐壓(譬如i〇〇〇kv/cm 度特性,(譬如介電率對溫度的平均變化率,在 基準溫度25 C時為± ΖΟΟρρπι/γ⑺. (譬如表面粗縫度Ra為2nm以下);内)、表面平滑性亦優越 再者,本發明的電容器複合電路元 y即便較薄仍能保持較高的介電率,且表面平滑=乃 因此即便單層仍可大雷交# 佳 化的效果而且可層積多層達更大電容 再者’本發明的電容器複合電 特性優越(孽如特定、、西痄π从^ 午之電合-係頻率 1 3女特疋/皿度下的向頻區域1 Hz之介電率值、 =低頻區域抓之介電值的比,為絕對值〇.9]與 i i寺性優越(譬如特定頻率下, 丨,與測量電壓5V下之介電率值的比,為二= 丹言 雷6、 、電谷器複合電路元件之電容器係每φ 電谷溫度特性優越(靜電電容針⑽产的孚% # ^ f ,、知電 率酿度25 c中,± 20 0Ppm/t以内)。 在基 再者,本發明中所謂「薄膜」係指利用各種薄膜 /斤形成厚度〇.2nm至數“料艇 ^ 、乂成 双私度的材科膜,主旨為除利用Nb, Ta, Sb, V, Mom to the top 0. A layered compound 2030-5987-P (Nl). Ptd 1234792 with Ga and one element selected 5. Description of the invention (6) The electro-membrane can be manufactured. The silk-layered compound with the above composition $ ^ θ ^ ^ ^ ^ The dielectric substance formed by the θ-shaped mouthpiece with C-axis alignment: =, two changes, still belongs to a higher dielectric constant (such as permittivity over ^ Yi Φ Dudu n tan 6 is less than G. 02), excellent leakage current characteristics (for example: the leakage current measured according to the electric field strength 50kV / cm is i χ i η-or less, = rate is less than 10% ) 、 Improve the withstand voltage (such as 10000kv / cm degree characteristics, (such as the average rate of change of dielectric constant vs. temperature, at a reference temperature of 25 C is ± ZO Ορρπι / γ⑺. For example, the surface roughness Ra is 2nm In the following); inner), the surface smoothness is also superior. Furthermore, the capacitor composite circuit element y of the present invention can maintain a high dielectric constant even if it is thin, and the surface is smooth = so even a single layer can still be large thunder The effect of optimizing and can be multilayered to achieve a larger capacitance, and furthermore, the capacitor of the present invention has superior electrical characteristics (such as specific, and 痄 π from ^ noon electric coupling-system frequency 1 3 female special / plate degree) The ratio of the dielectric value of 1 Hz in the lower frequency region to the dielectric value in the low frequency region is an absolute value of 0.9] and is superior in characteristics (such as At a specific frequency, the ratio of the dielectric constant value to the measured voltage at 5V is two = Dan Yan Lei 6. The capacitor of the compound circuit element of the electric valley device has excellent temperature characteristics per φ electric valley. The percentage of fu% # ^ f is within 25 ° C. of the specific electricity rate, within ± 20 0 Ppm / t). In the present invention, the so-called “thin film” refers to the use of various films / jin to form a thickness of 0.2 nm to Counting "material boat ^", the material film of the double family, the main purpose is to use

1234792 五、發明說明(7) 燒結法形成厚度數百# m程度以上 外。在薄膜+,除連續覆蓋既膜厚的塊材(㈤ 有依任意間隔間斷性覆蓋的間]讀連續膜之外,亦含 面的其中一部份,或者亦可全部、点/膜可為形成於基板 【實施方式】 乂、 以下,根據圖式所示實祢合丨_ / 扪實施形態 …1拜細說明本發明。 如第1圖與第2圖所示,本杂—以… 元侔? η孫且亡接a、屯儿兩令汽&amp;形悲的電容器複合電路 μΓ :ϋ 且並聯耦接的電容器2與電 -體形成於ίϋ 係利用薄膜形成方法層積並 :第2圖所不’電谷器複合電路元件2〇中的電容器2係 八有土板4,在此基板4上形成下電極薄膜6。在下電極薄 膜6上形成介電質薄膜8。在介電質薄膜8上形成上電極 膜10。 為層積於此電容器2上並形成電感3〇,因而介電質薄 膜8端部、與上電極薄膜丨〇表面,便由第1層間絕緣層1 2所 復盍’並在其上層積者磁性層14。在磁性層14内部,一齊 配置著供構成電感3 〇用的芯層1 8、與第2層間絕緣層1 6。 第1層間絕緣層1 2與第2層間絕緣層1 6,乃由如氧化石夕馨 或氮化矽等所構成,磁性層1 4係由磁鐵材料等所構成,芯 層1 8係由如同介電質薄膜8或上電極薄膜1 0相同的導電層 所構成,並利用微影法等形成既定芯圖案。該等絕緣層i 2 與1 6、磁性層1 4、芯層1 8係利用如同供形成電容器2用之1234792 V. Description of the invention (7) The sintering method forms a thickness of several hundred meters or more. In the film +, in addition to continuous coverage of both film-thick blocks (㈤ intermittently covered at any interval) and continuous film, it also contains part of the surface, or it can be all, and the point / film can be Formed on the substrate [Embodiment] 乂, the following, according to the actual implementation shown in the figure 丨 _ / 扪 embodiment ... 1 detailed description of the present invention. As shown in Figure 1 and Figure 2, this miscellaneous-with ... Yuan侔? η Sun Qiie then connected a, Tuner two steam &amp; shape sad capacitor composite circuit μΓ: 并联 and capacitor 2 coupled in parallel with the electric body is formed in the ϋ system is laminated using a thin film formation method: the second The capacitor 2 in the compound circuit element 20 of the valley device has a soil plate 4 on which a lower electrode film 6 is formed. A dielectric film 8 is formed on the lower electrode film 6. On the dielectric material, An upper electrode film 10 is formed on the thin film 8. In order to be laminated on the capacitor 2 and form an inductor 30, the end portion of the dielectric thin film 8 and the surface of the upper electrode thin film are formed by the first interlayer insulating layer 12 It is compounded and a magnetic layer 14 is laminated thereon. Inside the magnetic layer 14 are arranged together to form an inductor 3 〇 The core layer 18 and the second interlayer insulation layer 16 are used. The first interlayer insulation layer 12 and the second interlayer insulation layer 16 are made of, for example, oxidized stone azalea or silicon nitride, and the magnetic layer 1 The 4 series is composed of a magnet material, etc., and the core layer 18 is composed of the same conductive layer as the dielectric film 8 or the upper electrode film 10, and a predetermined core pattern is formed by a lithography method or the like. The insulating layers i 2 and 16 6, magnetic layer 1 4 and core layer 1 8 are used for forming capacitor 2

2030-5987-P(Nl).ptd 第10頁 1234792 五、發明說明(8) f琪成形法相同的CVD或濺鍍等薄膜成形 用微影法加工成既定圖案。 办烕並利 f層1 8係形成構成如第}圖所示電感3〇的芯圖案,在 A、,為j而要對電谷器2之上電極薄膜1 〇、與下電極薄膜 n 8接呈並聯耦接於電容器2的狀態。在本實施形態中, 二上二端:乃透過省略圖示的接觸洞或外接端子,而耦 接於上電極薄膜10與下電極薄膜6上。 佳的ίΪ4二由晶格匹配性(laUiCe 曰尊Γ、'Γ曰(譬如:SrTl〇3單結晶、Mg0單結晶、uai〇3單結 =、非晶質材料(譬如:玻璃、熔融石英、Si〇 /si等)、 5成樹脂(譬如:聚醯亞胺樹脂)、或其他材料(孽2 yzr^si、Ce〇2/Si等)等所構成。特別係最好為由立方 :板所播ft方晶、單斜晶等’配向於[1 00 ]方位等的 ^度。冓成。基板4厚度並無特別限制,譬如1()〜1 000 _ 植膜fi基板异4上採用晶格匹配性佳之單結晶情況時的下電極 或者Pt’或R好望為^2°.:CaRU〇3、、或SrRU〇3等導電性氧化物, i電n i =主屬所構成’尤以由配向於[10 0 ]方位的 Λ 屬所構成為佳°若基板4採用配向於 = 可在其表面上形成配向於[⑽]方位- 方、藉由下電極薄膜6由配向於 電極薄膜6上所把=2化物或貴金屬所構成’便可提高下 === 電質薄膜8對[〇°1]方位的配向性, 即徒冋C軸配向性。此種下雷士祛 此裡卜寬極薄膜6可利用普通的薄膜形 2030-5987-P(Nl).ptd 第11頁 1234792 五、發明說明(9) ϊίίί由最好在如賤鍍法或脈衝雷射蒸鑛法⑽)等物 3〇〇 將形成下電極薄膜6的基板4溫度,設定在 300 c以上(尤以5 0 0。。以上為佳)而形成。 由壁fTU i採用非晶質材料情況時的下電極薄膜6,亦可 性4二-4導電性玻璃所構成。當基板4上採用晶格匹配 ϋ早、·晶的情況時,可輕易地在其表面上形成配向於 100 ::的下電極薄膜6 ’藉此便容易提高該下電極薄膜 7 '&quot;電質薄膜8的c軸配向性。但是,即便基板4 採用玻璃等非晶皙姑料,拉叮心上 丨仗土攸4上 材枓仍可形成經提高C軸配向性的介 几、/膜8。此情況下,必須將介電質薄膜8成膜條件最佳 化0 主八他的下電極薄膜6除如金(Au)、纪(Pd)、銀(Ag)等 Ϊ金屬f該等合金之外,尚可採用鎳(Ni)、銅(Cu)等卑金 屬或該等合金。 下電極薄膜6厚度並無特別限制,最好為1〇〜1〇〇〇nm, 尤以50〜l〇〇nm程度為佳。 、上電極薄膜1 〇可採用如同上述下電極薄膜6相同材質 構成i此ϋ ’厚度亦僅要設定為相同的話便可。2030-5987-P (Nl) .ptd Page 10 1234792 V. Description of the invention (8) Thin film forming, such as CVD or sputtering, with the same fqi forming method. It is processed into a predetermined pattern by lithography. The f layer 18 is formed to form the core pattern of the inductor 30 as shown in the figure. At A, j is the upper electrode film 10 of the valley device 2 and the lower electrode film n 8. The connection is in a state of being coupled in parallel to the capacitor 2. In this embodiment, two upper and two terminals are coupled to the upper electrode film 10 and the lower electrode film 6 through contact holes or external terminals (not shown). The best ΪΪ42 is composed of lattice matching (laUiCe, Γ, 'Γ) (such as: SrT10 single crystal, Mg0 single crystal, uai〇3 single junction =, amorphous materials (such as: glass, fused silica, Si〇 / Si, etc.), 50% resin (such as: polyimide resin), or other materials (Se 2 yzr ^ si, Ce〇2 / Si, etc.), etc. In particular, it is best to use cubic: plate The so-called ft square crystal, monoclinic crystal, etc. are aligned to the angle of [1 00] orientation, etc .. The thickness of the substrate 4 is not particularly limited, such as 1 () ~ 1 000 _ used on the implanted film substrate 4 In the case of single crystals with good lattice matching, the lower electrode or Pt 'or R is expected to be ^ 2 ° .: CaRU〇3, or conductive oxides such as SrRU〇3. It is better to be composed of Λ gene aligned in the [10 0] orientation. If the substrate 4 is aligned to = the orientation can be formed on the surface of the [⑽] orientation-square, and the lower electrode film 6 is aligned to the electrode film. The composition of 6 = 2 compounds or precious metals can improve the alignment of the === electric film 8 to the [〇 ° 1] orientation, that is, the C-axis alignment. This kind of lower Negishi is removed here Bu Kuan The thin film 6 can use a common thin film shape 2030-5987-P (Nl) .ptd page 111234792 V. Description of the invention (9) ϊίίί is preferably made of materials such as low-level plating or pulsed laser vaporization (3), etc. 3 〇〇 The temperature of the substrate 4 on which the lower electrode film 6 is formed is set at 300 ° C or higher (especially 500 ° C or higher is preferred). The lower electrode film 6 is formed by using an amorphous material for the wall fTU i. It can also be made of 2-4 conductive glass. When the substrate 4 adopts the lattice matching ϋearly and crystalline, it is easy to form a lower electrode film 6 ′ on the surface aligned with 100 :: This makes it easy to improve the c-axis alignment of the lower electrode film 7 '&quot; the electric film 8. However, even if the substrate 4 is made of an amorphous material such as glass, it is still possible to use the material on the soil. A dielectric film / film 8 with improved C-axis alignment is formed. In this case, the film formation conditions of the dielectric thin film 8 must be optimized. Pd), silver (Ag), and other hafnium metals f and other alloys, base metals such as nickel (Ni), copper (Cu), or these alloys can be used. Lower electrode film 6 thick The degree is not particularly limited, but is preferably 10 to 1000 nm, and more preferably about 50 to 100 nm. The upper electrode film 10 can be made of the same material as the lower electrode film 6 described above. 'The thickness only needs to be set to the same.

&quot;電質薄膜8係本發明薄膜電容元件用組成物之一 例,含有組成式:(Bi2〇2)2+(AmiB九1)2、或 BiA_AU 鉍層狀7合物。一般鉍層狀化合物係將(m-1)個ΑΒ03所構成 的欽礦晶格相連的層狀鈣鈦礦層上下,利用一對B i與0層 形成二明治的層狀結構。在本實施形態中,提高此種鉍層 狀化合物對[〇 〇 1 ]方位的配向性,即提高c軸配性向。換句&quot; Electromagnetic film 8 is an example of a composition for a thin film capacitor element of the present invention, and contains a composition formula: (Bi2202) 2+ (AmiB 9 1) 2, or BiA_AU bismuth layer 7 compound. Generally, a bismuth layered compound is a layered perovskite layer formed by connecting a layer of perovskite with (m-1) Αβ03, and a pair of B i and 0 layers. In this embodiment, the alignment of such a bismuth layered compound to the [OO 1] orientation is improved, that is, the c-axis alignment is improved. In other words

第12頁 2030-5987-P(Nl).ptd 1234792 五、發明說明(ίο) 話說’依鉍層狀化合物的c軸配置呈垂直於基板4狀態形成 介電質薄膜8。Page 12 2030-5987-P (Nl) .ptd 1234792 V. Description of the Invention (1) If the c-axis configuration of the bismuth layered compound is perpendicular to the substrate 4, a dielectric thin film 8 is formed.

本發明中’雖特別以絲層狀化合物的c軸配向度為 1 0 0 %為佳,但是亦可未必c軸配向度為1 〇 〇 %,僅要鉍層狀 化合物的c軸配向度最好在80%以上(尤以90%以上為佳,更 以9 5 %以上為佳)的話便可。譬如採用由玻璃等非晶質材料 所構成基板4而使鉍層狀化合物進行c軸配向的情況時,該 絲層狀化合物的c軸配向度,最好在8 〇 %以上的話便可。此 外’當採用後述各種薄膜形成法使絲層狀化合物進軸 配向的情況時,該级層狀化合物的c軸配向度,最好在9 〇 % 以上(尤以9 5%以上為佳)的話便可。 此處所謂「银層狀化合物的c軸配向度(ρ ) 將形成元全無規配向之多結晶體c軸的X線繞射強度設定j P0,將實際c軸的X線繞射強度設定為p之情況時,便利用 F(%) = (P-P〇)/(l-P〇) X 1〇〇 …(式1 )求得。式1 中所謂 「P」係指來自(0 0 1 )面的反射強度I ( 〇 〇 1 )總計2 I ( 〇 〇 1 )In the present invention, although the c-axis alignment degree of the silk layered compound is particularly preferably 100%, the c-axis alignment degree may not necessarily be 100%, as long as the c-axis alignment degree of the bismuth layered compound is the highest. Fortunately, it is more than 80% (especially 90% or more, more preferably 95% or more). For example, when the substrate 4 composed of an amorphous material such as glass is used to perform c-axis alignment of the bismuth layered compound, the c-axis alignment degree of the silk layered compound is preferably 80% or more. In addition, when the silk laminar compound is axially aligned using various film formation methods described later, the c-axis alignment degree of the layered compound is preferably 90% or more (especially 95% or more is preferred). That's it. Here, the "c-axis alignment degree (ρ) of the silver layered compound will set the X-ray diffraction intensity of the polycrystalline body forming the random orientation of the crystal to the j-axis, and set the actual X-ray diffraction intensity of the c-axis to In the case of p, it is convenient to use F (%) = (PP〇) / (lP〇) X 1〇〇 ... (Equation 1). The "P" in Equation 1 refers to the (0 0 1) plane The reflection intensity I (〇〇1) totals 2 I (〇〇1)

與來自各結晶面(hkl)的反射強度l(hkl)總計SI(hkl)之 比({ Σ 1(001)/ Σ I(hkl)}),相關P〇亦同。其中,在式j 中,將1 0 0%配向於C軸的情況時的X線繞射強度p設定為J &lt; 此外,利用式1,在形成完全無規配向時(p = p〇),F = , 而當形成完全配向於c轴方向的情況時(p = i)= 再者,所謂「鉍層狀化合物的c軸」係指一對(β i 〇 層間的連結方向,即[0 0 1 ]方位。依此藉由使鉍層狀彳2匕2人 物進行c軸配向,使介電質薄膜8的介電特性發揮^最大極&quot;The ratio ({Σ 1 (001) / Σ I (hkl)}) to the total reflection SI (hkl) from the reflection intensity l (hkl) from each crystal plane (hkl) is the same for P0. Here, in Formula j, the X-ray diffraction intensity p when 100% is aligned on the C axis is set to J &lt; In addition, when Formula 1 is used to form a completely random alignment (p = p〇) , F =, and when it is completely aligned in the c-axis direction (p = i) = Furthermore, the so-called "c-axis of bismuth layered compounds" refers to a pair of (β i 〇 layer connection directions, ie [ 0 0 1] Orientation. According to the c-axis alignment of the bismuth layered cymbals 2 and 2 characters, the dielectric characteristics of the dielectric thin film 8 are exerted.

1234792 五、發明說明(11) ,:換句話說,即便將介電質薄膜8膜厚削薄如1〇〇nm以下 J仍可賦予較尚介電率且低損失(t a η占較低),漏電 〜特性優越,耐壓提昇,介電率溫度特性優越,且表面平 滑性亦優越。若減少tan 3的話,損失Q(i/tan 值便將 上升。 上述式中,符號m係若為正數的話便可,並無特別限 制。 鼾而再::若符號“偶數的話’因為具有平行於c面的鏡 ^面’因此便以該鏡射面為界線’自發性極 成分將相互抵消,形成如軸方向上未具極化轴。 保持順電性(paraelectric),實現介電率溫 而且低損失(tan (5較低)。 吁注徒升, 上述式中,符號A係自Na、K、Pb、Ba、Sr 種元素所構成。另外,當符號… ^ 構成之情況時,該等的比率可為任意比率。 凡素 τ上述式中,符號B係自Fe、Co、Cr、Ga、Ti、Nb、 ,、Sb、V、Mo及W中至少選擇i種元素 符號B由2個以上元♦椹士 —比 士 另外,當 比率。 凡素構成之情況時’該等的比率可為任意1234792 V. Description of the invention (11): In other words, even if the thickness of the dielectric thin film 8 is reduced to less than 100 nm, J can still give a relatively high dielectric constant and low loss (ta η accounts for a relatively low) , Leakage ~ Superior characteristics, improved withstand voltage, superior dielectric temperature characteristics, and superior surface smoothness. If tan 3 is reduced, the loss Q (i / tan value will increase. In the above formula, the symbol m is only required if it is a positive number, and there is no special restriction. 鼾 And again: if the symbol "even number 'because it has parallel The mirror surface on the c-plane will therefore use this mirror surface as the boundary line. The spontaneous polar components will cancel each other out, forming a non-polarized axis in the axial direction. Maintaining paraelectricity and achieving the dielectric constant temperature And low loss (tan (low 5). Call for zoom, in the above formula, the symbol A is composed of Na, K, Pb, Ba, Sr elements. In addition, when the symbol ... The ratio of equals can be any ratio. In the above formula, the symbol B is selected from Fe, Co, Cr, Ga, Ti, Nb,, Sb, V, Mo, and W at least i element symbol B is 2 More than ♦ 椹 士 — 比 士 In addition, when the ratio. In the case of prime composition 'the ratio can be arbitrary

I 式.m’n特別最好乃鉍層狀化合物為化學 當此組合物的情況時,特別/提二= 生X係Uw。 在介電質薄膜8中,對上述 有由1丫七、〜、^七士,匕=更含The formula I.m'n is particularly preferably a bismuth layered compound which is chemical. In the case of this composition, special / mention two = raw X series Uw. In the dielectric thin film 8, the above is composed of

1234792 五、發明說明(12)1234792 V. Description of the invention (12)

Dy、Ho、Er、Tm、Yb、及Lu中至少選擇1種的元素。(包含 Y的稀土族元素)。利用稀土族元素的取代量乃隨111值而 異,譬如當m = 3之情況時,在組成式·· Bi2A2_xRexB3012中,最 好0·4$χ$1·8 ’尤以1·0$χ$1·4為佳。藉由將稀土族元 素依此範圍進行取代,便可將介電質薄膜8的居禮溫度 (Curie temper a ture)(從強介電質轉化為順電性的相轉化 溫度)。最好收束於-;[〇〇它以上且1〇〇以下(尤以—5〇以上 且50 C以下為佳)。若居禮點在-100 °c〜+ 1〇〇的話,介雷At least one element selected from Dy, Ho, Er, Tm, Yb, and Lu. (Containing rare earth elements of Y). The amount of substitution using rare earth elements varies with the value of 111. For example, when m = 3, in the composition formula Bi2A2_xRexB3012, it is best to be 0.4 $ x $ 1 · 8 'especially 1 · 0 $ χ $ 1 · 4 is better. By replacing the rare-earth elements in this range, the Curie temperature of the dielectric thin film 8 (the phase transition temperature from the conversion of the ferroelectric to the paraelectric) can be achieved. It is best to be bundled at-; [00〇 it and not more than 100 (especially -50 or more and 50 C or less is preferred). If Curie Point is -100 ° c ~ + 100

λ涛膜8的介電率賊1 μ &lt;L· 、油、®7 ώ: θ At &lt; I 电旱將上升。居禮溫度即便利用DSC(示差掃 描熱篁測置)等你可、任—丨曰 r 〇 , 〇Γ . ^ _ 乃了進仃測1。此外,若居禮點低於室溫 再者&quot;,辟tan/將更減少,結果損失Q值將更加上升。 n言如當m為偶數之rn = 4的情況時,在組成 〇'為』2广认〇15中’最好0.01。$2.0,尤以ο.1 sx^1. 可具優ί漏^ f處薄膜8亦未具稀土族元素Re,如後述仍 變i更佳’。机特性,但是藉由Re取代將可使漏電流特性 度5。二未二二土Λ元素Re的介電質薄膜8 ’利用電場強 下,尤以5x 騎的漏電流,最好在lx 10—7A/cm2以 以下,尤以5%以下下為佳,而且短路率亦最好在10% 相對於此,链: 依相同條侔、# ^ s如具有稀土族元素Re的介電質薄膜8, 下,尤以Ivt測量時的漏電流’最好在5x 10-8仏#以 /cm以下為佳,而且短路率亦最好在5%以The dielectric rate of the lambda film 8 is 1 μ &lt; L ·, oil, ® 7 Price: θ At &lt; I Electricity drought will rise. Even if you use DSC (Differential Scanning Thermal Detector) to wait for you, you can do any of the following: r 〇, 〇Γ. ^ _ This is the first test. In addition, if the courtesy point is lower than room temperature, &quot; the tan / will be reduced, and the loss Q value will increase as a result. In the case where n is an even number of rn = 4, n is preferably 0.01 in a composition of 0 ′ and 2′15. $ 2.0, especially ο.1 sx ^ 1. The thin film 8 at f may not have the rare-earth element Re, but it will be better to be i as described below. Machine characteristics, but by replacing with Re will make the leakage current characteristics degree 5. Di-di-di-dielectric thin film of element Re 8 8 'Using electric field strength, especially leakage current of 5x riding, preferably below 1x 10-7A / cm2, especially below 5%, and The short-circuit rate is also preferably 10%. In contrast, the chain: according to the same bar, # ^ s such as the dielectric thin film 8 with the rare earth element Re, the leakage current when measured especially by Ivt is preferably 5x 10-8 仏 # is preferably less than / cm, and the short circuit rate is also preferably less than 5%.

五、發明說明(13) 下,尤以3%以下為佳 介電質薄膜8可採用如:真空蒸鑛法、 衝雷射蒸鑛法(PLD)、M0CVD(Metal 〇rganic Chewed 法、液相法(CSD法)等各種薄膜形成 法。s ;丨電貝薄膜8特別需要在低溫下進行成膜之情況 時’最好採用電聚CVD、光⑽、雷射CVD、光CSD、雷射 CSD 法。 λ在本貫轭形態中,採用配向於特定方位([1 〇 〇 ]方位 等)的薄膜形成用基板等形成介電質薄膜8。就從降低製造 士二的觀點而言,最好採用由非晶質材料所構成基板4。 右$用依此所形成介電質薄膜8的話,便構成特定組成的 鉍θ狀化合物呈c軸配向。此種介電質薄膜8與採用其之薄 膜電容器2,~便將介電質薄膜膜厚變薄為如20〇nm:下, ,可=予較南介電率且低損失’漏電流特性優_,耐壓提 什,;丨電率溫度特性優越,且表面平滑性亦優越。 因為一可將介電質薄膜8變薄,因此便可同時實現電容 器二it型化。而且,、在本實施形態中,因為 、&quot;電質溥膜8表面平滑性優越,因此可更輕易 地利:薄膜形成方法,在電容器2上層積形成電感3〇更/ 20的:!壯含有電容器2與電感30之電容器複合電路元件 、^子凌體在内之厚度,可變薄至〇. 〇5~〇· 5_程度。所 二t施形態的電容器複合電路元件20,亦可輕易地埋 藏於極溥地1C卡等薄型電子機器内部中。 再者,介電質薄膜8乃因為溫度特性優越,因此即便V. Description of the invention Under (13), the dielectric film 8 which is preferably less than 3% can be used, such as: vacuum vapor deposition method, laser vapor deposition method (PLD), MOCVD (Metal 〇rganic Chewed method, liquid phase) (CSD method) and other thin film formation methods. S; 丨 Electro-shell thin film 8 when it is necessary to form a film at low temperature 'Electropolymer CVD, photoluminescence, laser CVD, optical CSD, laser CSD Λ In the native yoke form, a dielectric thin film 8 is formed using a film-forming substrate or the like that is aligned to a specific orientation ([100] orientation, etc.). From the viewpoint of reducing the number of manufacturers, it is best A substrate 4 made of an amorphous material is used. If a dielectric thin film 8 formed in this manner is used, a bismuth θ-shaped compound having a specific composition is aligned in the c-axis direction. The thin film capacitor 2 will reduce the dielectric film thickness to as low as 20nm, which can be lower than the dielectric constant and low loss. 'Excellent leakage current characteristics_, withstand voltage, The temperature and temperature characteristics are excellent, and the surface smoothness is also excellent. Because the dielectric thin film 8 can be thinned, it can be simultaneously It is possible to realize two-type capacitors. In addition, in this embodiment, because the surface of the capacitor 8 is excellent in smoothness, it is easier to use: a thin-film formation method in which an inductor 3 is laminated on the capacitor 2 and more. / 20: The thickness of the capacitor composite circuit element including capacitor 2 and inductor 30, and the ^ Zi Ling body, can be thinned to the level of 0.05 to 0. 5_ capacitor capacitor composite The circuit element 20 can also be easily buried inside a thin electronic device such as a ground-level 1C card. Furthermore, the dielectric thin film 8 is superior in temperature characteristics, so that

1234792 五、發明說明(14) 使用溫度環境有所變化,因為電容器的靜電電容並未有變 化,因而維持著元件的功能。 μ F1 ϋ者本發明並不僅限定於上述實施形態,在本發明 摩巳圍内可進行各種變化。 '如電谷器2亦可組合搭配電感3 〇以外的電路要件 電备裔複合電路元件。可與電容器2組合搭配的電 導體元伴ΐ ΐ ί別限制,除如電阻等被動元件’尚有如半 人杖,動凡件等等。除平滑電路元件以外的用途, ;(5二.1容器與電感的電路元件,,如單石微波積體電 複合元0件 ^ ::MlCr〇Wa:e Integrated Circuit’MMIC)用 号的且體用、辛,組合搭配主動元件(或被動元件)與電容 盗的具體用途,可例示如衝“戈混成電路基板等。 ,者’本發明+,介電質薄膜8亦 J電:膜U。而層積著多層。本發明的電容器之 膜’乃因為表面平滑性優越二:負薄 壓性仍優越,可較習知層積更多數層P更車又4 ’絕緣性與耐 以下,根據更詳細的實施例說明本發明, 不僅限於該等實施例。料,在下述實施 准本發明並 為確認本發明電容器複合電路元件之電容 ,乃例不著 施例。僅要可確認本發明新賴電容器單獨特=特性的實 此外相關層積電感等其他電路元件方面,的話便可, 2 :導體製程等中所採用薄膜形成微=習知已知 的達成。 倣衫法,便輕易 實施例11234792 V. Description of the invention (14) The operating temperature environment has changed, because the electrostatic capacitance of the capacitor has not changed, so the function of the component is maintained. μ F1 The present invention is not limited to the above-mentioned embodiments, and various changes can be made in the motorcycle enclosure of the present invention. 'If the electric valley device 2 can also be combined with circuit elements other than the inductor 30, the electric backup composite circuit components. The electric conductor element ΐ ΐ which can be combined with the capacitor 2 is not limited. In addition to passive components such as resistors, there are still half-sticks, moving parts, and so on. Uses other than smooth circuit elements; (5.2.1 Circuit elements for containers and inductors, such as monolithic microwave integrated electric composite elements 0 pieces :: MlCr〇Wa: e Integrated Circuit'MMIC) The specific use of body and hard, combined with active components (or passive components) and capacitor theft, can be exemplified such as "mixed circuit boards, etc.", the present invention +, the dielectric thin film 8 is also J electrical: film U . And there are multiple layers. The capacitor film of the present invention is because the surface is smooth. Second: The negative thin pressure is still superior, and it can be laminated more than conventional layers. According to more detailed embodiments, the present invention is not limited to these embodiments. It is expected that the following implementation of the present invention and the confirmation of the capacitance of the capacitor composite circuit element of the present invention are not examples. Only the present invention can be confirmed. Inventing a new capacitor based on the characteristics of the individual capacitors and other circuit components, such as laminated inductors, is fine. 2: Thin film formation used in conductor processes and the like is known and achieved. The imitation shirt method can be easily implemented. example 1

1234792 五、發明說明(15) 將,[1 〇〇]方位磊晶成長出構成下電極薄膜之SrRu〇3的 ^丁1〇3單結晶基板((1〇0)31^11〇3//(1〇〇)31^1〇3)加熱至7〇〇 C。其次,在SrRu03下電極薄膜表面上,採用Ca(CnHi9〇2) 2(C8H32N5)2、Sr(C&quot;H19 02 )2 (C8H32N5)2、Bi(CH3)2&amp;Ti(〇-i-C3H7) 4為原料\利用MOCVD法,使膜厚約丨⑽⑽的。』^〜 ΒΙΤΊΟβ薄膜(&quot;電質薄膜)’變化χ = 〇、,而複數形 成。X值的控制乃利用調整Ca原料與Sr原料的載氣流量而 執行。1234792 V. Description of the invention (15) The [1 00] orientation epitaxial growth will form a SrRu 03 single crystal substrate ((100) 31 ^ 11〇3 // (100) 31 ^ 103) heated to 700C. Secondly, on the surface of the electrode film under SrRu03, Ca (CnHi9〇2) 2 (C8H32N5) 2, Sr (C &quot; H19 02) 2 (C8H32N5) 2, Bi (CH3) 2 &amp; Ti (〇-i-C3H7) 4 as the raw material \ Using the MOCVD method, the film thickness is about 丨 ⑽⑽. ^^ ΒΙΤΊΟβ thin film (&quot; electrolytic film) 'changes χ = 〇, and is formed in plural. The X value is controlled by adjusting the carrier gas flow rates of the Ca raw material and the Sr raw material.

再者,在上述化學式中,當χ=〇時,SrBi4Ti4〇i5薄膜 (SBTi薄膜/組成式:Bi2Am a%㈣中,符號^4、符號 A3-Sr + ^i2 及符唬β4 = Τι4)。此外,當χ = 1 時,CaBi4Ti4〇i5 薄膜 (cbti薄膜/組成式:Bi2m3中,符號㈣、符號 A3 =Ca + B i2 及符號b4 =T i4)。 忒等介電質薄膜結晶結構經x線繞射(XRD)測量結果, 可確認到配向於[001]方位,換句話說,垂直於SrTi〇3單結 晶基板表面的C軸配向。此外,對該等介電質薄膜表面粗 糙度(ja),依據JIS_B060 1,採用AFM(原子力顯微鏡,精 工工業公司製、s P I 3 8 0 0 )進行測量。Furthermore, in the above chemical formula, when χ = 0, the SrBi4Ti4oi5 film (SBTi film / composition formula: Bi2Am a% ㈣, symbol ^ 4, symbol A3-Sr + ^ i2, and symbol β4 = Ti4). In addition, when χ = 1, the CaBi4Ti4〇i5 thin film (cbti thin film / composition formula: Bi2m3, symbol ㈣, symbol A3 = Ca + B i2, and symbol b4 = T i4). As a result of X-ray diffraction (XRD) measurement of the crystal structure of 忒 and other dielectric thin films, it can be confirmed that the orientation is in the [001] orientation, in other words, the C-axis orientation perpendicular to the surface of the SrTi03 single crystal substrate. The surface roughness (ja) of these dielectric films was measured using AFM (Atomic Force Microscope, manufactured by Seiko Instruments Inc., s P I 3800) in accordance with JIS_B0601.

其次,在該等介電質薄膜表面±,利用賤鑛法形成0. Ιππηφ的Pt上電極薄膜,製成薄膜電容器樣本。 評估所獲得電容器樣本的電氣特性(介電率、tan 5、 損失Q值、漏電流、耐壓)、及介電率的溫度特性。 ’I電率(無單位)係對電容器樣本用數位lcr計 (YHR公司製4274A),從在室溫(25。〇 '測量頻率Secondly, on the surface of the dielectric thin film ±, a Pt upper electrode thin film of 0.1 ππηφ was formed using a base ore method to prepare a thin film capacitor sample. The electrical characteristics (dielectric rate, tan 5, loss Q, leakage current, withstand voltage) of the obtained capacitor samples were evaluated, and the temperature characteristics of the dielectric rate were evaluated. ‘I electric rate (unitless) is a digital lcr meter (4274A, manufactured by YHR) for capacitor samples, and the frequency is measured at room temperature (25.0 ′).

1234792 五、發明說明(16) 1 0 0kHz(AC2 0mV)條件下,所測得靜電電容、電容器樣本的 電極尺寸、及電極間距離計鼻出。 tan 5係在如同上述測量靜電電容的相同條件下進行 測量,隨此亦計算出損失Q值。 漏電流特性(單位A/cm2)係依電場強度5〇kV/cm測量。 介電率的溫度特性係對電容器樣本,依上述條件測量 介電率’當將基準溫度設定為2 5 C時,測量相對於 - 55〜+ 150 °C溫度範圍内之溫度下的介電率平均變化率(△ ε ),並計算出溫度係數(ppm/ °c )。耐壓(單位kv/cm)係在 漏電流特性測量中,利用使電壓上升而測得。 該等結果,如表1所示。1234792 V. Description of the invention (16) Under the condition of 100kHz (AC2 0mV), the measured capacitance, the electrode size of the capacitor sample, and the distance between the electrodes are measured. Tan 5 was measured under the same conditions as above for measuring capacitance, and the loss Q was calculated. The leakage current characteristic (unit A / cm2) is measured according to the electric field strength of 50 kV / cm. The temperature characteristic of the dielectric constant is measured for the capacitor sample according to the above conditions. 'When the reference temperature is set to 2 5 C, the dielectric constant is measured at a temperature in the temperature range of -55 ~ + 150 ° C. The average change rate (△ ε), and calculated the temperature coefficient (ppm / ° c). The withstand voltage (in kv / cm) is measured by increasing the voltage in the leakage current characteristic measurement. These results are shown in Table 1.

2030-5987-P(Nl).ptd 第19頁 234792 五、發明說明(17) 室 η 諸 室 |_χ ο 1 ' 1 〇 •~*· ο BW bf銪 砗(V Θ1 ·—» a~i 1—1 Γπι 將 bt Ν' 5h ·—L 〇 1»»L o ^τΛ. 暴i 訖到 II » V 1~~L 〇 〇 V .—ι- Ο o lg t随 ^ 八 Ο ·—1 -Ιο X ^ 八 O -1 -lo x ^ m Q 鵃 oo ο g o 鹏 1 ·—L K^i 〇 贫|S π W 爲染 \ J vtofi Λ ο S Λ O s § 〇3 V ◦ V o 碰 /02030-5987-P (Nl) .ptd Page 19 234792 V. Description of the invention (17) Room η Various rooms | _χ ο 1 '1 〇 • ~ * · ο BW bf 铕 砗 (V Θ1 · — »a ~ i 1—1 Γπι will bt Ν ′ 5h · —L 〇1 »» L o ^ τΛ. Ii 讫 to II »V 1 ~~ L 〇〇V .—ι- 〇 o lg t follows ^ 〇 0—-1 -Ιο X ^ eight O -1 -lo x ^ m Q 鵃 oo ο go / 0

UUUI 2030-5987-P(Nl).ptd 第20頁 1234792 五、發明說明(18) 評估 如表1所示,實施例1所獲得鉍層狀化合物之〇軸配向 膜確認到耐壓高至1 0 0 0kV/cm以上,漏電流低至1 X 1 〇_7以 下程度,介電率在2 0 0以上,tan 6在〇· 〇2以下,損失q值 亦在5 0以上。藉此便可期待更加薄膜化,進而亦可期待薄 膜電容器的高電容化。 再者’在實施例1中,亦確認到溫度係數雖在土 1 5Oppm/ °C以下的非常小值,但是介電率在2〇〇以上的較大 狀態,具有當作溫度補償用電容器材料的優越基本特性。 此外,在實施例1中,因為表面平滑性優越,因此確認到UUUI 2030-5987-P (Nl) .ptd Page 20 1234792 5. Description of the invention (18) As shown in Table 1, the 0-axis alignment film of the bismuth layered compound obtained in Example 1 was confirmed to have a pressure resistance as high as 1 Above 0 0 0 kV / cm, the leakage current is as low as 1 X 1 〇_7, the dielectric constant is above 200, tan 6 is below 〇 2, and the loss q value is also above 50. This can be expected to further reduce the thickness of the film, and further increase the capacitance of the thin film capacitor. Furthermore, in Example 1, it was also confirmed that although the temperature coefficient is a very small value of less than 150 ppm / ° C, the dielectric constant is larger than 2000, and it is used as a capacitor material for temperature compensation. Superior basic characteristics. In addition, in Example 1, it was confirmed that the surface smoothness was excellent.

頗適於層積結構製造的薄膜材料。換句話說,經由實施例 1,可確認到鉍層狀化合物的c軸配向膜之有效性。 實施例2 在本貫施例中,採用實施例丨所製得薄膜電容器樣 本,評估頻率特性與電壓特性。 7 頻率特性係如下述進行評估。針對電容器樣本, 溫(25 C)下,使頻率從lkHz變化至1MHz,測量靜Thin film material suitable for manufacturing laminated structure. In other words, through Example 1, the effectiveness of the c-axis alignment film of the bismuth layered compound was confirmed. Example 2 In this example, the film capacitor samples prepared in Example 丨 were used to evaluate the frequency characteristics and voltage characteristics. 7 The frequency characteristics were evaluated as follows. For the capacitor sample, change the frequency from 1kHz to 1MHz at temperature (25 C), and measure the static

:二算介電率,結果如第4圖所示。靜電電容的測量採二 化Hi如第」圖所示,確認到即便使特定溫度下的頻率 性優越。 “、、欠化換句活况,確認到頻率 電壓特性係依如下述進行評估。 u頻率uookw下的測量電壓(施加電: 又5kV/cm)變化至5V(電場強度⑽v/cm),測量: Calculate the permittivity. The result is shown in Figure 4. The electrostatic capacitance was measured using Hi2 as shown in the figure, and it was confirmed that the frequency characteristics were superior even at a specific temperature. "、, understatement In other words, it was confirmed that the frequency and voltage characteristics were evaluated as follows. The measured voltage (applied electricity: 5kV / cm) at u frequency uookw was changed to 5V (electric field strength ⑽v / cm) and measured.

1234792 五、發明說明(19) 壓下的靜電電容(測量溫度2 5 °C ),並計算介電率,結果如 第5圖所示。靜電電容的測量採用LCR計。如第5圖所示, 確認到即便使特定頻率下的測量電壓變化至5 V,介電率值 仍無變化。換句話說,確認到電壓特性優越。 以上,雖針對本發明的實施形態與實施例進行說明, 惟本發明並不僅限定於該等實施形態與實施例,在不脫逸 本發明主旨範疇内,當然可實施各種態樣。 如上述所說明,依照本發明的話,可提供屬於譬如可 配設於I C卡内部程度的尺寸小型,即便高溫下特性變化仍 少,且偏壓依存性較少,大電容且低介電損失,譬如將電 感元件等電容器之外的電路元件、與電容器予以複合化的&lt;1 電容器複合電路元件。1234792 V. Description of the invention (19) The electrostatic capacitance under pressure (measured at 25 ° C), and the dielectric constant is calculated. The result is shown in Figure 5. The electrostatic capacitance is measured using an LCR meter. As shown in Fig. 5, it was confirmed that the dielectric constant value did not change even if the measured voltage at a specific frequency was changed to 5 V. In other words, it was confirmed that the voltage characteristics were superior. Although the embodiments and examples of the present invention have been described above, the present invention is not limited to these embodiments and examples. Of course, various aspects can be implemented without departing from the scope of the present invention. As described above, according to the present invention, it is possible to provide a small size which can be arranged inside an IC card, for example, even if the temperature is high, the characteristic change is still small, and the bias dependency is small, the capacitance is large, and the dielectric loss is low. For example, a circuit component other than a capacitor such as an inductive element, and a capacitor composite circuit element combined with a capacitor &lt; 1.

2030-5987-P(Nl).ptd 第22頁 234792_ 圖式簡單說明 第1圖係本發明一實施例的電容器複合電路元件之電 路圖。 第2圖係本發明一實施例的電容器複合電路元件之概 略剖視圖。 第3圖係本發明一實施例的電容器複合電路元件中, 供執行電容器單體試驗用之樣本剖視圖。 第4圖係本發明實施例的電容器之頻率特性圖。 第5圖係本發明實施例的電容器之電壓特性圖。 (符號說明) 2 電容器 4 基板 6 下電極薄膜 8介電質薄膜 1 0 上電極薄膜 1 2 第1層間絕緣層 14 磁性層 16 第2層間絕緣層 18 芯層 20電容器複合電路元件 30電感2030-5987-P (Nl) .ptd Page 22 234792_ Brief Description of Drawings Figure 1 is a circuit diagram of a capacitor composite circuit element according to an embodiment of the present invention. Fig. 2 is a schematic cross-sectional view of a capacitor composite circuit element according to an embodiment of the present invention. FIG. 3 is a cross-sectional view of a sample of a capacitor composite circuit element according to an embodiment of the present invention for performing a capacitor unit test. FIG. 4 is a frequency characteristic diagram of a capacitor according to an embodiment of the present invention. FIG. 5 is a voltage characteristic diagram of a capacitor according to an embodiment of the present invention. (Description of symbols) 2 Capacitor 4 Substrate 6 Lower electrode film 8 Dielectric film 1 0 Upper electrode film 1 2 First interlayer insulating layer 14 Magnetic layer 16 Second interlayer insulating layer 18 Core layer 20 Capacitor composite circuit element 30 Inductor

2030-5987-P(Nl).ptd 第23頁2030-5987-P (Nl) .ptd Page 23

Claims (1)

申請專利範圍 述電 種電容器複合蕾私 容器外之電路元件予以複^件,將電容器、與除上 其特徵在於: ” ΐϊ: = ί具有介電質薄膜; 用某係由μ配向呈真正垂直於薄膜形成 用基板面的鉍層狀化合物 、 且孓潯Μ爪 該鉍層狀化合物係由J二$ ’ (叫〇2)2+(14〇,_„+1)2-、\成式. 式中的符號m係正數,符味/Bl2VlBm〇3in+3所示,上述組成 心中至少選擇i種元係自Na、K、Pb、Ba、Sr、Ca Ti、Nb、Ta、Sb、V、M〇 及:號8 係自 Fe、C〇、Cr、Ga、 中 2. 如申請專利範圍第7:至/選擇1種元素。 上述介電質薄膜H之,容器複合電路元件,其 中 3. 如申請專d §極薄膜之間。 上述㈣狀化合器複合電路元件,其 件 4. 如申請專利範Ξΐ T二係8〇%〜 祀固第1、2或3項之雷交怒 5其:申以!質薄膜係具有層積構造 路元 件 *如申6月專利乾圍第1、2或3項之電容。。 其中’上述電路要件係電感電?複合電路元 滑電路使用。 電路元件係當作平 6. -種1C卡’埋藏著申請 合電路元件。 ㈤第5項之電容器複The scope of the patent application is to duplicate the circuit elements outside the electric capacitor capacitor composite container. The capacitors and capacitors are characterized by: ”ΐϊ: = ί has a dielectric film; it is truly vertical with μ orientation from a certain system The bismuth layered compound on the surface of the substrate for thin film formation, and the claw layer of the bismuth layer is composed of J 2 '(called 〇2) 2+ (14〇, _ „+ 1) 2-, \ formula The symbol m in the formula is a positive number, as shown by the symbol / Bl2VlBm〇3in + 3. At least i kinds of elementary systems are selected from the above composition center from Na, K, Pb, Ba, Sr, Ca Ti, Nb, Ta, Sb, V , M0 and: No. 8 are from Fe, Co, Cr, Ga, and middle 2. If the scope of patent application is 7: to / select 1 element. Among the above-mentioned dielectric thin films H, container composite circuit elements, among which 3. If applied for d § between thin films. The above-mentioned ㈣-shaped coupler composite circuit element, its components 4. Such as the patent application Ξΐ T series 2 80% ~ worship the thunder cross of item 1, 2 or 3 5 it: apply for! The thin film is a layered structure road element. * If the capacitor of the June patent application No. 1, 2 or 3 is applied. . Which ‘the above circuit elements are inductive? Sliding circuit for composite circuit elements. The circuit components are regarded as flat 6.-1C card 'is embedded with the application circuit components.电容器 Capacitor complex of item 5
TW92131513A 2002-11-12 2003-11-11 Capacitor composite circuit element and IC card multilayer capacitor TWI234792B (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2002328574A JP2004165372A (en) 2002-11-12 2002-11-12 Capacitor compound circuit element and ic card

Publications (2)

Publication Number Publication Date
TW200410271A TW200410271A (en) 2004-06-16
TWI234792B true TWI234792B (en) 2005-06-21

Family

ID=32310548

Family Applications (1)

Application Number Title Priority Date Filing Date
TW92131513A TWI234792B (en) 2002-11-12 2003-11-11 Capacitor composite circuit element and IC card multilayer capacitor

Country Status (3)

Country Link
JP (1) JP2004165372A (en)
TW (1) TWI234792B (en)
WO (1) WO2004044935A1 (en)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN208173340U (en) 2015-10-30 2018-11-30 株式会社村田制作所 LC multiple device and processor
CN113496821A (en) * 2020-04-03 2021-10-12 余学恩 Micro battery of chip process technology

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH07106198A (en) * 1993-10-08 1995-04-21 Matsushita Electric Ind Co Ltd Manufacture of laminated thin-film capacitor
JP3349612B2 (en) * 1994-01-13 2002-11-25 ローム株式会社 Dielectric capacitor and method of manufacturing the same
JPH08253324A (en) * 1995-03-10 1996-10-01 Sumitomo Metal Mining Co Ltd Ferroelectric thin film constitution body
JP2692646B2 (en) * 1995-05-11 1997-12-17 日本電気株式会社 Capacitor using bismuth-based layered ferroelectric and its manufacturing method
JPH09213894A (en) * 1996-02-06 1997-08-15 Nippon Telegr & Teleph Corp <Ntt> Smoothing circuit element
JPH10294432A (en) * 1997-04-21 1998-11-04 Sony Corp Ferroelectric capacitor, ferroelectric nonvolatile storage device, and ferroelectric device
JP2000169297A (en) * 1998-09-29 2000-06-20 Sharp Corp Production of thin ferroelectric oxide film, thin ferroelectric oxide film and thin ferroelectric oxide film element

Also Published As

Publication number Publication date
TW200410271A (en) 2004-06-16
WO2004044935A1 (en) 2004-05-27
JP2004165372A (en) 2004-06-10

Similar Documents

Publication Publication Date Title
CN1974472B (en) Composition for thin-film capacitive device, insulating film, thin-film capacitive device, and capacitor
JP4623005B2 (en) Composition for thin film capacitor, high dielectric constant insulating film, thin film capacitor, thin film multilayer capacitor, and method for manufacturing thin film capacitor
US6876536B2 (en) Thin film capacitor and method for fabricating the same
KR20060005342A (en) Barium strontium titanate containing multilayer structures on metal foils
WO2004077566A1 (en) High dielectric constant insulating film, thin-film capacitive element, thin-film multilayer capacitor, and method for manufacturing thin-film capacitive element
EP1598840A1 (en) Composition for thin-film capacitor device, high dielectric constant insulator film, thin-film capacitor device, thin-film multilayer capacitor, electronic circuit and electronic device
TWI239024B (en) Composition for thin film capacitor, insulation film with high dielectric rate, thin film capacitor, thin film laminated capacitor, and manufacturing method of thin film capacitor
US20060072282A1 (en) Dielectric thin film, thin film capacitor element, and method for manufacturing thin film capacitor element
CN100431066C (en) Thin film capacity element-use composition, high-permittivity insulation film, thin film capacity element and thin film multilayer capacitor
CN114388693A (en) Dielectric material, and device and memory device including the same
TWI234792B (en) Capacitor composite circuit element and IC card multilayer capacitor
KR20050092437A (en) Composition for thin film capacitance element, insulating film of high dielectric constant, thin film capacitance element, thin film laminated capacitor and method for manufacturing thin film capacitance element
TWI227503B (en) Thin film capacitor for reducing power supply noise
JP4604939B2 (en) Dielectric thin film, thin film dielectric element and manufacturing method thereof
US6958900B2 (en) Multi-layered unit including electrode and dielectric layer
US20040165336A1 (en) Multi-layered unit including electrode and dielectic layer
JP4088477B2 (en) Thin film capacitor and thin film multilayer capacitor
US7067458B2 (en) Multi-layered unit including electrode and dielectric layer
JP2004043251A (en) Oxide laminated film containing perovskite-type oxidized film
JP2004186540A (en) Laminated electronic parts
Ma et al. Ferroelectric Thin Films Grown on Base-Metal Foils for Embedded Passives
JP2006128657A (en) Dielectric thin film, thin film capacitor element, and method of manufacturing thin film capacitor element

Legal Events

Date Code Title Description
MM4A Annulment or lapse of patent due to non-payment of fees