JPH07106198A - Manufacture of laminated thin-film capacitor - Google Patents

Manufacture of laminated thin-film capacitor

Info

Publication number
JPH07106198A
JPH07106198A JP25268393A JP25268393A JPH07106198A JP H07106198 A JPH07106198 A JP H07106198A JP 25268393 A JP25268393 A JP 25268393A JP 25268393 A JP25268393 A JP 25268393A JP H07106198 A JPH07106198 A JP H07106198A
Authority
JP
Japan
Prior art keywords
thin film
film layer
metal
dielectric
metal electrode
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP25268393A
Other languages
Japanese (ja)
Inventor
Akiyuki Fujii
映志 藤井
Atsushi Tomosawa
淳 友澤
Satoru Fujii
覚 藤井
Ryoichi Takayama
良一 高山
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Industrial Co Ltd filed Critical Matsushita Electric Industrial Co Ltd
Priority to JP25268393A priority Critical patent/JPH07106198A/en
Priority to EP94104369A priority patent/EP0617440B1/en
Priority to DE69401826T priority patent/DE69401826T2/en
Priority to US08/215,816 priority patent/US5459635A/en
Publication of JPH07106198A publication Critical patent/JPH07106198A/en
Priority to US08/465,350 priority patent/US5663089A/en
Pending legal-status Critical Current

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Abstract

PURPOSE:To provide the method of manufacturing a laminated thin-film capacitor, which can miniaturize a chip capacitor and which can make the capacity of the chip capacitor large. CONSTITUTION:A dielectric thin-film layer 4 in a film thickness of 3mum or lower is formed, by a plasma CVD method, on a substratum substrate 1 on which a metal-electrode thin-film layer 2 has been formed by a vacuum deposition method or a sputtering method. The two layers are laminated alternately, a laminated body is cut in such a way that metal-electrode thin-film layers 2, 4, 6 faced alternately sidewalls every other layer, external electrodes 8, 9 are formed on cut faces, the electrodes are brought into continuity with the metal-electrodes thin-film layers 2, 4, 6 at the inside, and a small and large- capacity laminated thin-film capacitor is manufactured.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【産業上の利用分野】本発明は、小型、大容量チップコ
ンデンサとして用いられる、積層薄膜コンデンサの製造
方法に関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a multilayer thin film capacitor used as a small-sized, large-capacity chip capacitor.

【0002】[0002]

【従来の技術】ペロブスカイト型結晶構造のチタン酸ス
トロンチウム(SrTiO3)は、約110K以上の温
度のにおいては立方晶であり常誘電体である。チタン酸
ストロンチウムを主成分としたセラミックスは、同じ結
晶構造のチタン酸バリウム(BaTiO3)系に比べて
誘電率は低いが、温度特性がよく誘電損失も少ないとい
った特徴を有する。また、バリウムや鉛などのシフタを
加えてキュリー点をシフトさせることにより、常温にお
いて常誘電性で高誘電率のセラミックスが得られ、高周
波・高電圧用コンデンサとして幅広く利用されている。
また、代表的な緩和型強誘電体の一つであるPb(Mg
1/3,Nb2/3)O3とチタン酸鉛(PbTiO3)の複合
材料であるPb(Mg1/3,Nb2/3)O3−PbTiO3
の複合ペロブスカイト構造化合物は、チタン酸バリウム
系強誘電体に比べて、大きな比誘電率と良好な直流バイ
アス特性を有するため、小型大容量積層コンデンサなど
に応用されている。
2. Description of the Related Art Strontium titanate (SrTiO 3 ) having a perovskite crystal structure is a cubic crystal and a paraelectric material at a temperature of about 110 K or higher. Ceramics containing strontium titanate as a main component have a lower dielectric constant than barium titanate (BaTiO 3 ) based on the same crystal structure, but have characteristics of good temperature characteristics and small dielectric loss. Further, by adding a shifter such as barium or lead to shift the Curie point, a paraelectric ceramic having a high dielectric constant can be obtained at room temperature, which is widely used as a capacitor for high frequency and high voltage.
In addition, Pb (Mg) which is one of typical relaxation type ferroelectrics
Pb (Mg 1/3 , Nb 2/3 ) O 3 -PbTiO 3 which is a composite material of 1/3 , Nb 2/3 ) O 3 and lead titanate (PbTiO 3 ).
The complex perovskite compound of (1) has a large relative permittivity and good DC bias characteristics as compared with barium titanate-based ferroelectrics, and is therefore applied to small and large capacity multilayer capacitors.

【0003】一方、電子機器の小型化、高密度実装化に
対応するため、チップコンデンサの小型化、大容量化が
進んでいる。大容量化を達成するには、比誘電率の大き
い誘電体材料を用いることや、誘電体層を薄くして積層
数を増加する方法がある。たとえば、エレクトロニク・
セラミック誌103号(1990年)第57頁から第6
1頁に積層セラミックコンデンサの製造方法が発表され
ている。この文献での積層セラミックコンデンサの製造
における誘電体層と金属電極層の積層方法は以下の通り
である。BaTiO3などの誘電体材料の粉末を配合、
混合し、かつ乾燥させたものをスラリ調合して薄膜状の
シートに成形する。このシートにパラジウムなどの内部
電極ペーストを印刷し、シートを積み重ねる。この操作
を数回繰り返し、その後目的の大きさに切断し、セラミ
ックと金属の同時焼成を行うといったものである。
On the other hand, in order to cope with miniaturization of electronic equipment and high-density mounting, miniaturization and large capacity of chip capacitors are being advanced. In order to achieve high capacity, there is a method of using a dielectric material having a large relative dielectric constant or a method of increasing the number of layers by thinning the dielectric layer. For example, electronic
Ceramics Magazine No. 103 (1990), pages 57 to 6
A manufacturing method of a monolithic ceramic capacitor is announced on page 1. The method of laminating the dielectric layer and the metal electrode layer in the production of the laminated ceramic capacitor in this document is as follows. Mixing powder of dielectric material such as BaTiO 3 ,
The mixed and dried product is slurried and formed into a thin film sheet. An internal electrode paste such as palladium is printed on this sheet, and the sheets are stacked. This operation is repeated several times, and then cut to a desired size, and the ceramic and metal are co-fired.

【0004】[0004]

【発明が解決しようとする課題】しかしながら、上記積
層方法では、出発原料のBaTiO3が粒径1μm程度
の粉末であり、これをスラリ調合し、シート状に成形し
て焼成するため、誘電体層を3μm以下に薄くしようと
すると、膜厚の均一性や電極間の絶縁性に問題があり、
技術的に困難であった。また焼成温度が約1200℃と
高く、電極材料が限定されるため、安価で特性の良い積
層コンデンサを低温で得る製造方法を見出すことが求め
られていた。
However, in the above-mentioned lamination method, the starting material BaTiO 3 is a powder having a particle size of about 1 μm, and this is compounded into a slurry, molded into a sheet and fired, so that the dielectric layer is formed. Is less than 3 μm, there is a problem in film thickness uniformity and insulation between electrodes.
It was technically difficult. Further, since the firing temperature is as high as about 1200 ° C. and the electrode materials are limited, it has been required to find a manufacturing method for obtaining an inexpensive and excellent laminated capacitor at low temperature.

【0005】本発明は前記従来の課題に留意し、チップ
コンデンサの小型化、大容量化を可能とする積層薄膜コ
ンデンサの製造方法を提供することを目的とする。
In view of the above-mentioned conventional problems, the present invention has an object to provide a method for manufacturing a laminated thin film capacitor which enables miniaturization and large capacity of a chip capacitor.

【0006】[0006]

【課題を解決するための手段】上記課題を解決するため
に本発明は、基板上に金属電極薄膜層を真空蒸着法また
はスパッタリング法によってパターン形成し、その上に
誘電体薄膜層として、チタン酸ストロンチウムを主成分
とするペロブスカイト型酸化物やPb(Mg1/ 3,Nb
2/3)O3とチタン酸鉛を主成分とする複合ペロブスカイ
ト型化合物を、プラズマの活性とCVD反応を利用した
プラズマCVD法によって成膜し、この操作を繰り返し
て基板上に金属電極薄膜層と誘電体薄膜層を積層したも
のを所定の大きさに切断し、その切断面に外部電極を真
空蒸着法またはスパッタリング法またはめっき法または
塗布焼付け法によって形成して積層薄膜コンデンサを製
造するものである。
In order to solve the above-mentioned problems, the present invention is to form a metal electrode thin film layer on a substrate by a vacuum deposition method or a sputtering method, and form a dielectric thin film layer on the substrate by using titanic acid. perovskite oxide and Pb (Mg 1/3 composed mainly of strontium, Nb
2/3 ) A composite perovskite type compound containing O 3 and lead titanate as main components is formed by a plasma CVD method utilizing plasma activation and a CVD reaction, and this operation is repeated to form a metal electrode thin film layer on the substrate. A laminated thin film capacitor is manufactured by cutting a laminate of a dielectric thin film layer and a dielectric thin film into a predetermined size, and forming external electrodes on the cut surface by a vacuum deposition method, a sputtering method, a plating method, or a coating baking method. is there.

【0007】[0007]

【作用】本発明によれば、誘電体薄膜層の成膜にプラズ
マCVD法を用いることにより、膜厚3μm以下で、誘
電特性の良好なチタン酸ストロンチウムやPb(Mg1/
3,Nb2/3)O3−PbTiO3を主成分とする緻密なペ
ロブスカイト型誘電体薄膜が比較的低温で得られる。ま
た、金属電極薄膜層の成膜に真空蒸着法またはスパッタ
リング法を用いることにより、やはり緻密で薄い金属電
極薄膜層が得られる。よって、単位体積あたりの静電容
量が大きくなり、小型化、大容量化に対応した積層薄膜
コンデンサが、バルクの焼成温度よりも低い温度で製造
できることとなる。
According to the present invention, by using the plasma CVD method for forming the dielectric thin film layer, strontium titanate or Pb (Mg 1 / Mg 1 /
3, Nb 2/3) dense perovskite dielectric thin film with O 3 -PbTiO 3 as the main component is relatively obtained at low temperatures. Also, by using the vacuum deposition method or the sputtering method for forming the metal electrode thin film layer, a dense and thin metal electrode thin film layer can be obtained. Therefore, the electrostatic capacitance per unit volume becomes large, and the multilayer thin film capacitor corresponding to miniaturization and large capacity can be manufactured at a temperature lower than the firing temperature of the bulk.

【0008】[0008]

【実施例】【Example】

(実施例1)図1は、本発明の一実施例における積層薄
膜コンデンサの断面の構成の概略図を示すものである。
(Embodiment 1) FIG. 1 is a schematic view showing a cross-sectional structure of a multilayer thin film capacitor in one embodiment of the present invention.

【0009】図1において1はアルミナからなる下地基
板、2、4、6は金属白金からなる金属電極薄膜層、
3、5、7はSrTiO3からなる誘電体薄膜層、8、
9は銀からなる外部電極である。
In FIG. 1, 1 is a base substrate made of alumina, 2, 4, 6 are metal electrode thin film layers made of metallic platinum,
3, 5, 7 are dielectric thin film layers made of SrTiO 3 , 8,
Reference numeral 9 is an external electrode made of silver.

【0010】上記構成要素よりなる積層薄膜コンデンサ
の製造方法は以下の通りである。下地基板1上に、金属
電極薄膜層2を真空蒸着法によって図1(a)に示すよ
うにパターン形成する。その上に、誘電体薄膜層3をプ
ラズマCVD法により形成する。さらにその上に、金属
電極薄膜層4を真空蒸着法によって、図1に示すように
金属電極薄膜層2とはずらしてパターン形成する。さら
にその上に、誘電体薄膜層5をプラズマCVD法により
形成する。さらにその上に、金属電極薄膜層6を真空蒸
着法によって、図1に示すように金属電極薄膜層2と同
じパターンで形成する。さらにその上に、誘電体薄膜層
7をプラズマCVD法により形成する。この操作を繰り
返して、所定の層数を積層した後、図1(b)に示すよ
うに、金属電極薄膜層が一層おきに互い違いの側壁に面
するように所定の大きさに切断する。その切断面に、銀
の外部電極8、9を塗布し、焼き付けて内部の金属電極
薄膜層2、46と外部電極8、9の導通をとる。
A method of manufacturing a laminated thin film capacitor composed of the above constituent elements is as follows. A metal electrode thin film layer 2 is patterned on a base substrate 1 by a vacuum deposition method as shown in FIG. The dielectric thin film layer 3 is formed thereon by the plasma CVD method. Further, a metal electrode thin film layer 4 is patterned thereon by a vacuum vapor deposition method, offset from the metal electrode thin film layer 2 as shown in FIG. Further thereon, the dielectric thin film layer 5 is formed by the plasma CVD method. Further, a metal electrode thin film layer 6 is formed thereon by a vacuum deposition method in the same pattern as the metal electrode thin film layer 2 as shown in FIG. Further thereon, the dielectric thin film layer 7 is formed by the plasma CVD method. After repeating this operation to stack a predetermined number of layers, as shown in FIG. 1B, the metal electrode thin film layers are cut into a predetermined size such that every other metal electrode thin film layer faces alternating side walls. External electrodes 8 and 9 made of silver are applied to the cut surface and baked to establish electrical connection between the internal metal electrode thin film layers 2 and 46 and the external electrodes 8 and 9.

【0011】上記の製造方法のうち、誘電体薄膜層の成
膜方法について以下に説明する。図2は、本発明の一実
施例における積層薄膜コンデンサのうち、誘電体薄膜層
を成膜するのに用いるプラズマCVD装置の概略図を示
すものである。
Among the above manufacturing methods, a method for forming a dielectric thin film layer will be described below. FIG. 2 is a schematic diagram of a plasma CVD apparatus used for forming a dielectric thin film layer in the multilayer thin film capacitor in one embodiment of the present invention.

【0012】図2において構成要素として10は反応チ
ャンバー、11は電極、12は基板回転モーター、13
は基板加熱ヒーター、14はアルミナからなる下地基
板、15は排気系、16は高周波電源(13.56MH
z)である。
In FIG. 2, as components, 10 is a reaction chamber, 11 is an electrode, 12 is a substrate rotation motor, 13
Is a substrate heater, 14 is a base substrate made of alumina, 15 is an exhaust system, 16 is a high frequency power source (13.56 MH)
z).

【0013】一方原料の入った気化容器17、18、1
9、20はバルブ25、26、27、28を介して反応
チャンバー10における電極11の間に開口するパイプ
に接続され、また、気化容器17、18、19、20の
それぞれに導入されたパイプは、バルブ21、22、2
3、24を介してキャリアガスのアルゴンボンベ29に
接続されており、バルブ25、26、27、28の開閉
により原料ガスとキャリアガスの反応チャンバー10内
への導入が制御される。また、酸素ボンベ30は、反応
チャンバー10における電極11の間に開口するパイプ
に接続されている。出発原料にはストロンチウムジピバ
ロイルメタン〔Sr(C111922〕、およびイソプ
ロポキシチタン〔Ti(C37O)4〕を用いた。
On the other hand, vaporization vessels 17, 18 and 1 containing raw materials
9 and 20 are connected to the pipes opened between the electrodes 11 in the reaction chamber 10 through valves 25, 26, 27 and 28, and the pipes introduced into the vaporization vessels 17, 18, 19 and 20 are , Valves 21, 22, 2
It is connected to an argon cylinder 29 for carrier gas through 3, 24, and the introduction of the source gas and the carrier gas into the reaction chamber 10 is controlled by opening and closing the valves 25, 26, 27, 28. Further, the oxygen cylinder 30 is connected to a pipe opened between the electrodes 11 in the reaction chamber 10. Strontium dipivaloyl methane [Sr (C 11 H 19 O 2 ) 2 ] and isopropoxy titanium [Ti (C 3 H 7 O) 4 ] were used as starting materials.

【0014】誘電体薄膜層の成膜方法は以下の通りであ
る。真空蒸着法により予め金属白金の金属電極薄膜層を
パターン形成した下地基板14を、基板加熱ヒーター1
3に取り付け、700℃に加熱し保持した。気化容器1
7にストロンチウムジピバロイルメタンを、気化容器1
8にイソプロポキシチタンを入れ、それぞれ235℃、
50℃に加熱し保持した。反応チャンバー10内を排気
系15によって排気し、基板回転モーター12によっ
て、基板加熱ヒーター13ごと下地基板14を毎分12
0回転の速度で回転した。バルブ17、18、25、2
6を開き、キャリアガス(気化器17、18にそれぞれ
流量25SCCM、5SCCM)により、ストロンチウムジピバ
ロイルメタン、イソプロポキシチタンの蒸気を、反応ガ
スである酸素(流量10SCCM)とともに反応チャンバー
10内に導入し、プラズマ中(電力1.4W/cm2)で
50分間減圧下(0.02Torr)で反応を行い、誘電体
薄膜層であるSrTiO3の薄膜を、金属電極薄膜層を
パターン形成した下地基板14の上に成膜した。これを
冷却後取り出して、再び真空蒸着法で金属電極薄膜層を
誘電体薄膜層上にパターン形成し、その上に上記と同じ
方法で誘電体薄膜層を成膜した。後はこの操作を繰り返
して、金属電極薄膜層と誘電体薄膜層を10層ずつ積み
重ねた。これを、図1に示したように、金属電極薄膜層
が一層おきに互い違いの側壁に面するように基板ごと所
定の大きさに切断し、切断面に銀を塗布して焼付け、外
部電極を形成した。
The method for forming the dielectric thin film layer is as follows. The base substrate 14 on which the metal electrode thin film layer of metal platinum is patterned in advance by the vacuum deposition method is used as the substrate heater 1.
Attached to No. 3, heated to 700 ° C. and held. Vaporization container 1
Vaporization vessel 1 with strontium dipivaloyl methane in 7
Put isopropoxytitanium in 8 and 235 ℃,
It was heated to and held at 50 ° C. The inside of the reaction chamber 10 is evacuated by the exhaust system 15, and the substrate heating motor 12 and the underlying substrate 14 together with the substrate heating heater 13 are evacuated to 12 per minute.
It rotated at a speed of 0 revolutions. Valves 17, 18, 25, 2
6 is opened, and strontium dipivaloylmethane and isopropoxytitanium vapors are introduced into the reaction chamber 10 by the carrier gas (vaporizers 17 and 18 with flow rates of 25 SCCM and 5 SCCM, respectively) together with oxygen as a reaction gas (flow rate of 10 SCCM). Introduced and reacted in plasma (power 1.4 W / cm 2 ) under reduced pressure (0.02 Torr) for 50 minutes to form a dielectric thin film layer of SrTiO 3 on which a metal electrode thin film layer was patterned. A film was formed on the substrate 14. After cooling this, it was taken out, the metal electrode thin film layer was pattern-formed again on the dielectric thin film layer by the vacuum evaporation method, and the dielectric thin film layer was formed thereon by the same method as described above. Thereafter, this operation was repeated to stack 10 metal electrode thin film layers and 10 dielectric thin film layers. As shown in FIG. 1, this is cut into a predetermined size together with the substrate so that every other metal electrode thin film layer faces the alternate side walls, and silver is applied to the cut surface and baked to form an external electrode. Formed.

【0015】また誘電体薄膜層の分析用に、アルミナ基
板上に金属白金を成膜し、その上にSrTiO3の薄膜
を、上記と全く同じ方法で一層だけ成膜した試料を作製
した。
For the analysis of the dielectric thin film layer, a sample was prepared in which metallic platinum was deposited on an alumina substrate and a thin film of SrTiO 3 was deposited thereon by the same method as above.

【0016】得られた積層薄膜コンデンサの誘電体薄膜
層の膜厚は一層あたり2.2μmで、金属電極薄膜層の
膜厚は一層あたり0.06μmであった。この積層薄膜
コンデンサの電極8、9間で電気特性を測定した。誘電
特性は、LCRメーターにより1kHz、1V、室温で
測定すると、比誘電率が190、誘電損失が0.06で
あった。絶縁抵抗は109Ω・cm以上で、直流破壊電
圧は0.7kV/cmであった。また、アルミナ基板上
に金属白金を成膜し、その上にSrTiO3の薄膜を一
層だけ成膜した試料で、X線回折による分析を行ったと
ころ、ペロブスカイト型結晶構造であった。
The thickness of the dielectric thin film layer of the obtained laminated thin film capacitor was 2.2 μm per layer, and the thickness of the metal electrode thin film layer was 0.06 μm per layer. The electrical characteristics were measured between the electrodes 8 and 9 of this laminated thin film capacitor. The dielectric characteristics were 190 kHz and a dielectric loss of 0.06 when measured by an LCR meter at 1 kHz and 1 V at room temperature. The insulation resistance was 10 9 Ω · cm or more, and the DC breakdown voltage was 0.7 kV / cm. A sample in which a platinum metal film was formed on an alumina substrate and a single thin film of SrTiO 3 was formed on the film was analyzed by X-ray diffraction and found to have a perovskite crystal structure.

【0017】なお、上記実施例では、SrとTiの原料
としてストロンチウムジピバロイルメタン、イソプロポ
キシチタンを用いたが、本実施例の製造方法ではこの原
料に限定されることなく、ペロブスカイト型結晶構造の
SrTiO3の薄膜を得ることができ、同等の誘電特性
が得られることを確認した。また、反応ガスとしてN 2
OやH2Oを用いた場合においても酸素を用いた場合と
同等の誘電特性が得られることを確認した。
In the above embodiment, the raw materials of Sr and Ti are used.
As strontium dipivaloyl methane, isopropo
Although xyltitanium was used, this raw material was used in the manufacturing method of this embodiment.
The perovskite type crystal structure is not limited to
SrTiO3It is possible to obtain a thin film of
It was confirmed that In addition, N as a reaction gas 2
O or H2Even when O is used, when oxygen is used
It was confirmed that equivalent dielectric properties were obtained.

【0018】添加物としてバリウム、鉛、ビスマス、カ
ルシウム、マグネシウムを加えた場合においても同様の
結果が得られた。 (実施例2)図3は、本発明の実施例2における積層薄
膜コンデンサの断面の構成の概略図を示すものである。
Similar results were obtained when barium, lead, bismuth, calcium and magnesium were added as additives. (Embodiment 2) FIG. 3 is a schematic view of the cross-sectional structure of a multilayer thin film capacitor according to Embodiment 2 of the present invention.

【0019】図3において構成要素として31はアルミ
ナからなる下地基板、32、34、36は金属白金から
なる金属電極薄膜層、33、35、37はPb(Mg
1/3,Nb2/3)O3−PbTiO3からなる誘電体薄膜
層、38、39は銀からなる外部電極である。
In FIG. 3, 31 is an underlying substrate made of alumina, 32, 34 and 36 are metal electrode thin film layers made of metallic platinum, and 33, 35 and 37 are Pb (Mg).
1/3, Nb 2/3) O 3 consisting -PbTiO 3 dielectric thin film layers, 38 and 39 are external electrodes made of silver.

【0020】この積層薄膜コンデンサの製造方法は以下
の通りである。下地基板31上に金属電極薄膜層32を
真空蒸着法によって、図3(a)に示すようにパターン
形成する。その上に誘電体薄膜層33をプラズマCVD
法により形成する。さらにその上に金属電極薄膜層34
を真空蒸着法によって、図3(a)に示すように金属電
極薄膜層32とはずらしてパターン形成する。さらにそ
の上に誘電体薄膜層35をプラズマCVD法により形成
する。さらにその上に金属電極薄膜層36を真空蒸着法
によって、図3(a)に示すように金属電極薄膜層32
と同じパターンで形成する。さらにその上に誘電体薄膜
層37をプラズマCVD法により形成する。この操作を
繰り返して所定の層数を積層した後、図3(b)に示す
ように、金属電極薄膜層32、34、36が一層おきに
互い違いの側壁に面するように所定の大きさに切断す
る。その切断面に銀の外部電極38、39を塗布し、焼
き付けて内部の金属電極薄膜層32、34、36と外部
電極38、39の導通をとる。
The manufacturing method of this multilayer thin film capacitor is as follows. The metal electrode thin film layer 32 is patterned on the base substrate 31 by a vacuum deposition method as shown in FIG. Plasma CVD of a dielectric thin film layer 33 thereon
It is formed by the method. On top of that, the metal electrode thin film layer 34
Is formed by a vacuum evaporation method so as to be displaced from the metal electrode thin film layer 32 as shown in FIG. 3 (a). Further, a dielectric thin film layer 35 is formed thereon by the plasma CVD method. Further, a metal electrode thin film layer 36 is formed thereon by a vacuum deposition method as shown in FIG.
It is formed in the same pattern as. Further, a dielectric thin film layer 37 is formed thereon by the plasma CVD method. After repeating this operation to stack a predetermined number of layers, as shown in FIG. 3 (b), the metal electrode thin film layers 32, 34, and 36 are made to have a predetermined size so as to face alternating side walls. Disconnect. External electrodes 38 and 39 made of silver are applied to the cut surface and baked to establish electrical continuity between the internal metal electrode thin film layers 32, 34 and 36 and the external electrodes 38 and 39.

【0021】上記の製造方法のうち、誘電体薄膜層3
3、35、37の成膜方法について以下に説明する。出
発原料には鉛ジピバロイルメタン〔Pb(C11
1922〕、イソプロポキシチタン〔Ti(C37O)
4〕、マグネシウムアセチルアセトナート〔Mg(C5
722・H2O〕、ペンタエトキシニオブ〔Nb(OC
255〕を用いた。
Of the above manufacturing methods, the dielectric thin film layer 3
The film forming methods of 3, 35, and 37 will be described below. Lead dipivaloyl methane [Pb (C 11 H
19 O 2 ) 2 ], isopropoxy titanium [Ti (C 3 H 7 O)
4 ], magnesium acetylacetonate [Mg (C 5 H
7 O 2 ) 2 · H 2 O], pentaethoxyniobium [Nb (OC
2 H 5 ) 5 ].

【0022】このものも図2に示すように真空蒸着法に
より予め金属白金の金属電極薄膜層をパターン形成した
下地基板14を、基板加熱ヒーター13に取り付け、7
00℃に加熱し保持した。気化容器17に鉛ジピバロイ
ルメタンを、気化容器18にイソプロポキシチタンを、
気化容器19にマグネシウムアセチルアセトナートを、
気化容器20にペンタエトキシニオブを入れ、それぞれ
145℃、50℃、195℃、60℃に加熱し保持し
た。反応チャンバー10内を排気系15によって排気
し、基板回転モーター12によって、基板加熱ヒーター
は毎分120回転の速度で回転した。バルブ21、2
2、23、24、25、26、27、28を開き、キャ
リアガス(気化器17、18、19、20にそれぞれ流
量35SCCM、15SCCM、10SCCM、8SCCM)により、鉛
ジピバロイルメタン、イソプロポキシチタン、マグネシ
ウムアセチルアセトナート、ペンタエトキシニオブの蒸
気を、反応ガスである酸素(流量30SCCM)とともに反
応チャンバー10内に導入し、プラズマ中(電力1.4
W/cm2)で50分間減圧下(0.03Torr)で反応を
行い、誘電体薄膜層であるPb(Mg1/3,Nb2/3)O
3−PbTiO3の薄膜を、金属電極薄膜層をパターン形
成した下地基板14の上に成膜した。これを冷却後取り
出して、再び真空蒸着法で金属電極薄膜層を誘電体薄膜
層上にパターン形成し、その上に上記と同じ方法で誘電
体薄膜層を成膜した。後はこの操作を繰り返して、金属
電極薄膜層と誘電体薄膜層を10層ずつ積み重ねた。こ
れを、図3に示したように、金属電極薄膜層が一層おき
に互い違いの側壁に面するように基板ごと所定の大きさ
に切断し、切断面に銀を塗布して焼付け、外部電極を形
成した。
As shown in FIG. 2, the base substrate 14 on which a metal electrode thin film layer of platinum metal is patterned in advance by the vacuum deposition method is attached to the substrate heater 13 as shown in FIG.
It was heated to and held at 00 ° C. Lead dipivaloyl methane was added to the vaporization container 17, and isopropoxy titanium was added to the vaporization container 18.
Magnesium acetylacetonate is added to the vaporization container 19,
Pentaethoxyniobium was put in the vaporization container 20 and heated and held at 145 ° C., 50 ° C., 195 ° C. and 60 ° C., respectively. The inside of the reaction chamber 10 was exhausted by the exhaust system 15, and the substrate heating motor 12 rotated the substrate heating heater at a speed of 120 rotations per minute. Valves 21, 2
2, 23, 24, 25, 26, 27, 28 are opened, and lead dipivaloyl methane, isopropoxy is supplied by a carrier gas (flow rate 35 SCCM, 15 SCCM, 10 SCCM, 8 SCCM for vaporizers 17, 18, 19, 20 respectively). Titanium, magnesium acetylacetonate, and pentaethoxyniobium vapor were introduced into the reaction chamber 10 together with oxygen as a reaction gas (flow rate 30 SCCM), and plasma (power 1.4
The reaction is performed under reduced pressure (0.03 Torr) for 50 minutes at W / cm 2 ) to obtain a dielectric thin film layer of Pb (Mg 1/3 , Nb 2/3 ) O.
Of 3 -PbTiO 3 thin film was formed on a base substrate 14 having patterned metal electrode thin film layer. After cooling this, it was taken out, the metal electrode thin film layer was pattern-formed again on the dielectric thin film layer by the vacuum evaporation method, and the dielectric thin film layer was formed thereon by the same method as described above. Thereafter, this operation was repeated to stack 10 metal electrode thin film layers and 10 dielectric thin film layers. As shown in FIG. 3, this is cut into a predetermined size together with the substrate so that every other metal electrode thin film layer faces alternating side walls, and silver is applied to the cut surface and baked to form an external electrode. Formed.

【0023】また誘電体薄膜層の分析用に、アルミナ基
板上に金属白金を成膜し、その上にSrTiO3の薄膜
を、上記と全く同じ方法で一層だけ成膜した試料を作製
した。
Further, for the analysis of the dielectric thin film layer, a sample was prepared in which a platinum metal film was formed on an alumina substrate, and a thin film of SrTiO 3 was formed thereon by the same method as above.

【0024】得られた積層薄膜コンデンサの誘電体薄膜
層の膜厚は一層あたり2.2μmで、金属電極薄膜層の
膜厚は一層あたり0.06μmであった。この積層薄膜
コンデンサの電極8、9間で電気特性を測定した。誘電
特性は、LCRメーターにより1kHz、1V、室温で
測定すると、比誘電率が190、誘電損失が0.06で
あった。絶縁抵抗は109Ω・cm以上で、直流破壊電
圧は0.7kV/cmであった。また、アルミナ基板上
に金属白金を成膜し、その上にPb(Mg1/3,N
2/3)O3−PbTiO3の薄膜を一層だけ成膜した試
料で、X線回折による分析を行ったところ、ペロブスカ
イト型結晶構造であった。X線マイクロアナライザーに
より分析した膜組成はPb{(Mg1/3Nb2/30.7
0.3 }O3であった。
The thickness of the dielectric thin film layer of the obtained laminated thin film capacitor was 2.2 μm per layer, and the thickness of the metal electrode thin film layer was 0.06 μm per layer. The electrical characteristics were measured between the electrodes 8 and 9 of this laminated thin film capacitor. The dielectric characteristics were 190 kHz and a dielectric loss of 0.06 when measured by an LCR meter at 1 kHz and 1 V at room temperature. The insulation resistance was 10 9 Ω · cm or more, and the DC breakdown voltage was 0.7 kV / cm. Also, a metal platinum film is formed on an alumina substrate, and Pb (Mg 1/3 , N
A sample in which only one thin film of b 2/3 ) O 3 -PbTiO 3 was formed was analyzed by X-ray diffraction and found to have a perovskite crystal structure. The film composition analyzed by an X-ray microanalyzer is Pb {(Mg 1/3 Nb 2/3 ) 0.7 T
i 0.3 } O 3 .

【0025】なお、上記実施例では、Pb、Ti、M
g、Nbの原料として鉛ジピバロイルメタン、イソプロ
ポキシチタン、マグネシウムアセチルアセトナート、ペ
ンタエトキシニオブを用いたが、本実施例の製造方法で
はこの原料に限定されることなく、ペロブスカイト型結
晶構造のPb(Mg1/3,Nb2/3)O3−PbTiO3
膜を得ることができ、同等の誘電特性が得られることを
確認した。また、反応ガスとしてN2OやH2Oを用いた
場合においても酸素を用いた場合と同等の誘電特性が得
られることを確認した。
In the above embodiment, Pb, Ti, M
Although lead dipivaloyl methane, isopropoxy titanium, magnesium acetylacetonate, and pentaethoxyniobium were used as the raw materials for g and Nb, the perovskite crystal structure is not limited to these raw materials in the manufacturing method of the present embodiment. It was confirmed that the Pb (Mg 1/3 , Nb 2/3 ) O 3 -PbTiO 3 thin film could be obtained, and that equivalent dielectric characteristics could be obtained. Further, it was confirmed that even when N 2 O or H 2 O was used as the reaction gas, the same dielectric characteristics as when oxygen was used were obtained.

【0026】添加物としてバリウム、ストロンチウム、
ビスマス、カルシウム、ニッケル、亜鉛、コバルト、
鉄、タンタル、タングステンを加えた場合においても同
様の結果が得られた。
As additives, barium, strontium,
Bismuth, calcium, nickel, zinc, cobalt,
Similar results were obtained when iron, tantalum and tungsten were added.

【0027】実施例1および2において、金属電極薄膜
層に、真空蒸着法により白金以外の金属、たとえばパラ
ジウム、パラジウム/銀合金、ニッケル、銅等を用いた
場合や、成膜方法にスパッタリング法を用いた場合で
も、同等の特性を持つ積層薄膜コンデンサの製造が可能
であった。同様に、外部電極の形成に、銀以外の金属を
用いた場合や、塗布焼付け法以外に真空蒸着法またはス
パッタリング法またはめっき法を用いた場合でも、同等
の特性を持つ積層薄膜コンデンサの製造が可能であっ
た。
In Examples 1 and 2, when a metal other than platinum, such as palladium, palladium / silver alloy, nickel, copper, etc., was used for the metal electrode thin film layer by a vacuum deposition method, or a sputtering method was used as a film forming method. Even when used, it was possible to manufacture a multilayer thin film capacitor having equivalent characteristics. Similarly, even when a metal other than silver is used for forming the external electrodes, or when a vacuum deposition method, a sputtering method, or a plating method is used in addition to the coating and baking method, it is possible to manufacture a multilayer thin film capacitor having the same characteristics. It was possible.

【0028】また、実施例1および2においては、誘電
体薄膜層を成膜するプラズマCVD装置と、金属電極薄
膜層を成膜する真空蒸着装置やスパッタリング装置が別
になっていたが、連結した装置を用いて、真空を破らず
に基板を搬送して連続して成膜すれば、さらに容易に製
造することができた。
Further, in Examples 1 and 2, the plasma CVD apparatus for forming the dielectric thin film layer and the vacuum vapor deposition apparatus and the sputtering apparatus for forming the metal electrode thin film layer were separate, but they were connected. It was possible to more easily manufacture the substrate by transporting the substrate without breaking the vacuum and continuously forming a film by using.

【0029】[0029]

【発明の効果】以上の実施例の説明より明らかなよう
に、本発明は誘電体薄膜層の成膜にプラズマCVD法を
用いることによって、金属電極薄膜層上に、誘電特性の
良好なSrTiO3またはPb(Mg1/3,Nb2/3)O3
−PbTiO3の緻密な薄膜が、比較的低温で得られ
る。また、金属電極薄膜層の成膜に真空蒸着法またはス
パッタリング法を用いることによって、やはり緻密で薄
い金属電極薄膜層が得られる。したがって、従来の積層
セラミックコンデンサでのスラリ状のものを積み重ねて
焼成する方法よりも薄くできるため、同じチップ厚みで
も積層数が増え、静電容量が大きくなり、小型化、大容
量化に対応できる。
As is apparent from the above description of the embodiments, the present invention uses the plasma CVD method to form a dielectric thin film layer, so that SrTiO 3 having good dielectric properties can be formed on the metal electrode thin film layer. Or Pb (Mg 1/3 , Nb 2/3 ) O 3
Dense thin film of -PbTiO 3 is obtained at a relatively low temperature. Further, by using the vacuum deposition method or the sputtering method for forming the metal electrode thin film layer, a dense and thin metal electrode thin film layer can be obtained. Therefore, since it can be made thinner than the method of stacking and firing slurry-like ones in the conventional monolithic ceramic capacitor, the number of laminated layers is increased even if the chip thickness is the same, the electrostatic capacity is increased, and it is possible to cope with downsizing and large capacity .

【図面の簡単な説明】[Brief description of drawings]

【図1】本発明の一実施例の積層薄膜コンデンサの断面
の概略図
FIG. 1 is a schematic view of a cross section of a multilayer thin film capacitor according to an embodiment of the present invention.

【図2】本発明の一実施例の積層薄膜コンデンサの誘電
体薄膜層を成膜するために使用するプラズマMOCVD
装置の概略図
FIG. 2 is a plasma MOCVD used for forming a dielectric thin film layer of a multilayer thin film capacitor according to an embodiment of the present invention.
Device schematic

【図3】本発明の他の実施例の積層薄膜コンデンサの断
面の概略図
FIG. 3 is a schematic cross-sectional view of a multilayer thin film capacitor according to another embodiment of the present invention.

【符号の説明】[Explanation of symbols]

1 下地基板 2、4、6 金属電極薄膜層 3、5、7 SrTiO3誘電体薄膜層 8、9 外部電極 1 Base substrate 2, 4, 6 Metal electrode thin film layer 3, 5, 7 SrTiO3 dielectric thin film layer 8, 9 External electrode

───────────────────────────────────────────────────── フロントページの続き (51)Int.Cl.6 識別記号 庁内整理番号 FI 技術表示箇所 H01G 4/30 311 Z 9174−5E (72)発明者 高山 良一 大阪府門真市大字門真1006番地 松下電器 産業株式会社内─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. 6 Identification number Reference number within the agency FI Technical indication location H01G 4/30 311 Z 9174-5E (72) Inventor Ryoichi Takayama 1006 Kadoma, Kadoma, Osaka Prefecture Matsushita Denki Sangyo Co., Ltd.

Claims (5)

【特許請求の範囲】[Claims] 【請求項1】 基板上に、真空蒸着法またはスパッタリ
ング法によりパターン形成した金属電極薄膜層の作製
と、金属化合物の蒸気と反応ガスとの混合ガスを用いた
プラズマCVD法による誘電体薄膜層の作製を交互に繰
り返すことにより金属薄膜層と誘電体薄膜層を積層し、
前記パターン形成した金属電極薄膜層が一層おきに互い
違いの側壁に面するように切断した後、その切断面に外
部電極を真空蒸着法またはスパッタリング法またはめっ
き法または塗布焼付け法により形成することを特徴とす
る積層薄膜コンデンサの製造方法。
1. A metal electrode thin film layer patterned on a substrate by a vacuum deposition method or a sputtering method, and a dielectric thin film layer formed by a plasma CVD method using a mixed gas of a vapor of a metal compound and a reaction gas. The metal thin film layer and the dielectric thin film layer are laminated by alternately repeating the production,
The above-mentioned patterned metal electrode thin film layer is cut so that every other layer faces alternating side walls, and external electrodes are formed on the cut surface by a vacuum deposition method, a sputtering method, a plating method, or a coating baking method. And a method for manufacturing a multilayer thin film capacitor.
【請求項2】 誘電体薄膜層の材料がチタン酸ストロン
チウムを主成分とするペロブスカイト型酸化物であるこ
とを特徴とする請求項1記載の積層薄膜コンデンサの製
造方法。
2. The method for producing a multilayer thin film capacitor according to claim 1, wherein the material of the dielectric thin film layer is a perovskite type oxide containing strontium titanate as a main component.
【請求項3】 誘電体薄膜層の材料がPb(Mg1/3
Nb2/3)O3とチタン酸鉛を主成分とする複合ペロブス
カイト型化合物であることを特徴とする請求項1記載の
積層薄膜コンデンサの製造方法。
3. The material of the dielectric thin film layer is Pb (Mg 1/3 ,
The method for producing a multilayer thin film capacitor according to claim 1, wherein the compound is a complex perovskite type compound containing Nb 2/3 ) O 3 and lead titanate as main components.
【請求項4】 金属化合物としてβ−ジケトン金属錯体
または金属アルコキシドを用いることを特徴とする請求
項1記載の積層薄膜コンデンサの製造方法。
4. The method for producing a multilayer thin film capacitor according to claim 1, wherein a β-diketone metal complex or a metal alkoxide is used as the metal compound.
【請求項5】 反応ガスとして酸素またはN2Oまたは
2Oを用いることを特徴とする請求項1記載の積層薄
膜コンデンサの製造方法。
5. The method for producing a multilayer thin film capacitor according to claim 1, wherein oxygen, N 2 O or H 2 O is used as a reaction gas.
JP25268393A 1993-03-25 1993-10-08 Manufacture of laminated thin-film capacitor Pending JPH07106198A (en)

Priority Applications (5)

Application Number Priority Date Filing Date Title
JP25268393A JPH07106198A (en) 1993-10-08 1993-10-08 Manufacture of laminated thin-film capacitor
EP94104369A EP0617440B1 (en) 1993-03-25 1994-03-19 Laminated thin film capacitor and method for producing the same
DE69401826T DE69401826T2 (en) 1993-03-25 1994-03-19 Thin film capacitor and process for its manufacture
US08/215,816 US5459635A (en) 1993-03-25 1994-03-22 Laminated thin film capacitor and method for producing the same
US08/465,350 US5663089A (en) 1993-03-25 1995-06-05 Method for producing a laminated thin film capacitor

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP25268393A JPH07106198A (en) 1993-10-08 1993-10-08 Manufacture of laminated thin-film capacitor

Publications (1)

Publication Number Publication Date
JPH07106198A true JPH07106198A (en) 1995-04-21

Family

ID=17240794

Family Applications (1)

Application Number Title Priority Date Filing Date
JP25268393A Pending JPH07106198A (en) 1993-03-25 1993-10-08 Manufacture of laminated thin-film capacitor

Country Status (1)

Country Link
JP (1) JPH07106198A (en)

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WO2004044935A1 (en) * 2002-11-12 2004-05-27 Tdk Corporation Capacitor composite circuit element and ic card multilayer capacitor
WO2004061881A1 (en) * 2002-12-27 2004-07-22 Tdk Corporation Thin film capacitor and method for manufacturing same
KR100865760B1 (en) * 2006-03-29 2008-10-28 박영진 Multi layer capacitor device and multi layer varistor device and method for manufacturing the same
JP2012164834A (en) * 2011-02-08 2012-08-30 Canon Inc Lithography apparatus, and method of producing article

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2004044934A1 (en) * 2002-11-12 2004-05-27 Tdk Corporation Thin film capacitor for reducing power supply noise
WO2004044935A1 (en) * 2002-11-12 2004-05-27 Tdk Corporation Capacitor composite circuit element and ic card multilayer capacitor
WO2004061881A1 (en) * 2002-12-27 2004-07-22 Tdk Corporation Thin film capacitor and method for manufacturing same
JPWO2004061881A1 (en) * 2002-12-27 2006-05-18 Tdk株式会社 Thin film capacitor and manufacturing method thereof
KR100865760B1 (en) * 2006-03-29 2008-10-28 박영진 Multi layer capacitor device and multi layer varistor device and method for manufacturing the same
JP2012164834A (en) * 2011-02-08 2012-08-30 Canon Inc Lithography apparatus, and method of producing article

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