TWI234345B - Complementary input dynamic logic - Google Patents

Abstract

A complementary input dynamic logic circuit for evaluating a logic function including an N-channel dynamic circuit, a P-channel dynamic circuit and a pass device. The N-channel dynamic circuit determines a complement of the logic function when a clock signal is high by pulling a first evaluation node low if it evaluates. The P-channel dynamic circuit also determines a complement of the logic function when the clock signal is high by pulling a second evaluation node low if the P-channel dynamic circuit evaluates. The pass device is controlled by the first evaluation node and pulls the second evaluation node low if the N-channel dynamic circuit fails to evaluate. An inverted version of the clock signal may be used to drive the second evaluation node low through the pass device. The N- and P-channel dynamic circuits may be implemented with parallel-coupled devices to achieve high fan-in implementations.

Description

1234345 V. Description of the invention (1) Cross-reference with related applications [0001] This application claims the following US application 60/412, 110, and the application date is September 19, 2002. Priority: Case No. [0 002 ] This application is related to the following U.S. patent applications filed under the same application, and all are: People with the same filing date. Botong's Applicant and Invention Taiwan Application No.

DOCKETNUMBER 92123091 CNTR.2205 92123090 CNTR.2206 Complementary Dynamic Input Logic Architecture for Complex Logic Functions Complementary Input Dynamic Multiplex Decoder Architecture [Technical Field of the Invention] [0 0 0 3] The present invention is related to logic circuits, ^ rb ^ ^ ^ ^ ^ You Cairi's implementation of a fan-in logic function in a dynamic logic drop mine road. Prior art] Line [0004] Based on the requirements for speed, dynamic circuits are often used to implement the total

Page 7 1234345

The source terminal of the element is connected to L0 inputs D1 ~ DN are provided to the n-channel elements N1 ~ NN, respectively, and the point HI is connected to the inverters and the old input terminals, and the output terminal of the inverter element U3 . -[0 0 0 6] In operation, when the CLK signal is at the low level, point I is precharged to the logic high level by the leading element, and the signal Q is changed to the low level by the inverter / driver, and the signal is input at the same time]) 1 ~ 1) \ was built for logical function estimation. When the CLK signal is raised to a high level, the logic function of the logic circuit 104 will be evaluated or not evaluated according to the input states of D1 ~ DN: when the logic circuit i 〇4 is evaluated, all input signals D1 —DN causes all N channel elements N1 ~~ NN to be turned on, and the logic circuit 10 \ drives the point HI to a logic low level through the activated end element NO, and at the same time the output signal Q is driven to a logic high level. When the point H 丨 is driven to the low level, it will remain at the low level until the CLK signal is driven to the low level again. If the logic circuit 104 is not evaluated, the holding circuit 丨 〇6 will Maintain the point Η I at a logic high level, so that the signal q remains low. Therefore, when the CLK signal is at the low level, the q signal is also at the low level; if the logic function is "true", the logic circuit 104 will drive the% number Q to the high level when the CLK signal is at the high level. ^ ° [0007] The logic function implemented by the logic circuit 104 is a multi-input AND function. For evaluation, when the CLK signal is high, the inputs D1 ~ DN must also be high. Level. "And" Logic functions are usually implemented in series with N-channel elements in N logic (as shown in logic circuit 104), and this type of connection in series or stacked N-channel elements will at least There are two factors that cause problems in dynamic circuits: one is between point H and ^ 〇

V. Description of the invention (4) = Khan estimates the length of the loop. This logic circuit evaluates the path: once is also a function of fan-in, and the longer the evaluation path ::: the input signal in the function, but also requires a longer Evaluate two beta estimates relative = circuit speed. Second, because the second component will reduce the function, stacking the components at higher positions for evaluation will make the critical voltage of the components latent instability because of the ^ 1 substrate effect circuit. . ", And change, so that [〇0 0 8] in order to solve the evaluation path _: usually will each stack: Q: logic circuits are layered. One boat and the old, a make, make it No more than four

^ The evaluation path of λλ is a better configuration. 1¾ mu pp #J The solution of the estimation path can be used to limit the function, or the high-level access or logical terms can be reversed into the implementation. And "both functions: one time to reach: the number is decomposed into hierarchically connected low-wide [0009] to implement an inverse" and " function, " " or " path. " When the purpose is only 4 = this fi single tii / Ge logic function solution can of course satisfy the following two; ί However, the above solution is not feasible in complex logic conditions, because the first layer of logic operations "And" results, * or m forcing subsequent ones, or "terms" are successively transformed into, 'and: terms, which means that the problem of n stacking is transferred to the subsequent logical hierarchy. [W0] FIG. 2 is a schematic diagram of a 16-input gate and gate 200, and an exploded view of an exemplary logic circuit 200 for implementing gate 2 and gate 200. First, gate 200 includes 16 input signals ( Represented by A1 ~ A16 respectively) and the solid output signal Q to form a high fan-in " and, a function. A single 1234345 5. Invention description (5) of the '' and π gate 2 0 0 are composed of four low The fan-in layers 2 0 4, 2 0 6, 2 0 8, 2 1 0 are connected in series, and each layer includes one or a plurality of two-input “and” gates. Among them, the first layer 204 includes eight ”and "Gates, each" and "Gates respectively receive input signal pairs from the input signals A1 ~ A16; the second layer 206 contains four" and π gates, each η and "gates respectively correspond to The output of the two “and” gates in the first layer 204 is regarded as its input pair; the third layer 208 includes two “and” gates, each of which “and” the gate respectively The output of the two "and" gates in level 2 〇6 is regarded as its input pair; the fourth level 2 1 0 includes a third level 2 0 8 ,, and a ,, the output of the gate as its input pair. [0 0 11] It is worth noting that each "and" function in the logic circuit 202 has only two inputs', so that the individual evaluation paths are decomposed into a low fan-in configuration. However, decomposing the "high fan-in" and "functions into hierarchical low-fan-in" and "operations is not as expected, because each additional series level of the decomposition function increases the overall circuit delay. By increasing the fan-in of each gate, and gates, the number of “and” gates can be reduced. For example, the number of gates can be reduced to five four-input gates. Each gate has a recommended maximum number of four. However, because each "and" function has a relatively large fan-in and requires two layers, this solution still cannot avoid delay. [Summary of the Invention] [0 0 1 2] According to one of the inventions, it is specific In an embodiment, a complementary input dynamic logic circuit for evaluating a logic function includes an N-channel dynamic circuit, a P-channel dynamic circuit, and a conducting element. The N-channel dynamic circuit

1234345 V. Description of the invention (6) The channel receives one clock, and the dynamic circuit goes to the first-evaluation point. If the channel is evaluated first, then when the clock signal is at a high level, the dynamic circuit of the P channel to the low level J determines the complement of the logic function: the evaluation point. If the P receives the clock signal 'and it is connected to a second evaluation channel dynamic circuit for evaluation, 南 is south on time, then it can be pulled to the high level at the complement of the clock signal function-a supplementary ^ one Khan estimation point, The dynamic circuit disk method of the logical track is determined: it is controlled by the first evaluation point, and the second evaluation point is pulled to a low level when Nit [〇〇 Hi ding evaluation. Stable and Safe, Lo &: 4 ^ Estimation points can be coupled to a buffer or driver to provide two, use, and count results. The buffer may include a logic state of an inverter / driver ^ & inverting output first evaluation point. This embodiment also incorporates a two-phase pulse inverter / driver for outputting the clock signal in inverse and buffering the inverted clock signal. The inverted clock signal can be sent to the conducting element when the N-channel dynamic L circuit cannot be evaluated to pull the > evaluation point to a low level. [0014] The N-channel dynamic circuit may include an n logic circuit to determine a complement of the logic function. In one embodiment, the N logic circuit has a reference point, an output terminal coupled to the first evaluation point, and a plurality of input terminals for receiving a plurality of input signals. The N-channel dynamic circuit can further include a leading component and a trailing component, which can respond to the clock signal so that the N logic circuit can be evaluated. [0015] The P-channel dynamic circuit may include a P logic circuit to determine the complement of the logic function. In one embodiment, the P logic circuit has an output coupled to a reference point of a source electric dust and an output coupled to a second evaluation point.

Page 121234345 5. Description of the invention (Ό terminal, and a plurality of input terminals for receiving a plurality of input signals. Ρ 迢 dynamic circuit may further include a lead element coupled to the second evaluation point at the clock signal is At the low level, the second evaluation point is pre-charged, and the clock signal is at the high level, enabling the ρ logic circuit to perform the evaluation. In the specific embodiment for performing one, and `` logical functions, A p-channel dynamic circuit includes a plurality of N-channel dynamic circuits connected in parallel. A channel N-channel dynamic circuit includes a plurality of N-connected components connected in parallel. [0017] According to a specific embodiment of the present invention, a The method includes: evaluating the first and second evaluation points Chu 1 2 *, and using them to evaluate the logical function of-ρ; short / time at a complementary to pull the second evaluation point to a high level The number of formulas Λ is evaluated, and the other Λ of the logic function is evaluated. 平: Flat complementary " logic circuit cannot be evaluated, then the first standard-conducting element is pulled, and the second evaluation point is pulled to a low level and inverted. Blind r 1 goo can include · Turn and buffer a clock signal to provide an estimate, then ^ Γ bl; and if the complementary logic circuit cannot evaluate :: drive the second estimate with the inverse clock signal via the conducting element. [Embodiment] Specific Applications and conditions ^ ^ are provided to provide a person familiar with the art with which the present invention can be used. However, various pairs of preferred embodiments 1234345

It is shown that the storage circuit 304 is implemented as a half-hold circuit 304, and the storage circuit 304 includes an inverter ui and a p-channel element? 1. Among them, the input of inverter U1 is connected to NT0P, and the output is connected to the gate terminal of the π element; the source terminal of P1 element is connected to VDD, and the drain terminal is connected to NT0p. [0032] The CLK signal is also provided to the gate terminal of another p-channel element μ and the input terminal uco of an inverter / driver. Among them, the source terminal of P2 is connected to VDD, the drain terminal is connected to the second or output evaluation point PTOP, and the inverter / driver UC0 sends the inversion of the pulse signal CLK (that is, CLKB), and its output is connected to the n-channel conduction element. The source terminal of N1 is connected to NTOP and the drain terminal is connected to PTOP. A complement of a logical function used for evaluation by NC〇Mp 3〇2 φ can be implemented using p logic, as shown in PCOMP 30 6. Among them, the reference point of PC〇Mp 306 is connected to VDD, and the output point is connected to ptop point. In addition, PC0MP 30 6 receives N input signals D1 to DN and implements it with "P logic" (meaning using p-channel components), just as NCOMP 302 implements the complement of logic functions with N logic. ρτ〇ρ is provided to the input terminal of an output inverter / driver U2, and the output signal of the output terminal of the inverter / driver U2 is "q". [0 0 3 3] In operation, the initial value of the CLK signal is a low level, so that the TPOP output evaluation point is precharged to a high level via the lead element P2, while the NTOP preliminary evaluation point is precharged to a high level via the lead element ρ0. quasi. The initial value of the output signal Q is a low level. When the CLK signal is at a high level, NCOMp · 302 and PCOMP 306 respectively evaluate the input signal]) 1 ^: 1) ^ and off: 1) 1 to determine or control the status of the NT0P and PT0P points. Both NC〇Mp 3〇2 and pc〇Mp 306 implement the same logical function complement, so when clk is high,

1234345 V. Description of the Invention (ίο) NCOMP 302 and PCOMP 306 are both evaluated or not evaluated. When NCOMP 302 and PCOMP 306 are both, false " a / ('Immediately ° NCOMP 302 and PC0MP 306 are not evaluated), then the logical function itself is true "; when both NCOPM302 and PCOMP 306 are true" When both are evaluated, the logic function itself is "false". [0034] Therefore, when the logic function is "true" and Nc0Mp 2 03 and PCOMP 306 are not evaluated, the hold circuit 3 is used. 4 After the calculation, the NTOP is still sold and maintained at a high level. Since NT0p is still a high-level conducting element N1, it is also maintained in an on or on state. The CLKB signal stored by the inverse υΓ is at a low level, and the signal passes through It is turned on to the low level, so Q becomes the high level, that is to say "True". In this way, when the conducting element N1 is continuously controlled by the implicit, and held in the conducting state, the 'inverter uc〇 passes through a maximum and The short circuit t with the ST element pulls the evaluation point PT〇P to a low level, so the guideline inputs ^ ° These two channel elements refer to the Nit channel element in the inverter function (not shown as Logic makes the Second Medical Classic! 302 and PC0MP 306 are evaluated at the same time, Phase 306: $ 古Huaikou tail. The element N0 is pulled to a low level, and the PTOP is PC0MP ^ λ. The conduction element N1 is frozen or closed, so the PTOP dimension: in the pseudo: bit ... the output signal is kept at a low level, which means a logic function [ 0 0 3 5] Unlike the simple bone face circuit 300, which allows it to emerge in the circuit, the complementary input dynamic logic is different from the domino t; it can be driven to a high level. It is also because of the right W into the alum number When the delay arrives, when the CLK signal 1234345 V. Invention Description (11) is at a high level and NCOMP 302 and PCOMP 306 are both evaluated, the output signal Q can still be pulled back to the low level. Complementary input dynamic logic circuit 30 0 can be regarded as including a complementary N-channel logic circuit 308 related to the first preliminary evaluation point ^ ⑽ and a complementary P-channel logic circuit 310 related to the second output evaluation point ρτορ. Among them, ρτορ is used to The inverter / driver U 2 generates an output signal Q; the complementary n-channel logic circuit 3 08 includes: a leading and trailing element P 0 and N 0, a complementary N logic circuit NCOMP 302 for evaluating a logic function, and a holding circuit 3 〇4; complementary p The channel logic circuit 310 includes: a lead element P2, a complementary P logic circuit PCOMP 306 for evaluating a logic function. If the complementary logic circuits 30.8 and 31 () are both evaluated, NT &OP; is driven low by the circuit 308 Ρτ〇ρ is driven to a high level by circuit 310; when circuits 308 and 31 ° are not evaluated, the conducting element N1 * controlled by MOP passes a temporarily inverted CLK signal ( Generated by the inverter / driver UC0) drives pToop to a low level. [0 036] Another alternative embodiment considers replacing the UCO with an N-channel element, as shown by the dashed connector in FIG. The source terminal of Ν2 is connected to the connection terminal, and the non-terminal is connected to the source terminal of the bypass element N1. The intermediate terminal of Ν2 = = the signal. Therefore, when CLK is high, N2 will be activated and ^ pi 1 will be pulled to the low level. If the input of NC〇Mp 3〇2 and "〇 shenbei 6 is not high level is passed to the signal PT0P ', two stable points of reference will be generated ° == ΡΤ〇P provided by-including the element P lake. Because These components are recommended to be used instead of the virtual connection lines.

Page 17 1234345 V. Description of the invention The holding circuit (as shown in Figure 1) instead of the semi-holding circuit configuration will also be able to provide PTOP-a stable reference point. [0038] Another pull-down replacement element 取代 to replace the inverter uc0, and a weak holding circuit which is proposed to be added and used to provide a stable reference point for PTOP, is used in all the embodiments mentioned later in the present invention And can be described as follows. [0039] FIG. 4 is a schematic diagram of an exemplary complementary input dynamic logic circuit 40 (), which is implemented according to a more specific embodiment of the present invention for implementing one ”and” logic functions. The complementary input dynamic logic circuit 4 00 is substantially similar to the complementary dynamic logic circuit 3 00, and the same component presets have the same reference numerals. For the complementary input dynamic logic circuit 400, the complementary "and / logic circuit 402 is used to replace NCOpM 3002, and the complementary" and "P logic circuit 406 is used to replace PC 〇Mp 306. In other words, except for the part specially used by f for the evaluation of “and” logic functions, complementary input, evil logic circuit 400 is completely the same as complementary dynamic logic circuit 300. It is worth noting that as long as the inverter / driver U2 is replaced with a driver, or a buffer is removed from its inversion function, or another inverter / driver is added to the output (not shown in the figure) (Shown), the complementary dynamic logic circuit 400 can be easily converted into an inverse, and, logic function. [0040] In N logic, the channel elements NΠ ~ ncn are connected in parallel between NTOP and NBOT to implement the complementary "AND" logic circuit 402 and the complement of the AND function. Therefore, when the complement input is provided, the result is the logic of the required D1 ~ DN inputs, and π. Similarly, in p logic, can you use \ ?? Channel elements pci ~ pCN are connected in parallel

1234345 V. Description of the invention (13) Complementary implementation between VDD and PTOP, and 1's logic circuit 406 and another 'and complement of π function. Input signal complements D1 B ~ DNB are provided to n-channel components respectively Gates of NCn ~ NCN (for example, D1 B is provided to the gate of NC1, and D 2 B is provided to the gate of NC 2, and so on), and non-complementary input signals D1 to DN are provided respectively To the gate terminal of the p-channel element pc and PCN (for example, D1 provides the gate to PC 1 and D2 provides the gate to PC2, and so on.) [0 04 1] Complementary input dynamic logic circuit 400 The operation mode is similar to the above-mentioned complementary input dynamic logic circuit 3 〇〇, so you can refer to it. ^ ~ DN Any one or more input signals are "false," or low level (such as logic "〇π), then complementary And logic circuits 40 2 and 406 are evaluated, because "the corresponding D1B ~ DNB input signals are" true ", or a high level (such as logic ^"). In addition, when the complementary type "and "Logic circuits 4 2 and 406 are both evaluated, then the" and "function becomes" "Therefore, when CLK is pulled up to a high level May ^ 'Q output signal becomes" false "(pulled to the low level). Conversely, when all of the 4 6 ^ numbers D1 ~ ⑽ are true, the complementary ‘and’ logic circuits 4 0 2 and / are not evaluated, so the signals of the input signals of D1B to DNB are all evaluated as false. In addition, when the complementary logic and logic circuits 402 and 406 are both ignored, the 0 rule and the function become true, so when the CLK signal is pulled to a high level, the output signal of the main 1 will change. For ,, pseudo, '(that is, high level). What deserves special mention is that the speed of the circuit in Figure 4 is not sensitive to fan-in. Therefore, any reasonable number of electric power can be accepted because it will not slow down the N component. This is due to the evaluation path. Via only two stacked τ · Ν1 and UC elements in UC0 (not labeled).

Page 19, 1234345 V. Description of the invention (14) [0 0 4 2] FIG. 5 is a schematic diagram of an exemplary complementary input dynamic logic circuit 5 0 0 according to another specific embodiment of the present invention, which is used to implement, OR "logic function. Complementary input dynamic logic circuit 5000 is roughly similar to complementary dynamic logic circuit 300 (the same composition is assumed to have the same label). The difference is that NCOPM 302 is complementary, or" N logic circuit 502 is replaced, and PCOMP 306 is replaced with complementary "or" p logic circuit 506. In other words, the complementary input dynamic logic circuit 500 is exactly the same as the complementary dynamic logic circuit 300 except for a portion which is specifically implemented for evaluation of an “OR” logic function. [0043] In N logic, the ΓΗϋN channel elements Nπ ~ KN are connected in series between NTOP and NBOT to implement the complementary " or " N logic circuit 502 and the complement of the " function. The complement of the "or" function is driven by the complement input DIB ~ DNB. Similarly, in p logic, N p-channel elements PC1 ~ PCN can be connected in series between VDD and PT0P to implement complementary "logic circuit 506 and" or "complement of function" and the " The complement of the OR function is driven by the inputs D1 ~ DN. Therefore, the complement dibdnb of the input signal is not provided to the gate terminal of the N-channel element NC and NCN, and ~ DN is provided to the P-channel element Pc and ㈣ respectively. Μ pole terminal and input signal [0044] When all D1 ~ M input signals are "false", or OR logic circuits 502 and 506 are evaluated to make D1B ~ _ input signals "true" In addition, when the value of 50 W is evaluated, the "quote" or "function" is pulled to the south level, and the Q output signal will change to the field level.) Conversely, when one or When multiple input signals are "true", they are complementary

Page 20 1234345 V. Description of the invention (15) The formula “'OR” logic circuits 502 and 506 are not evaluated, so that the corresponding D1B-DNB input signal is " false ". In addition, when the complementary logic circuits "402" and "406" are not evaluated, the "or" function will be, true I, so when the CLK signal is pulled high, the Q output signal will change. "True" (that is, pulled to a high level). [0 0 4 5] The use of complementary input dynamic logic circuit 3 0 0 and its related forms = (for example, complementary input dynamic logic circuit 4 0 0) has several benefits and pitfalls: complementary input dynamic logic circuit 3 0 0 Particularly suitable for high fan = and speaking f: for example for decoding circuits. As discussed previously with reference to FIG. 4, the complementary input dynamic logic circuits 300 and 400m have only a maximum of two components. 1 Compared to what has been done before: : Obviously faster. Compared with the current decomposition technology used to implement high fan-in and function, 400 will be closer to the other than the _ ^^ input dynamic logic circuit 300 and series circuit 500 because they are complemented by the complementary number ^ order The input dynamic logic and p-channel components are stacked and matched, or the logic channels 502 and 506's channel response and delay generation limit the fan-in number. Human [0 0 4 6] FIG. 6 is an exemplary interactive logic circuit for a complex logic function using a complementary input dynamic logic circuit 600J—and complementary == intention. With complementary input, it has similar characteristics, so now it can enter dynamic logic circuit 3 °. In the graphic structure, and each "or" term is equal to 3 to 4 "or" item "is implemented by complementary input dynamic logic: _ high fan-in logic series two" function. System-a complex logical function implemented by the following equations: 2 ° and 6 °°: The complex "and" and "or" functions of the nine formulas:

苐 Page 21, 1234345 V. Description of the invention (16) Q2 D11 · D12 · --D1X + D21 · D22 · --D2Y + ·· + DM1 · DM2 · --DMZ (1) where the dots represent logic '' and "Function, and the plus sign" + π represents a logical π or "function. Equation (1) is a logical π or operation of M multiple inputs π and" terms ", which is usually found in the operations of pipeline processing systems. The first term has X `` And '' items: Dll, D12 ..... D1X; the second item has one, and the "and" items: D21, D22 ..... D2Y; and so on, until the last item or Item M (the last item) has a total of Z, and, and items: DM 1, DM2, ..., DMZ.

[0 047] The complementary input dynamic logic circuit 600 has M complementary N channel dynamic logic circuits, each of which is similar to the complementary v channel logic circuit portion of the complementary input dynamic logic circuit 300. The first complementary ν-channel dynamic logic circuit 602 is used to implement the first "and" term AND1 (that is, D11 • D12 · "· β1χ) 'It includes: a ρ channel with a lead element ρι, a ν channel The end element N10, an N logic block 604 marked with AND1, and a storage circuit S1. Among them, the CLK signal is supplied to the gate terminals of the components ρ0 and Ν1〇; the inverting input signals D11B ~ D1XB (that is, D1XB: D11B) Provided to the individual input terminals of the logic block 604; the source terminal of the lead element? 10 is connected to VDD; if not, the source terminal is connected to the first preliminary evaluation point NT0IM; the source terminal of the end element N1 0 is connected to gn D, Not connected to the first reference point == 1; The output of N logic block 604 is connected to NT0P1 point, and the reference point is N = T1 point. Similar to the configuration method of "" N logic circuit technology, M = contains X The N-channel components configured in parallel, and each N: gate can receive the inverting, track storage circuit S1 from _: dub, which is implemented as a half-hold circuit, and is connected to the storage circuit.

1234345 V. Invention description (17) 304 also includes an inverter U11 and a P-channel element P1 1 connected to VDD and the point NT0p ^^. [0048] Complementary input dynamic logic circuit 600 and other MIMO and the implementation configuration of the complementary N-channel dynamic logic circuit are the same as the first complementary N-channel dynamic logic circuit 602. As shown in the figure, the last (or M) complementary N-channel dynamic logic circuit 606 is used to implement the last "and" item ANM (that is, DM1 · DM2 ···· 〇〇), which is Including ... a ρ channel leading element PM0, an N channel ending element R0, a N logic block 608, and a storage circuit ... Among them, the CLK signal is provided to the gate terminals of the components PM0 and NM0; the inverting input A signal DMZB (ie DMZB: DM1B) is provided to the N logic block 608; the source terminal of the lead element PM0 is connected to VDD, and the drain terminal is connected to the last preliminary evaluation point NTOPM; the source terminal of the end element NM0 is connected to GND, and The drain terminal is connected to the last reference point NBOTM; the output of the N logic block 608 is connected to the NTOPM point, the reference point is connected to the NB0TM point, and the configuration of the logic circuit 402 is similar to that of the two. Contains Z in parallel The configured n-channel components' and the gate terminal of each N-channel component can receive the inverting input signal from MXB: DM1B; the storage circuit is used to implement a half-hold circuit, and it also contains a The inverter UM1 and a P-channel element PM1 connected between VDD and the point NTOPM. [0 049] The M preliminary evaluation points NTTOF ~ NTPOρM are respectively connected to the gate terminals of μ ρ channel elements P21 to P2M, and also connected to the gate terminals of μ ν channel conduction elements N1 1 to NM1. The ρ channel elements ρ? 1 to ρ2M are arranged in series' or connected in a P stack between VDD and the output evaluation point ρτ〇ρ. its

Page 23 1234345

In the figure, the drain terminal of the first P-channel element P21 is connected to the point ρτ〇ρ, and its source 1 end is connected to the drain terminal of the second P-channel element P22 (not shown); the second P-channel element P22 The source terminal of is connected to the drain terminal of the third p-channel element P23 (not shown in the figure); and so on, until the source terminal of the last P-channel element P2M is connected to the channel conducting element Nil ~ NM1 in parallel. ρτ〇ρ and an inverter / driver uc0 output-, and the inverter / driver uc0 provides an inverted clock signal CLKB at the point CLKB. Among them, the drain terminal of each N-channel conducting element Nn ~ NM1 is connected to the PTOP point, and the source terminal is connected to the inverter / driver uc0 to receive clkb. The input of the inverter / driver UCO is used to receive the CLK signal. The call output is the CLKB signal; the input of an output inverter / driver U2 is connected to the PTOP point, and its output provides an output signal 卩. [0050] The operation of the complementary input dynamic logic circuit 600 is as follows. When the CLK signal is at a low level, each preliminary evaluation point NTTOm jTOPM is pulled to a high level by the corresponding lead element ρ0 ～ ρΜ〇, so that each N channel conduction element nu ~ NM1 is activated. The inverter / driver uc〇 pulls the CKLB signal to a high level and charges ρτ〇ρ to a high level in advance, so the initial value of the Q output signal is pulled to a low level. Because N logic blocks --... ~ ANDM are connected in parallel, when CLK signal is pulled to a high level, every N logic block AND1 ~ ANDM evaluates each input signal simultaneously. If one or more N logic blocks AND1 ~ ANDM are not evaluated, the corresponding evaluation points NT0P1 ~ NT0PM will be maintained at a high level due to the operation results of the corresponding storage elements S1 ~ SM, so the corresponding N The channel conducting elements N11 to NM1 are maintained in an on state. When one or more n-channel conducting elements are

Page 24 1234345 V. Description of the invention (19) When the CLKB signal is operating at the low level, the inverter / driver uc0 discharges the ρτορ point to the low level ', causing the Q output signal to become the high level ("true"). This situation occurs when all the inverting inputs of one or more N logic blocks ANDi ~ ANDM are "false" (meaning the non-inverting inputs are all "true"), so the complex logic function is "true" On the other hand, if all N logic blocks ανιη ~ ANDM are evaluated, and all P channel elements P2 and P2M are turned on, the N channel conduction elements N1 1 ~ NM1 will be turned off when pulled to a high level, therefore, Make Q output signal low level (,, pseudo "). This happens when at least one inverting input in the N logic blocks AND1 ~ ANDM is "true", (meaning the corresponding non-inverting input is "false"), so the result of the complex logic function is π Pseudo π. [0051] If the complementary input dynamic logic circuit 30 of FIG. 3 is compared with the complementary input dynamic logic circuit 6 0 0, it is different from implementing complex logic function complements with ρ logic, which focuses on each The viewpoints of the initial evaluation points NTOP1 ~ NTOPM. From the observation of the simple complementary circuit, it can be seen that the required logical operation of the P logic complementary operation is logically regarded as the implementation of the complement of another logical function. Therefore, instead of implementing the logical function complement of each of the parallel P-channel elements π and `` terms '' and `` terms '' with ρ logic, N τ 〇ρ 1 ~ NTOPM points are treated as P-channel elements P2 The input of the P logical stack of P2M is used to determine the state of the output evaluation point PTOP. Therefore, since each of the M complementary P logical blocks (each block represents a "and" item), one can be used. Single The ρ channel elements are replaced, and each of the ρ channel elements P2 and P2M gate ends is driven by the corresponding evaluation point NTPO and NTTOPM, so the configuration result has been significantly simplified.

Page 25 1234345 V. Description of the invention (20)

[0052] The complementary input dynamic logic circuit 600 does not require stacked components in the N-channel evaluation path of the n-logic block-... to ANDM. For example, when the complementary input dynamic logic circuit 300 is configured with n and p-channel evaluation paths, the components need to be stacked to obtain each additional or term of the complex logic function. However, the complementary input dynamic logic circuit 600 is on the p-channel. The maximum number of stacked P-channel elements P2 and P2M in the evaluation path will be limited by leakage issues and matrix effects. As shown in the examples, the number of π or `` terms is limited to about three To four items. For simple circuits, the complementary input dynamic logic circuit 600 is slightly slower than the complementary input dynamic logic circuit 300 'because the N logic blocks AND1 to ANDM are all evaluated before driving PTOP. However, at present, Compared with the technology for implementing complex functions, the method of using complementary input dynamic logic circuit 600 is still an order of magnitude faster than the others.

[0053] FIG. 7 is a simplified block diagram of a complementary input dynamic logic circuit 700 using multiple complementary input dynamic logic circuits 702, 704, and 706. Among them, each of the complementary input dynamic logic circuits having more, and, terms is similar to the complementary input dynamic logic circuit 600. The first logic circuit 7 0 2 is used to process two logic items, including: the first one has a "and" item, that is, D11, D1 2, ..., D1 A; the second has β π and "'Item, that is, D21, D22, ..., D2B. The second logic circuit 704 is used to process the other two logical items, including: the third has C" and "items, that is, D3 1, D32, ..., D3C; the fourth has D ', and "items, that is, D41, D42, ..., D4D. By analogy, the last logic circuit 706 is used to process the last Mth and Nth logical items, including γ and Z "and" items, respectively. For best

Page 26, 1234345 V. Description of the invention (21) Solution, each complementary input dynamic logic circuit 702 ~ 706 only handles two π and "terms. [0054] Complementary input dynamic logic circuits 702 ~ 706 in turn, It is provided to each OR gate 70 8 input terminal to determine the final output value q. As shown in the figure, the logic circuit 702 provides an output Q12 to OR gate 708-the input terminal, and the logic circuit 70. 4 provide ________ irj, wυ ^ ^. Inputs. By analogy, the last logic circuit 706 provides another input that outputs QMN to OR 708. Any person skilled in the art should understand that any number of complementary input dynamic logic circuits can be stacked in parallel, so the “OR” gate 708 can easily pass through as many input terminals as desired. It can be implemented without considering the element matrix effect or delay ^. For example, "or, the gate 708 can be implemented by connecting N-channel elements in parallel (not shown in the figure), and each N-channel element is respectively used to receive a corresponding complementary input dynamic logic circuit 702 The output result of ~ 7〇6. Μ [0055] Complementary input dynamic logic circuit 300 is suitable for combinations that allow logical operation, and this operation combination includes logic, and, Yun Zengshun f Figure 8 is a block diagram of a common multi-satellite decoder, which is based on the sequence of == and the I operation example for two sets of bits: selection and decoding of the selected result. * As shown in the figure, two sets of coded bits = Rui, = [1 · 〇] are provided to the input of the two-bit multiplexer 802. The embodiment shows that each-address has two bits ... As far as the two primary and secondary solutions are concerned, the multiplexing used for address calculation is generally two bits. Select one and select one. 丨 The first multiplexer 802 in Tian M, the SEL number ^ is used for a k-selective input, and the input of the inverter U1 1234345 V. Description of the invention (22) terminal 'The output of the inverted U1 is provided to another selection input of the multiplexer 8 0 2. The state of the SEL signal is used for the coded address bit A. : Call or b [1 · (choose between Π, and the selected bit (represented by the message · · 〇)) is provided to the input of the decoder 804 for the decoder 804 Decode the ENCODED [l · · 〇] signal into the output signal 1)] £ (: 〇]) £;]) [3: ㈧. [0 0 5 6] Anyone skilled in the art should understand that performing bit decoding involves performing logical “AND” operations at the same time to determine each decoding output of 0 £ (: 00 £ 0 [3: 〇] state. For example, {: 1) (: 〇1) 5:]) [〇] The state of the signal is determined by the π and "operations shown in the following equation (2): ENCODED [1] B · ENCODED [0] B (2) Among them, the symbols “•” indicate local ”and“ operation, and the letter π Βπ added after the signal name indicates logical inversion. When receiving the SEL signal, the multiplexer 80 2 selects The A [1: 0] signal is the ENCODEDC1: 〇] signal; otherwise, if the opposite SEL signal is received, the B [1: 0] signal is selected. [0057] FIG. 9 is an exemplary complementary input dynamic multiplex decoding A schematic diagram of the decoder circuit 900, which is used to determine the highest decoding bit or]) ECODED [3] signal decoding status. The complementary input dynamic multiplexing decoder circuit g 〇〇 includes the first and second complementary Input dynamic logic circuits 902 and 906, and they are implemented in the same way as the complementary input dynamic logic circuits 4 previously mentioned. The complementary input dynamic logic circuit 902 is similar to the complementary input dynamic logic circuit 400. The difference is that the conducting element N1 is renamed to N4; the signal points NTOP, NBOT, CLKB, and PTOP are renamed to 〇1 > 1, NBOT1, CLKB1, PT0P1; π and N logic circuit 402 in parallel with three N-channel elements N1, N2, and N3 are implemented as N logic circuit 903; three

Page 1234 34345

P channel elements P1, P2, and P3 are connected in parallel, and, p logic circuit 406, Yumu for P logic circuit 9 Xingyou · Miaoliu + ^ w circuit 4Ub, is used as ^ .. 7 shells for storage The circuit 304 is replaced by the same storage circuit 905, and the inverter / driver U2 is removed or replaced with a two-input i "i" :: U4. In addition, the PTOP1 signal is provided to an input of the inverse gate / driver U4. The dynamic logic circuit 906 is also similar to the complementary input. The difference is that the conducting element νι is renamed; the bluff points NTOP, NB0T, CLKB, and ρτ〇ρ are renewed respectively.

-^, (^^, cut the old / parallel three-channel element and the N logic circuit 402, and implement it as the N logic circuit 907; use three P channel elements P9, ρι, and pu The parallel "and" ρ logic circuit 406 is implemented as the P logic circuit 908; the storage circuit 304 is replaced by the same storage circuit 109; the inverter / driver U2 is removed; the PT0ρ2 signal is provided To the other input of the inverse and logic gate / driver u4.

[0059] As shown in the figure, the complementary input dynamic logic circuits 902 and 906 respectively include corresponding clock inverters / drivers UC * UC2, and are used to invert the CLK signal, and The configuration provides each of the inverted clocks CLKB1 and CLKB2. It is observed that a single clock buffer circuit can be used instead of providing a single buffer and inverting clock signal to the conducting element. [00 6] The gate of the N-channel element N1 receives an inverted SEL signal (or written as SELB). The gates of the N-channel elements N2 and N3 respectively receive an inverse ° A0 and ^ signals (or written as A0B and A1B). Therefore, the logic value that can be obtained by the complementary input dynamic logic circuit 902 is SEL · A0 · A1. N channel yuan \ N6 leisure

1234345 V. Description of the invention (25) Instead, AOB is provided to the gate terminal of P-channel element P4; not A1B but A1 is provided to the gate terminal of N-channel element N3; not A1 but A1B is provided to P-channel element P5 Is not the B0B but B0 is provided to the gate terminal of the ~ channel element N7; not B0 but BOB is provided to the p-channel element? The gate terminal of 10 ′ is not B1B but B1 is provided to the gate terminal of the N-channel element ㈣; instead of B1, B1B is provided to the gate terminal of the p-channel element Pu). [0063] Additional bits can be added to each evaluation path by adding additional N-channel and P-channel components to decode (meaning that they are added between the points NTTOρχ / ΝΒΟΤχ and VDD / PTTOPχ respectively, and the " χ "represents the number of complementary input dynamic logic circuits in parallel.) By increasing the multiplexing function, you can choose from more than two input sets, and the increase is based on the parallel N channel and ρ channel of each evaluation path. In the element, add a parallel solution layer and select a remote input logic combination. "[0064]" and "gate U4" can be implemented roughly in the same way as the complementary input logic circuit 400, but must have sufficient And a non-inverting output. Use the complementary input dynamic logic circuit 4 00 driver / driver U2 to replace with an inverting driver (not shown), or add another inverter to the output ( (Not shown in the figure), it can implement 疋 inverting output. Those skilled in the art should notice that because of its high fan-in, it can use complementary input dynamic logic circuit 4 〇Dangyu, anti • 'and' 'gates to help any number of addresses (for example, more than four). 刖 [0 0 6 5] Figure 1 〇 is a diagram of an exemplary fast dynamic multiplexing decoder, which is Demonstration of four addresses A [3: 〇], B [3: 0], c [3: 〇] and D [3: 〇] through complementary input dynamic logic circuit is faster than 4 speeds =

Page 31 1234345 V. Description of the invention (27), then address A is selected; if SEli is obtained and SEL0 is invalid (via logic circuit 1 004), then address B is selected; if SEL1 is invalid and SEL0 is obtained ( Via logic circuit 1 0 06) 'then address C is selected; if both SEL1 and SEL 0 are invalid (via logic circuit 1 0 0 8), then address D is selected. Therefore, the A address bit is provided to the logic circuit 102, the B address bit is provided to the logic circuit 〇〇04, [The address bit is provided to the logic circuit 1 06, and the D bit Address bits are provided to the logic circuit 1008. Each N-channel and P-channel contains six elements (two select bits and four address bits). The selection of each evaluation path and the special combination of address bits are selected based on the special output bits being decoded. [0 0 68] Edit circuit to achieve multiplex decoding (8 00) fast. The input dynamic logic is decoded from each of the two bits, each of which uses N and M as the amplifier '. So full logic circuit. The logic circuits are based on the embodiments of the invention, and can use complementary input dynamic logic as a dynamic multiplex decoder. In contrast, the complementary input kinetic energy path 900 is more commonly used than the multiplex decoder (such as the multiplex decoder #, according to the example of the present invention, the number of decoding bits of the complementary circuit used by the multiplex decoder can be It is easy to expand and choose from the above decoding input set. In the example of a general full dynamic multiplexing decoder, there are M address bits for N coded bits, resulting in 2 decoded output bits which are integers equal to 1. All The two dynamic multiplexing solutions provided are selected from the decoded bits, and the selected, Yiyao-decoded bits complementary input dynamic logic electrical decoder system contains 2 sets of N complementary inputs :: Each complementary input of the dynamic multiplexing decoder receives the bit of an address and the inverse phase of the address ^ 1234345 V. Description of the invention (28) The special bit system is decoded and provided by mouth To the N-channel evaluation path, the "^ 疋 eight address or its inverse copy will take [00 70] one step further, and the second two-channel evaluation path is enough. It is enough to stop the N code from the N number of bits. Including (where P is greater than 0 and P = 1 or N = 4 digits? When the second example address P = 3; and so on. At each p, register, 5 ~ 8 addresses, the complementary input dynamic logic circuits M —, ^ are provided to each other > — each P channel of the tail circuit Please change your name in a complementary input of the mother, 离. P is open, and the surname is 人 4, and the mother of the circuit is evaluated in the evaluation path of 路径, a, and a or logical state. It is used to select the swing phase # + and the complementary input dynamic logic is used to select the relative decoding circuit 900, in order to select = 2 reason: address. As in the dynamic multi-logic circuit 902, ΠΡΤ ^ is selected in Complementary input dynamics. SEL is provided in the ρ channel evaluation path, = phase SELB is provided in the corresponding request evaluation path ^ In order to select the B address, the complementary input dynamic logic circuit 9 In 6, the logic state of the bit SEL / SELB is reversed. [0 0 7 1] Although the present invention has tried to mention a better way to a certain extent, and the details that can be considered are described in detail, However, other ways or changes can also be considered at the same time. For example, the special logic of an output signal The states may be inverted according to their use in logic circuits. In addition, 'Although the application considered in the present disclosure is a metal oxide semiconductor (MQ g) type element (including complementary MOS elements and the like, such as NMOS and {^ 〇8 电 晶) 'but can also be applied in the same way to those with similar technology and graphic structure, such as bipolar elements or other similar ones. [0 0 7 2] Finally, those skilled in the art should perceive that they can Quick Sen · Page 34 1234345 V. Use of the disclosed concept in the description of the invention (29), use this specific example as the basis for design or modification of the structure, and get the same purpose as the present invention without violating The spirit and scope of the present invention is the same as the scope of the patent application. 1 ·· Page 35 1234345 Brief description of the drawings [0 0 1 8] The cup, features and advantages of the present invention can be better understood by cooperating with the following description and the accompanying drawings. Number diagram [0019] FIG. 1 is a diagram with N inputs to represent, and, a logical function and an implementation corresponding to N inputs, and “Schematic entry of a gate demonstration dynamic circuit [0020] FIG. 2 is a 16 input "and" schematic diagram, and an implementation of the "input and" brake non-standard logic circuit exploded view. [0 0 2 1] Figure 3 is a schematic diagram of a complement input dynamic logic circuit according to the present invention. Fig. 4 shows an example of a pillow circuit [0 022]. Fig. 4 is a schematic diagram of a circuit that is more specifically used according to an embodiment of the "logic function" and "logic function" of the present invention. Bei Zuo's exemplary complementary input dynamic logic [0 023] FIG. 5 is a schematic diagram of another specific and practical implementation of the logical function embodiment according to the present one. 〇〇2 4] FIG. 6 is an exemplary complementation according to an embodiment of the present function a and another is used to implement a complex logic. [0025] FIG. 7 is a schematic diagram of a complementary " dry-wheel-in dynamic logic circuit. , Is used to implement a simplified block with a large number of ", don't, enter a dynamic logic circuit and its way is through a complex logic function containing ^ and 'logical terms, and each complementary input dynamic logic ^ Complementary input dynamic logic circuit. The input dynamic logic circuit is similar to the complementary circuit of Figure 6. [0026] Figure 8 is a common multiplexing sequence commonly used in pipeline systems. Used to illustrate calculation examples for two sets of addresses

Claims (1)

1234345 The scope of the patent application is a way to evaluate a logic function, which includes: Shan Tan's complementary input dynamic logic electrical-n-channel dynamic circuit, receiving-ambiguity-evaluation point, if the N-channel kinetic energy circuit] Coupling to the -th clock signal saying that the ancient & quasi-sun ^ road is evaluated, then it can decide at this standard to pull the first evaluation point to a low complement of the K-side logical function; a P channel Dynamic circuit, receiving $%-Cicada sighs 4 clock signals and is coupled to a first 4 evaluation point. If the P channel moves away from the main port and the circuit is evaluated, it is not necessary. When the pulse signal is at a high level, the complement of the logic function is determined by the dagger and the quaternary; and the q-bit description element is controlled by the first evaluation point and cannot be entered in the N-channel dynamic circuit. When s is estimated, the second evaluation point is pulled to a low level. 02. As the complementary input dynamic logic circuit of item 1 of the patent claim, the N-channel dynamic circuit in i includes: 〃 an N logic circuit. To determine the complement of the logic function, the n logic circuit has A reference point, an output terminal coupled to the first evaluation point, and a plurality of input terminals for receiving a plurality of input signals; a leading το component receives the clock signal and is coupled to the first evaluation point , When the clock signal is at a low level, charge the first evaluation point in advance; and a ending element that receives the clock signal and is coupled to the reference point of the N logic circuit, wherein the leading element and the ending element can return It should be a clock signal. 1234345 VI. Scope of patent application Enable the N logic circuit to be evaluated. 3 · If you apply for the patent, the second annoying stone in the 4th, the upper, and the middle: the student's complementary input dynamic logic circuit, the leading element sentence today—p fuyi ^ ^ ^ ^ followed by β pulse A gate and a drain coupled to the 3rd Khan estimation point; and the tail element in the source i includes a channel element, which has a gate and a coupling of a 1-to-4 clock signal of the ground circuit The drain connected to the reference point of the N logic circuit. ^ 4. ΐΓΐ = complementary input dynamic logic circuit around the second term, and more. ，， 路 ， coupled to a source voltage and the first evaluation point to pass through the complementary input dynamic logic circuit / 1 item, the channel dynamic and evil circuits include: logic electric P road logic series; ^ "Electrical know-how" is used to determine a complement of the logical function. The p 4: 2 includes: a reference point connected to a source voltage, • a round-in terminal connected to the first signal; Input points, / head 70 pieces, to receive the clock signal and consume it to the second evaluation point: when the clock signal is low, charge the second evaluation in advance to evaluate the clock signal as high On time, enable the complementary turn-in dynamic logic circuit in item 5 of the P logic circuit in the P logic circuit. The bean head element includes a -P channel element, which has 4 to a source. Page 1234345 Scope of patent application It is connected to the source of the voltage alone, a gate to receive the clock signal, and a drain of a bismuth evaluation point. For example, the complementary input dynamic logic circuit of item 1 of the patent application scope includes: 'a more inverter / driver' has a terminal for receiving the clock signal 'and an output terminal for providing an inverted clock signal; and Then, the conduction element includes an N-channel conduction element, which has a gate to the first evaluation point, a coupling to the second evaluation point, a connection, and a light connection to the output of the inverter / driver. End source. Pole 8. The complementary input dynamic logic circuit according to item 1 of the patent application scope includes an output inverter / driver having an input terminal coupled to the second evaluation point and an output terminal to provide the logic function. One result x. 9 · If the complementary input dynamic logic circuit of item 1 of the patent application scope, wherein the N-channel dynamic circuit uses an n-channel element to determine one "and the logic function is a complement, and wherein the P-channel dynamic circuit uses a p-channel The element is a complement of a logical function. 1 0 · = Complementary input dynamic logic circuit of item 9 of Shenyan's patent scope, the I · The P-channel dynamic circuit includes a plurality of 70 connected in parallel, each of these P-channel components has a source and a A drain, between a source voltage and the second evaluation point, and having a gate for receiving a corresponding one of a plurality of input signals; and wherein the N-channel dynamic circuit includes a plurality of parallel-connected, channel elements, Each of the N-channel elements has a drain and a source Page 41 1234345 VI Application Patent Range A pole is connected between the first evaluation point and a reference point, and has a question mark for receiving the inverted signal of the corresponding one of the input signals. . 11 · If the complementary input dynamic logic circuit of item No. 丨 0 of the patent application scope, wherein the N channel dynamic circuit further includes a first P channel head element, which has a gate for receiving the clock signal, a coupling A source to a source voltage, and a drain coupled to the first evaluation point; the N-channel end element has a gate that receives the clock signal, a grounded source, and a coupling to the A drain of the reference point; and a holding circuit coupled to the first evaluation point. 12. The complementary input dynamic logic circuit according to item u of the patent application scope, further comprising: a terminal: a driver having an input for receiving the clock signal and an output terminal for an inverted clock signal; and two the The conducting element includes an N-channel conducting element, which is connected to the pole between the first evaluation point, the eighteenth and eighth terminals, and a rubbish—the drain coupled to the second evaluation point is transferred to the inverter. The source of the driver is the source of the P channel. 勺 雷 路 #spoon source of the dog / dog out of the source; Source two: connect to the second evaluation point == pressure evaluation point, and: -The round-in terminal is coupled to the-output terminal to provide one of the results of the logical function. Page 42 1234345 ------- VI. Patent Application Scope I3 · A method for evaluating a complex dynamic logical function, · When the first and second evaluation points are pre-charged to the high-level system circuit for evaluation, use this to evaluate the logic ^, and at the same time when a second evaluation point is pulled to the high-level pan-p logic circuit for evaluation, Use it to evaluate the logical interaction: the complement; and, 铒Another number of 'is pulled through the second point to evaluate if the N complementary logic circuit can not be assessed by an assessment of one conduction element control point, the first - the low level. 14 · The method according to item 13 of the scope of patent application, further comprising: implementing a complementary n logic by connecting a plurality of N-channel elements in parallel between the first evaluation point and a reference point Providing a N-channel end element between the reference point of the complementary N logic circuit and the ground, and controlling the end element with a clock signal to couple a plurality of P-channel elements in parallel to the first Between the two evaluation points and a source voltage, the complementary P logic circuit is implemented. 15. If the method of item 13 of the scope of patent application, further includes: inverting and buffering a clock signal to provide an inverted clock signal; and if the complementary N logic circuit cannot be evaluated, pass the The device is turned on, and the second evaluation point is driven by the inverted clock signal. 16. The method as described in item 13 of the scope of patent application, further including if the complementary% logic Page 43 1234345 Page 44