1234230 0272()t\vfl.doc/006 修正日期 92.9.4 玖、發明說明： 本發明是有關於一種介層窗（Vm)的製造方法，且 特別是有關於一種可改善介層窗污染（Poisoned Via)之 介層窗的製造方法。 在超大型積體電路（VLSI)的製程上，可以在1〜2平 方公分面積的矽表面上配置數量多達數十萬的電晶體。並 且，爲了增加積體電路的積集度，將提高連接各個電晶體 或是其他元件的金屬線之密度。所以，以往單一金屬層的 設計，將無法完成整個積體電路的連線工作，兩層以上的 金屬層設計，便逐漸的成爲許多積體電路所必需採用的方 式。因此在金屬層之間須以內金屬介電層（Inter-metal Delectnc)力口以隔離，以避免元件之間產生非預期性的導 通，並在內金屬介電層中形成介層窗，接著覆蓋導電材料 以形成導線，在半導體工業上稱之爲插塞（Plug)，用來 連接上下兩層金屬層。 然多重金屬層的製作需要非常平坦的介電層，而旋塗 式玻璃（Spm-On-Glass，S0G)製程是一種常用的平坦化 技術，此外SOG的溝塡能力（Gap FH1)亦非常好。 第1A圖至第1B圖所示，係繪示習知一種介層窗的 製造流程剖面圖。 請參照第1A圖，首先提供一半導體基底10，並在其 上形成一已定義的金屬層12，金屬層12以K的M0S兀件 未繪示出。金屬層12的定義比如以傳統的微影蝕刻製程 進行，並同時形成開口 Π，接著於整個半導體基底10表 1234230 ()272()t\vfl.doc/006 修正日期 92.9.4 面形成一層與金屬層12共形的襯氧化層15。之後，例如 使用塗佈法（Coating)形成一層SOG層16塡入開口 13 並覆蓋襯氧化層1 5。 之後在S0G層16上形成一層覆頂氧化層（Cap Oxide Layer) 18，其形成方法是電漿增強化學氣相沈積（PECVD) 法，當沈積完覆頂氧化層18後，須經平坦化製程，比如 化學機械硏磨（CMP)法，以提供全面性平坦的覆頂氧化 層18 〇 當進行完平坦化製程後，於覆頂氧化層18上形成一 層光阻層20，此光阻層20已定義出開口 14，此開口 14 是做爲後續形成介層窗之用。 接著請參照第1B圖，利用完成定義的光阻層20當罩 幕（Mask)，依序蝕刻覆頂氧化層18、SOG層16和襯氧 化層15，並以金屬層12爲蝕刻終止層（Etchmg Stop Layer)，使形成覆頂氧化層18a、SOG層16a和襯氧化層 15a，以及介層窗24。 之後須將光阻層20去除，但習知在利用氧電漿 (Oxygen Plasma)進行蝕刻（Ashing)，用以移除光阻的 過程中，S0G 的有機官能基（Organic Functional Group) 部份會被氧化（Oxidize)，所發生的反應如下：1234230 0272 () t \ vfl.doc / 006 Revision date 92.9.4 (ii) Description of the invention: The present invention relates to a method for manufacturing a via window (Vm), and in particular to a method for improving the pollution of via windows ( Poisoned Via). On the VLSI process, hundreds of thousands of transistors can be placed on a silicon surface with an area of 1 to 2 cm2. In addition, in order to increase the integration degree of the integrated circuit, the density of metal wires connecting various transistors or other components will be increased. Therefore, in the past, the design of a single metal layer could not complete the connection of the entire integrated circuit. The design of two or more metal layers has gradually become a necessary method for many integrated circuits. Therefore, the inter-metal dielectric layer (Inter-metal Delectnc) must be used to isolate between the metal layers to avoid unintended conduction between the components, and a dielectric window is formed in the inner metal dielectric layer, which is then covered. The conductive material is used to form a wire, which is called a plug in the semiconductor industry, and is used to connect the upper and lower metal layers. However, the fabrication of multiple metal layers requires a very flat dielectric layer, and the spin-on-glass (S0G) process is a commonly used planarization technology. In addition, the SOG trench capability (Gap FH1) is also very good. . 1A to 1B are cross-sectional views showing a manufacturing process of a conventional interlayer window. Referring to FIG. 1A, a semiconductor substrate 10 is first provided, and a defined metal layer 12 is formed thereon. The metal layer 12 is not shown in K MOS elements. The definition of the metal layer 12 is, for example, performed by a conventional lithographic etching process, and an opening Π is formed at the same time. Then, the entire semiconductor substrate 10 is shown in Table 1234230 () 272 () t \ vfl.doc / 006. The metal layer 12 is conformally lined with an oxide layer 15. After that, a coating method (Coating) is used to form a SOG layer 16 into the opening 13 and cover the lining oxide layer 15. A cap oxide layer 18 is then formed on the SOG layer 16 by a plasma enhanced chemical vapor deposition (PECVD) method. After the cap oxide layer 18 is deposited, it must undergo a planarization process. For example, a chemical mechanical honing (CMP) method is used to provide a comprehensive flat top oxide layer 18. After the planarization process is completed, a photoresist layer 20 is formed on the top oxide layer 18, and the photoresist layer 20 An opening 14 has been defined, and this opening 14 is used for the subsequent formation of a via window. Next, referring to FIG. 1B, the photoresist layer 20 defined as the mask is used to sequentially etch the top oxide layer 18, the SOG layer 16 and the liner oxide layer 15, and the metal layer 12 is used as the etching stop layer ( Etchmg Stop Layer), so that the top oxide layer 18a, the SOG layer 16a, the liner oxide layer 15a, and the via window 24 are formed. After that, the photoresist layer 20 must be removed, but it is known that during the process of using Ash Plasma to etch to remove the photoresist, the organic functional group part of SOG will After being oxidized (Oxidize), the following reactions occur:
Si-R + 〇2 Si-OH + H20个 + C02个 （未平衡） 其中Si-R代表S0G的結構，R代表S0G的有機官能基， 因此C02的散逸會使S0G層16a變得較具多孔性 (Porous)，且會造成S0G層16a體積的縮減，另外，反 1234230 02720twfl.doc/006 修正日期 92.9.4 應產生的水氣也會容易滯留於SOG層16a中。因而在後 續金屬化製程（Metallization Process)期間，SOG 層 16a 所吸收水氣會被釋放，導致介層窗污染，使得金屬的沈積 不易進行，而造成非預期的斷路情形發生。 爲了改善介層窗污染的情形，習知改善介層窗污染的 方法有 Furusawa 等氏於 “Extended Abstracts of the 1996 International Conference on Solid State Devices and Materials” pp. 145-147 中發表的 “Reliability of Low-Parasitic-Capacitance Multievel Interconnection Using Surface-Densified Low-ε Organic Spin-on Glass”，提出在 低壓下利用氧反應離子蝕刻（Oxygen-Reactwe-Ion· Etchmg)，於介層窗所暴露出之SOG的表面形成一薄且 緻密的保護層。 1997年Kwon等氏於“Planar 97” ρρ· 1-5中發表的 “Prevention of 02 Plasma Damage on Siloxane SOG by Applying E-beam Curing”，提出利用電子束固化（E-beam Curing)，來降低氧電漿對介層窗的污染。1994年Wang 等氏於 “VMIC” pp. 10卜107 中發表的 “A Study of Plasma Treatments on Siloxane SOG”，提出利用氬（Ar)電獎來 強化（Strengthen) SOG薄膜。這些改善的方法是降低氧 電漿對介層窗污染的影響，但僅能降低介層窗污染的問 題。 因此本發明的第'-目的，就是在提供…種介層窗的製 造方法，以避免介層窗污染及其所衍生的問題， 1234230 02720t\\fl.doc/006 修正日期 92.9.4 本發明的第二目的，在提供一種介層窗的製造方法， 以簡化製程，並降低成本。 爲達成本發明之上述目的，一種介層窗的製造方法， 包括：利用阻障層做爲介層窗的蝕刻罩幕，而於使用光阻 完成阻障層的定義後，採用傳統氧電漿製程將光阻剝除。 此時，做爲內金屬介電層的SOG材質，並不會暴露於氧 電漿的環境中，因此可以有效避免介層窗污染的情形發 生。此外所選用阻障層並非高介電常數（Hlgh Dwlectnc Constant)材質，因此完成介層窗的蝕刻後，不須將做爲 蝕刻罩幕之用的阻障層剝除，而可直接繼續後續金屬化的 製程，因此可以簡化製程，並降低成本。 爲讓本發明之上述和其他目的、特徵、和優點能更明 顯易懂，下文特舉一較佳實施例，並配合所附圖式，作詳 細說明如下： 圖式之簡單說明： 第1A圖至第1B圖，係顯示習知一種介層窗的製造 流程剖面圖；以及 第2A圖至第2C圖係顯示根據本發明一較佳實施例 之一種介層窗的製造流程剖面圖。 其中，各圖標號與構件名稱之關係如下： 10、100 半導體基底 12、 102 金屬層 13、 14、105、103 開匚丨 15、15a 襯氧化層 1234230 02720tvvfl doc/006 修正日期 92.9.4 16 、 16a 、 106 、 106a S0G層 18 、 18a 、 108 、 108a 覆頂氧化層 20 、 112 光阻層 24 、 114 介層窗 101 抗反射塗佈層 104 、 104a 襯氧化層 110 、 110a 阻障層 實施例 第2A圖至第2C圖所示，爲根據本發明一較佳實施 例之一種介層窗的製造流程剖面圖。 首先請參照第2A圖，首先提供一半導體基底100， 並在其上形成一已定義的金屬層102，金屬層102以下的 MOS元件未繪示出。金屬層102的定義比如以傳統的微影 蝕刻製程進行，並同時形成開口 1〇5。金屬層102的材質 比如是錫銅（AlCu)。此外，金屬層102的上方更包括形 成一薄層抗反射塗佈（Arid-reflection Coating, ARC)層 101，其材質比如是氮化鈦（TiN)。 之後於整個半導體基底〗〇〇結構的表面形成一層襯氧 化（Liner Oxide)層104,其較佳的材質是氧化矽，厚度 約爲500〜1500A，較佳的形成方法是電漿增強化學氣相沈 積法。襯氧化層104直接覆蓋於金屬層102和抗反射塗佈 層101的表面，其目的是爲了提供高品質的附著性 (Adhesion)及絕緣性。 接著於襯氧化層104上方利用習知的方法塗佈一層 1234230 〇272()twfl.doc/⑻6 修正日期 92.9.4Si-R + 〇2 Si-OH + H20 + C02 (unbalanced) where Si-R represents the structure of SOG and R represents the organic functional group of SOG, so the dissipation of CO2 will make the SOG layer 16a more porous Porous, and will cause a reduction in the volume of the SOG layer 16a. In addition, the anti-1234230 02720twfl.doc / 006 date of revision 92.9.4 will also be easily trapped in the SOG layer 16a. Therefore, during the subsequent metallization process, the water and gas absorbed by the SOG layer 16a will be released, resulting in contamination of the interlayer window, making it difficult for metal deposition to occur, and causing unexpected disconnection situations. In order to improve the pollution of interposer windows, known methods for improving the pollution of interposer windows are "Reliability of Low" published by Furusawa et al. In "Extended Abstracts of the 1996 International Conference on Solid State Devices and Materials" pp. 145-147. -Parasitic-Capacitance Multievel Interconnection Using Surface-Densified Low-ε Organic Spin-on Glass ", proposes the use of oxygen reactive ion etching (Oxygen-Reactwe-Ion · Etchmg) under low pressure on the surface of the SOG exposed by the interlayer window Form a thin and dense protective layer. In 1997, "Prevention of 02 Plasma Damage on Siloxane SOG by Applying E-beam Curing" published by Kwon et al. In "Planar 97" ρρ · 1-5, proposed the use of E-beam Curing to reduce oxygen Contamination of dielectric windows by plasma. In 1994, "A Study of Plasma Treatments on Siloxane SOG", published by Wang et al. In "VMIC" pp. 10 and 107, proposed the use of argon (Ar) electricity award to strengthen (Strengthen) SOG films. These improved methods are to reduce the influence of oxygen plasma on the dielectric window pollution, but can only reduce the problem of dielectric window pollution. Therefore, the first object of the present invention is to provide a method for manufacturing interstitial windows to avoid the pollution of interstitial windows and the problems derived therefrom. 1234230 02720t \\ fl.doc / 006 Date of revision 92.9.4 The present invention A second object of the present invention is to provide a method for manufacturing an interlayer window to simplify the manufacturing process and reduce the cost. In order to achieve the above object of the present invention, a method for manufacturing an interlayer window includes: using a barrier layer as an etching mask of the interlayer window; and after using a photoresist to complete the definition of the barrier layer, a traditional oxygen plasma is used. The process strips the photoresist. At this time, the SOG material as the inner metal dielectric layer will not be exposed to the environment of the oxygen plasma, so the contamination of the dielectric window can be effectively avoided. In addition, the selected barrier layer is not a high dielectric constant (Hlgh Dwlectnc Constant) material, so after the dielectric window is etched, it is not necessary to strip the barrier layer used as an etching mask, but to continue the subsequent metal directly. The manufacturing process can be simplified, and the cost can be reduced. In order to make the above and other objects, features, and advantages of the present invention more comprehensible, a preferred embodiment is described below in detail with the accompanying drawings as follows: Brief description of the drawings: FIG. 1A FIG. 1 to FIG. 1B are cross-sectional views showing a manufacturing process of a conventional interlayer window; and FIGS. 2A to 2C are cross-sectional views showing a manufacturing process of a interlayer window according to a preferred embodiment of the present invention. Among them, the relationship between each icon number and the component name is as follows: 10, 100 semiconductor substrate 12, 102 metal layer 13, 14, 105, 103 opening 丨 15, 15a lining oxide layer 1234230 02720tvvfl doc / 006 date of revision 92.9.4 16 、 16a, 106, 106a S0G layer 18, 18a, 108, 108a top oxide layer 20, 112 photoresist layer 24, 114 interlayer window 101 antireflection coating layer 104, 104a liner oxide layer 110, 110a barrier layer embodiment FIG. 2A to FIG. 2C are cross-sectional views of a manufacturing process of a via window according to a preferred embodiment of the present invention. First, please refer to FIG. 2A. First, a semiconductor substrate 100 is provided, and a defined metal layer 102 is formed thereon. The MOS devices below the metal layer 102 are not shown. The definition of the metal layer 102 is performed, for example, by a conventional lithography process, and an opening 105 is formed at the same time. The material of the metal layer 102 is, for example, tin-copper (AlCu). In addition, the metal layer 102 further includes a thin-layer anti-reflection coating (ARC) layer 101 formed thereon. The material is, for example, titanium nitride (TiN). A linear oxide layer 104 is then formed on the surface of the entire semiconductor substrate. The preferred material is silicon oxide, with a thickness of about 500 to 1500 A. The preferred method of formation is plasma enhanced chemical vapor phase. Deposition method. The lining oxide layer 104 directly covers the surfaces of the metal layer 102 and the anti-reflection coating layer 101, and the purpose thereof is to provide high-quality adhesion and insulation. Next, a layer of 1234230 〇272 () twfl.doc / ⑻6 is applied on the liner oxide layer 104 by a conventional method.
SOG層106,其較佳的厚度約爲4,000〜8,000A。之後在SOG 層106上形成一層覆頂氧化層108，其較佳的材質是氧化 矽，較佳的形成方法是電漿增強化學氣相沈積法。當沈積 完覆頂氧化層108後，須經平坦化製程，較佳的平坦化方 法是化學機械硏磨法，以提供全面性平坦的覆頂氧化層 108,經平坦化製程後之覆頂氧化層108的較佳厚度約爲 2,000〜6,000A。覆頂氧化層108的目的，是爲了提供好的 附著性並確保後續沈積之金屬層與金屬層102之間的絕緣 性。 當進行完平坦化製程後，於覆頂氧化層108上形成一 層阻障層（Barrier Layer) 110，較佳的材質是氮化鈦或鈦， 較佳的厚度是300〜1，500A，其形成方法可以是化學氣相沈 積法或是物理氣相沈積法。阻障層11〇是用於後續介層窗 的蝕刻製程中，做爲蝕刻罩幕之用。接著於阻障層110上 形成一光阻層112，此光阻層112已定義出開口 103，此 開口 103是做爲後續形成介層窗之用。 接著請參照第2B圖，利用完成定義的光阻層112當 罩幕，繼續定義阻障層11〇，使阻障層形成阻障層 110a，其方法比如是非等向性反應離子蝕刻（Anisotropic Reactive Ion Etching)製程，並以覆頂氧化層108爲触刻 終止層。當完成阻障層〗10a的蝕刻後，接著利用氧電漿 將光阻層112剝除。由於此時尙未進行覆頂氧化層108、SOG 層106和襯氧化層104的蝕刻，所以SOG層106未暴露 在氧電漿的環境下，因此可以避免SOG層106與氧產生 1234230 02720t\vfl.doc/006 修正日期 92.9.4 反應，所以可以有效避免習知介層窗污染的情形發生。 接著請參照第2C圖，利用阻障層110a當蝕刻罩幕， 進行鈾刻覆頂氧化層108、SOG層106和襯氧化層104， 使形成覆頂氧化層l〇8a、SOG層106a和襯氧化層104a， 其方法比如是非等向性反應離子蝕刻法，並以抗反射塗佈 層101爲蝕刻終止層，於是形成如第2C圖中之介層窗114, 介層窗114是用以做爲後續形成導電插塞之用。在某些特 定的蝕刻條件下，金屬層102上的抗反射塗佈層101亦會 被去除，此時金屬層102便會直接暴露在介層窗114中。 最後，繼續習知形成導電插塞的製程。而做爲蝕刻罩 幕之用的阻障層ll〇a可以不用剝除，因此可以簡化製程， 並節省成本。接著比如先於整個半導體基底100結構表面 再形成一層薄薄的氮化鈦，之後塡入導電材質比如鎢金屬 於介層窗114中，最後利用化學機械硏磨法使於介層窗114 處形成金屬插塞。 本發明的特徵如下= (1) 本發明提供一種介層窗的製造方法，利用阻障層 做爲蝕刻罩幕，並於進行介層窗的蝕刻製程前，利用氧電 漿將光阻剝除，以避免SOG暴露於氧電漿的環境中，於 是可以避免介層窗污染及其衍生的問題產生。 (2) 本發明於利用阻障層做爲触刻罩幕完成蝕刻製程 後，因所選用阻障層爲金屬材質，不須將附障層剝除，因 此可以簡化製程，並降低成本。 雖然本發明已以一較佳實施例揭露如丨：，然其並非用 1234230 02720t\vfl.doc/006 修正日期 92.9.4 以限定本發明，任何熟習此技藝者，在不脫離本發明之精 神和範圍內，當可作各種之更動與潤飾，因此本發明之保 護範圍當視後附之申請專利範圍所界定者爲準。The SOG layer 106 preferably has a thickness of about 4,000 to 8,000 A. A top oxide layer 108 is then formed on the SOG layer 106. The preferred material is silicon oxide, and the preferred formation method is plasma enhanced chemical vapor deposition. After the top oxide layer 108 is deposited, it must undergo a planarization process. The preferred planarization method is a chemical mechanical honing method to provide a comprehensive flat top oxide layer 108. The top oxide after the planarization process The preferred thickness of the layer 108 is about 2,000 to 6,000 A. The purpose of the capped oxide layer 108 is to provide good adhesion and to ensure the insulation between the metal layer 102 and the metal layer 102 deposited subsequently. After the planarization process is completed, a barrier layer 110 is formed on the top oxide layer 108. The preferred material is titanium nitride or titanium, and the preferred thickness is 300 ~ 1,500A. The method may be a chemical vapor deposition method or a physical vapor deposition method. The barrier layer 110 is used in an etching process of a subsequent interlayer window, and is used as an etching mask. Next, a photoresist layer 112 is formed on the barrier layer 110. The photoresist layer 112 has defined an opening 103, and the opening 103 is used for subsequent formation of a via window. Referring to FIG. 2B, the photoresist layer 112 that has been defined is used as a mask, and the barrier layer 11 is further defined to form the barrier layer 110a. The method is, for example, anisotropic reactive ion etching (Anisotropic Reactive Etching Ion Etching) process, and the top oxide layer 108 is used as the contact stop layer. After the etching of the barrier layer 10a is completed, the photoresist layer 112 is then stripped off with an oxygen plasma. Since the top oxide layer 108, the SOG layer 106, and the liner oxide layer 104 are not etched at this time, the SOG layer 106 is not exposed to the oxygen plasma environment, so the generation of SOG layer 106 and oxygen can be avoided. 1234230 02720t \ vfl .doc / 006 Revision date 92.9.4 response, so it can effectively avoid the situation of the pollution of interposer windows. Next, referring to FIG. 2C, the barrier layer 110a is used as an etching mask to perform uranium etching on the top oxide layer 108, the SOG layer 106, and the liner oxide layer 104, so as to form the top oxide layer 108a, the SOG layer 106a, and the liner The oxide layer 104a is formed by, for example, an anisotropic reactive ion etching method, and the anti-reflection coating layer 101 is used as an etching stopper layer. Thus, a via window 114 as shown in FIG. 2C is formed. For subsequent formation of conductive plugs. Under certain specific etching conditions, the anti-reflection coating layer 101 on the metal layer 102 is also removed, and the metal layer 102 is directly exposed in the interlayer window 114 at this time. Finally, the process of forming a conductive plug is continued. The barrier layer 110a, which is used for etching the mask, does not need to be stripped, so the process can be simplified and costs can be saved. Then, for example, a thin layer of titanium nitride is formed before the entire structure surface of the semiconductor substrate 100, and then a conductive material such as tungsten is deposited in the interlayer window 114, and finally a chemical mechanical honing method is used to form the interlayer window 114. Metal plug. The features of the present invention are as follows: (1) The present invention provides a method for manufacturing an interlayer window, using a barrier layer as an etching mask, and using an oxygen plasma to strip the photoresist before performing the etching process of the interlayer window. In order to avoid the exposure of SOG to the environment of the oxygen plasma, the pollution of the interlayer window and the problems derived therefrom can be avoided. (2) In the present invention, after the etching process is completed by using the barrier layer as a touch engraving mask, the barrier layer is not required to be stripped because the selected barrier layer is made of metal, so the process can be simplified and the cost can be reduced. Although the present invention has been disclosed in a preferred embodiment, such as :, it does not use 1234230 02720t \ vfl.doc / 006 to amend the date to 92.9.4 to limit the present invention. Anyone skilled in this art will not depart from the spirit of the present invention Within the scope and scope, various modifications and retouching can be made, so the scope of protection of the present invention shall be determined by the scope of the appended patent scope.