1233173 玖、發明說明： 【發明所屬之技術領域】 本發明係關於一種半導體封裝結構，特別是一種具有單排錫 球（solder ball)之球柵陣列（ball grid array，BGA)封裝結 構。 【先前技術】 一般而言，積體電路（integrated circuit, 1C)的封裝係可 分為引腳插入型（pin through hole, PTH)與表面黏著型 (surface mount technology, SMT)，由於 SMT 係符合高 I/O 數、高散熱以及封裝尺寸縮小化等要求，所以SMT業已成為1C 封裝技術之主流。此外，SMT主要包含有球柵陣列封裝（ball grid array, BGA)與晶片型封裝（chip scale package, CSP) ’ 球柵陣列封裝與晶片型封裝均是以錫球（solder ball)取代引腳 (lead)，並且晶片型封裝係可視為極小型的球柵陣列封裝。 請參考圖一與圖二，圖一係為習知之一半導體封裝結構之底 視圖，圖二係為圖一所示之半導體封裝結構沿切線2-2，之剖面 示意圖。如圖一與圖二所示，一半導體封裝結構10包含有一具 有一上表面12a與一下表面12b之基板12，一晶片14設置於基 板之上表面12a，複數個焊墊（bonding pad)18設置於基板12之 下表面12b，以及複數個錫球（solder ball)16，分別設置於各個 焊墊18表面。其中，晶片14係為一影像感測晶片（image sensor chip)，例如電荷耗合元件（charge coupled device， CCD)或 CMOS 影像感測元件（CMOS image sensor device)等，並 且晶片14係可利用打線（wiring bonding)或覆晶（flip chip)的 1233173 方式而連接於基板12。此外，半導體封裝結構10係可藉由各個 錫球16電連接至一印刷電路板（printed circuit board, PCB)20，而形成球柵陣列封裝，一般而言，印刷電路板20係包 含有複數個接合墊（未顯示），分別設於各個錫球16與印刷電路 板20之間。 隨著半導體技術的進步，晶片14内的各種電子元件越來越 小，因而使得晶片14的尺寸日趨微小化，也就是說，晶片14的 寬度W與長度L係隨著半導體技術的進展而逐漸縮小。因此，為 了配合晶片16的微小化，半導體封裝結構10便必須減小各錫球 16的尺寸、以及縮小相鄰兩錫球16之間的距離。然而，由於製 程技術等原因，錫球16的尺寸以及各個錫球16之間的距離不能 無限制地縮小，因此當晶片14的尺寸持續地縮小，基板12之下 表面12b最後便只能形成單排的錫球16。不過，如圖三所示，當 半導體封裝結構10藉由單排的錫球16電連接至印刷電路板20 時，單排的錫球16容易使半導體封裝結構10在印刷電路板20 上產生傾斜的情形，因而會導致入射光與影像感測晶片14之間 的入射角偏斜，進而影響感測之精確度。 【發明内容】 本發明的目的是提供一種半導體封裝結構，以解決前述問 題。 依據本發明之目的，本發明的較佳實施例提供一種半導體封 裝結構，半導體封裝結構係設置於一第一基板上，並且半導體封 裝結構包含有一具有一第一表面與一第二表面之第二基板，一設 置於第二基板之第一表面的晶片，複數個設置於第二基板之第二 表面並沿一第一方向排成一列之第一焊球，以及至少一設置於第 1233173 二基板之第二表面的虛設蟬塊 來將第二基板連接至第一基板 封裝結構傾斜。 其中各第一焊球與虛設焊塊係用 並且虛設焊塊係用以避免半導體 由=本發明係於第二基板之第二表面設置至少—虛設焊塊， 因此可有效避免半導體職結構在第—基板上產生傾斜的情形。 【實施方式】 明參考圖四至圖六’圖四係為本發明第一實施例之半導體封 的底^si ’圖五係為圖四所示之半導體封裝結構沿切線5_ 5之J面不思圖’而圖六係為圖四所示之半導體封裝結構沿切 線6 6之剖面不意圖。如圖四與圖五所示，—半導體封裝結構 30包含凡有一具有一上表φ 32a與一下表自32b之基板32，一晶 片34 5又置於基板之上表面32a上，複數個焊墊38設置於基板32 之下表面32b ’以及複數個焊球（bonding ball)36，分別設置於 各個焊塾38表面。其中’晶片34係為—影像感測晶片，例如 CMOS影像感測兀件或電荷耦合元件等，並且晶片34係可利用打 線或覆晶的方式而連接於基板32。此外，晶片34的形狀係為一 長條形’而且各焊球36係沿著晶片34之長邊而排成一列，晶片 34之短邊的寬度係小於1000微米（//m)。另一方面，基板32可 以是一積層式印刷電路板、一共燒陶瓷基板、一薄膜沉積基板或 一玻璃基板。 此外，如圖三與圖五所示，半導體封裝結構30另包含有一 虛設详墊（dummy bonding pad)44，設置於基板32之下表面 32b，以及一虛設焊塊（dummy bonding bar)42，設置於虛設焊墊 44的表面。其中，虛設焊塊42係具有一平坦的表面42a，並且 卢設评塊42的高度h2係約等於各焊球36的高度hi。並且，半導 1233173 體封裝結構30係可藉由各個焊球36以及虛設焊塊42而連接至 一印刷電路板40，形成球栅陣列封裝。一般而言，印刷電路板 ， 40另包含有複數個接合墊（未顯示），分別設於各焊球36以及虛 設焊塊42與印刷電路板4〇之間。另外，各焊球36以及虛設焊 塊42均係由錫金屬所構成。 值得注意的是，由於虛設焊塊42具有一平坦的接觸表面 42a，因此當虛設焊塊42之表面42a連接至印刷電路板40時， 虚没知塊42與印刷電路板4〇之間的接觸係為一面接觸。並且， 又由於虛a又:kf*塊42的長邊（i〇ng side)係約略垂直於著晶片34 之長邊’因此虛設焊塊42係可使半導體封裝結構30在印刷電路 修 板40上維持一平衡狀態，進而避免晶片34在印刷電路板4〇上 產生傾斜的情形。除此之外，虛設焊塊42的形狀、所在位置以 及數量並不限於圖三所示，亦即虛設焊塊42的形狀、所在位置 以及數量係可依據製程需要而改變。因此請參考圖七，圖七係為 本發明第二實施例之半導體封裝結構的底視圖。如圖七所示，一 半導體封裝結構30包含有一基板32，複數個焊球36設置於基板 32之上’以及兩個虛設焊塊42設置於基板32之上並穿插於各焊 球36之間。 此外，請參考圖八至圖十一，圖八至圖十一係為本發明之半 導體封裝結構的製造方法示意圖，並且圖八至圖十一所示之剖面 不意圖係沿著圖四之切線8-8，所繪製。如圖八所示，首先提供 一基板32 ’並藉由複數道薄膜沉積、微影以及蝕刻等製程，於基 . 板32的表面形成複數個焊墊38以及一虛設焊墊44。接著，提供 一金屬製之鋼板46，其中鋼板46具有複數個開口 46a，並且鋼 板46的各個開口 46a係分別對應於各焊墊38以及虛設焊墊44。 然後’如圖九所示，將鋼板46擺放於基板32表面上，並暴露出 各焊塾38以及虛設焊墊44，隨後再將錫膏48塗佈於於鋼板46 11 1233173 之各個開口 46a之内，然後將鋼板34與基板32分離。之後，如 圖十所示，對基板32進行一熱處理製程，以使錫膏48溶化並形 成各個烊球36以及虛設焊塊42。其中，錫膏48的材料可以是含 斜的錫金屬或是不含鉛的錫金屬，其熔點大約是180〜235°C。此 外，在本發明之其它實施例中，鋼板46亦可以用一網板取代 之。 最後，如圖十一所示，利用打線或覆晶的方式而將晶片34 連接至基板32上。除此之外，各焊球36與虛設焊塊42另可利 用電鍍（electroplating)、無電極電鐘（electroless Plating)、蒸鍍（evaporation)、或雷射（laser ball shooter) _ 等方法形成之。 此外，圖四至圖六所示之半導體封裝結構30並非本發明唯 一的實施方式，以下係為本發明之其它實施例，並且為了方便說 明，以下的說明係以相同的標號來表示相同的元件。請參考圖十 二，圖十二係為本發明第三實施例之半導體封裝結構的底視圖。 如圖十二所示，一半導體封裝結構30包含有一基板32，複數個 焊球36a與焊球36b設置於基板32之上，以及至少一個虛設焊 塊42設置於基板32之上，其中各焊球36a與各焊球36b係彼此 籲 交錯設置。 相較於習知技術，本發明係於基板32的下表面32b設置至 少一虛設焊塊42。由於虛設焊塊42係具有一平坦的表面42a， 因此當虚設焊塊42之表面42a連接至印刷電路板40時，虛設焊 -塊42與印刷電路板40之間的接觸係為一面接觸。並且，又由於 虚設焊塊42的長邊係約略垂直於著晶片34之長邊，因此虚設焊 塊42係玎使半導體封裝結構30在印刷電路板40上維持一平衡 狀態，進而避免晶片34在印刷電路板40上產生傾斜的情形。 12 1233173 以上所述僅為本發明之較佳實_，凡依本發 圍所做之均等變化與修倚，皆應屬本發明專利之涵蓋範^。粑 【圖式簡單說明】 圖式之簡單說明 圖:係為習知之一半導體封裝結構之底視圖。 圖二^為圖—所示之半導體封裝結構沿切線2-2，《剖面示意 圖二係為習知具有單排錫球 圖四係為本發明第一實输如夕封K構的剖面示意圖。 圖五係為圖四所示之半導以=封裝結構的底視圖。 圖。打之牛¥體封裝結構沿切線5_5，之剖面示意 圖六^為圖四所示之半導體封裝結構沿切線"，《剖面示意 第實施例之半導體封裝結構的底視圖。 圖。面*、、本發明之半導體封裝結構的製造方法示意 圖十-係為本發明第三實施例之半導體封裝結構的底視圖。 圖式之符號說明 10 12a 14 18 30 半導體封裝結構 上表面 晶片 焊塾 半導體封裝結構 12 12b 16 20 32 基板 下表面 錫球 印刷電路板 基板 13 1233173 32a 34 36a 38 42 44 46a 上表面 32b 下表面 晶片 36 焊球 焊球 36b 焊球 焊墊 40 印刷電路板 虛設焊塊 42a 表面 虛設焊墊 46 鋼板 開口 48 錫膏1233173 发明 Description of the invention: [Technical field to which the invention belongs] The present invention relates to a semiconductor package structure, particularly a ball grid array (BGA) package structure with a single row of solder balls. [Previous technology] Generally, the package system of integrated circuit (1C) can be divided into pin through hole (PTH) and surface mount technology (SMT). High I / O numbers, high heat dissipation, and reduced package size have made SMT the mainstream of 1C packaging technology. In addition, SMT mainly includes ball grid array package (BGA) and chip scale package (CSP). 'Ball grid array package and chip package are solder balls instead of pins ( lead), and the chip-type package can be regarded as a very small ball grid array package. Please refer to FIG. 1 and FIG. 2. FIG. 1 is a bottom view of a conventional semiconductor package structure, and FIG. 2 is a schematic cross-sectional view of the semiconductor package structure shown in FIG. 1 along a tangent line 2-2. As shown in FIGS. 1 and 2, a semiconductor package structure 10 includes a substrate 12 having an upper surface 12a and a lower surface 12b. A wafer 14 is disposed on the upper surface 12a of the substrate, and a plurality of bonding pads 18 are disposed. The lower surface 12 b of the substrate 12 and a plurality of solder balls 16 are respectively disposed on the surface of each solder pad 18. The chip 14 is an image sensor chip, such as a charge coupled device (CCD) or a CMOS image sensor device, and the chip 14 can be wire-bonded. (Wiring bonding) or flip chip 1233173 method is connected to the substrate 12. In addition, the semiconductor package structure 10 can be electrically connected to a printed circuit board (PCB) 20 through each solder ball 16 to form a ball grid array package. Generally speaking, the printed circuit board 20 includes a plurality of Bonding pads (not shown) are respectively provided between the solder balls 16 and the printed circuit board 20. With the advancement of semiconductor technology, various electronic components in the wafer 14 are getting smaller and smaller, so that the size of the wafer 14 is becoming smaller and smaller, that is, the width W and length L of the wafer 14 are gradually increased as the semiconductor technology progresses. Zoom out. Therefore, in order to match the miniaturization of the wafer 16, the semiconductor package structure 10 must reduce the size of each solder ball 16 and the distance between two adjacent solder balls 16. However, due to process technology and other reasons, the size of the solder balls 16 and the distance between the solder balls 16 cannot be reduced indefinitely. Therefore, when the size of the wafer 14 continues to shrink, the bottom surface 12b of the substrate 12 can only form a single unit. Row of solder balls 16. However, as shown in FIG. 3, when the semiconductor package structure 10 is electrically connected to the printed circuit board 20 through a single row of the solder balls 16, the single row of the solder balls 16 easily causes the semiconductor package structure 10 to tilt on the printed circuit board 20. As a result, the incident angle between the incident light and the image sensing chip 14 will be skewed, which will affect the accuracy of the sensing. SUMMARY OF THE INVENTION An object of the present invention is to provide a semiconductor package structure to solve the aforementioned problems. According to the purpose of the present invention, a preferred embodiment of the present invention provides a semiconductor package structure. The semiconductor package structure is disposed on a first substrate, and the semiconductor package structure includes a second substrate having a first surface and a second surface. A substrate, a wafer disposed on a first surface of a second substrate, a plurality of first solder balls disposed on a second surface of the second substrate and arranged in a row along a first direction, and at least one of the 1233173 substrates The dummy surface on the second surface is inclined to connect the second substrate to the first substrate. Each of the first solder ball and the dummy solder bump is used and the dummy solder bump is used to avoid semiconductors. The present invention is provided on the second surface of the second substrate with at least-dummy solder bumps, so the semiconductor structure can be effectively avoided. -The case of tilt on the substrate. [Embodiment] Referring to FIGS. 4-6, FIG. 4 is the bottom of the semiconductor package according to the first embodiment of the present invention, and FIG. 5 is the J-plane of the semiconductor package structure shown in FIG. 4 along the tangent line 5_ 5 FIG. 6 is a cross-sectional view of the semiconductor package structure shown in FIG. As shown in Figures 4 and 5, the semiconductor package structure 30 includes a substrate 32 having an upper table φ 32a and a lower table 32b, and a wafer 34 5 is placed on the upper surface 32a of the substrate. 38 is disposed on the lower surface 32b 'of the substrate 32 and a plurality of bonding balls 36 are respectively disposed on the surface of each solder pad 38. The chip 34 is an image sensing chip, such as a CMOS image sensing element or a charge-coupled device, and the chip 34 is connected to the substrate 32 by wire bonding or flip chip. In addition, the shape of the wafer 34 is a long shape 'and the solder balls 36 are aligned along the long side of the wafer 34, and the width of the short side of the wafer 34 is less than 1000 micrometers (// m). On the other hand, the substrate 32 may be a laminated printed circuit board, a co-fired ceramic substrate, a thin film deposition substrate, or a glass substrate. In addition, as shown in FIGS. 3 and 5, the semiconductor package structure 30 further includes a dummy bonding pad 44 disposed on the lower surface 32b of the substrate 32 and a dummy bonding bar 42. On the surface of the dummy pad 44. Among them, the dummy solder bump 42 has a flat surface 42a, and the height h2 of the dummy solder bump 42 is approximately equal to the height hi of each solder ball 36. In addition, the semiconductor 1233173 body package structure 30 can be connected to a printed circuit board 40 through each solder ball 36 and a dummy solder bump 42 to form a ball grid array package. Generally speaking, the printed circuit board 40 further includes a plurality of bonding pads (not shown), which are respectively disposed between the solder balls 36 and the dummy bumps 42 and the printed circuit board 40. Each of the solder balls 36 and the dummy solder bumps 42 is made of tin metal. It is worth noting that since the dummy solder bump 42 has a flat contact surface 42a, when the surface 42a of the dummy solder bump 42 is connected to the printed circuit board 40, the contact between the dummy bump 42 and the printed circuit board 40 It is one-sided contact. Moreover, since the virtual a and kf * blocks 42 have long sides (i0ng sides) that are approximately perpendicular to the long sides of the wafer 34, the dummy solder bumps 42 allow the semiconductor package structure 30 to be mounted on the printed circuit board 40. An equilibrium state is maintained on the upper surface, thereby avoiding the situation where the wafer 34 is inclined on the printed circuit board 40. In addition, the shape, location, and number of dummy solder bumps 42 are not limited to those shown in FIG. 3, that is, the shape, location, and number of dummy solder bumps 42 can be changed according to process requirements. Therefore, please refer to FIG. 7, which is a bottom view of a semiconductor package structure according to a second embodiment of the present invention. As shown in FIG. 7, a semiconductor package structure 30 includes a substrate 32, a plurality of solder balls 36 are disposed on the substrate 32 ′, and two dummy solder bumps 42 are disposed on the substrate 32 and interposed between the solder balls 36. . In addition, please refer to FIGS. 8 to 11, which are schematic diagrams of a method for manufacturing a semiconductor package structure according to the present invention, and the cross sections shown in FIGS. 8 to 11 are not intended to be along the tangent line of FIG. 4. 8-8, drawn. As shown in FIG. 8, a substrate 32 ′ is first provided, and a plurality of thin film deposition, lithography, and etching processes are used to form a plurality of pads 38 and a dummy pad 44 on the surface of the substrate 32. Next, a metal steel plate 46 is provided. The steel plate 46 has a plurality of openings 46a, and each opening 46a of the steel plate 46 corresponds to each of the pads 38 and the dummy pads 44. Then, as shown in FIG. 9, the steel plate 46 is placed on the surface of the substrate 32, and each solder pad 38 and the dummy pad 44 are exposed. Then, the solder paste 48 is applied to each opening 46a of the steel plate 46 11 1233173. Then, the steel plate 34 is separated from the substrate 32. Thereafter, as shown in FIG. 10, a heat treatment process is performed on the substrate 32 to dissolve the solder paste 48 and form each of the ball 36 and the dummy bump 42. Among them, the material of the solder paste 48 may be oblique tin metal or lead-free tin metal, and its melting point is about 180 ~ 235 ° C. In addition, in other embodiments of the present invention, the steel plate 46 may be replaced by a mesh plate. Finally, as shown in FIG. 11, the wafer 34 is connected to the substrate 32 by wire bonding or flip chip. In addition, each of the solder balls 36 and the dummy solder bumps 42 may be formed by electroplating, electroless plating, evaporation, or laser ball shooter. . In addition, the semiconductor package structure 30 shown in FIGS. 4 to 6 is not the only embodiment of the present invention. The following are other embodiments of the present invention, and for convenience of explanation, the following description uses the same reference numerals to represent the same elements. Please refer to FIG. 12, which is a bottom view of a semiconductor package structure according to a third embodiment of the present invention. As shown in FIG. 12, a semiconductor package structure 30 includes a substrate 32, a plurality of solder balls 36 a and 36 b are disposed on the substrate 32, and at least one dummy solder bump 42 is disposed on the substrate 32. The balls 36a and the solder balls 36b are arranged alternately with each other. Compared with the conventional technology, the present invention is provided with at least one dummy solder bump 42 on the lower surface 32b of the substrate 32. Since the dummy solder bump 42 has a flat surface 42a, when the surface 42a of the dummy solder bump 42 is connected to the printed circuit board 40, the contact between the dummy solder bump 42 and the printed circuit board 40 is one-face contact. In addition, since the long side of the dummy solder bump 42 is approximately perpendicular to the long side of the wafer 34, the dummy solder bump 42 prevents the semiconductor package structure 30 from maintaining a balanced state on the printed circuit board 40, thereby avoiding the wafer. 34 causes a tilt on the printed circuit board 40. 12 1233173 The above is only the best practice of the present invention. Any equal changes and modifications made in accordance with the present invention should be covered by the patent of the present invention ^.粑 [Brief description of the drawings] Brief description of the drawings Figure: This is a bottom view of a conventional semiconductor package structure. Fig. 2 is a diagram showing the semiconductor package structure along the tangent line 2-2. "Schematic cross-section." Fig. 2 is a conventional cross-section diagram with a single row of solder balls. FIG. 5 is a bottom view of the semi-conducting semiconductor package shown in FIG. 4. Illustration. Figure ^ shows the cross section of the semiconductor package structure shown in Figure 4 along the tangent line 5_5, "Bottom view of the semiconductor package structure of the first embodiment shown in section". Illustration. Fig. 10 is a bottom view of a semiconductor package structure according to a third embodiment of the present invention. Description of the symbols 10 12a 14 18 30 Upper surface of the semiconductor package structure Wafer soldering Semiconductor package structure 12 12b 16 20 32 Substrate solder ball printed circuit board substrate 13 1233173 32a 34 36a 38 42 44 46a Upper surface 32b Lower surface wafer 36 Solder ball Solder ball 36b Solder ball pad 40 Printed circuit board dummy pad 42a Surface dummy pad 46 Steel plate opening 48 Solder paste
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