TWI232592B - LOCOS Schottky barrier contact structure and its manufacturing method - Google Patents
LOCOS Schottky barrier contact structure and its manufacturing method Download PDFInfo
- Publication number
- TWI232592B TWI232592B TW93106797A TW93106797A TWI232592B TW I232592 B TWI232592 B TW I232592B TW 93106797 A TW93106797 A TW 93106797A TW 93106797 A TW93106797 A TW 93106797A TW I232592 B TWI232592 B TW I232592B
- Authority
- TW
- Taiwan
- Prior art keywords
- layer
- silicon oxide
- local silicon
- schottky barrier
- patent application
- Prior art date
Links
Landscapes
- Electrodes Of Semiconductors (AREA)
Abstract
Description
1232592 五、發明說明(1) 【發明所屬之技術領域 本發明與一種蕭特基屏障(Schottky barrier)二極體 及其製造方法有關,特別的是與一種局部氧化矽(LOCOS) 蕭特基屏障接觸結構及其製造方法有關。 【先前技術】1232592 V. Description of the invention (1) [Technical field to which the invention belongs The present invention relates to a Schottky barrier diode and a method for manufacturing the same, and in particular to a local silicon oxide (LOCOS) Schottky barrier The contact structure and its manufacturing method are related. [Prior art]
一個蕭特基屏障二極體至少包含一個蕭特基接觸金屬 層形成於一個半導體基板之上係被公認是一種多數載子二 極體且因而作為一個高速交換二極體或一個高頻整流器。 對於作為一個交換功率二極體之用的一種蕭特基屏卩早' 一極 體而言,其主要設計問題均集中於逆向崩潰電壓(VB )、逆 向漏電流(IR )、順向電流(Ιρ )及順向電壓(Vf )。A Schottky barrier diode containing at least one Schottky contact metal layer formed on a semiconductor substrate is recognized as a majority carrier diode and thus acts as a high-speed exchange diode or a high-frequency rectifier. For a Schottky screen used as a switching power diode, its main design problems are concentrated on reverse breakdown voltage (VB), reverse leakage current (IR), and forward current ( Iρ) and forward voltage (Vf).
圖一顯示先前技術之一種蕭特基屏障接觸結構的一個 簡要剖面圖,其中一個p+擴散保護環1 0 5 係透過形成於兩 個成形場氧化物層1 〇2 a之間的一個擴散窗(未圖示)來形成 於一個n-/n+磊晶半導體基板10 1/1 00之一個所設計的表面 部份之内;一個金屬矽化物層1 0 3作為一個蕭特基接觸金 屬層係形成於經由一個成形步階棚玻璃(BSG)層106a所包 圍的該P +擴散保護環1 0 5及一個暴露n - 7 n +蠢晶半導體基 板1 0 1 / 1 0 0的表面之上;一個成形金屬層1 0 4 a係形成於該 成形場氧化物層1 〇 2 a的一部份表面、該成形步階棚玻璃層 106a及該金屬石夕化物層1〇3之上’以及一個为邊金屬層(未Figure 1 shows a schematic cross-sectional view of a Schottky barrier contact structure of the prior art, in which a p + diffusion guard ring 1 0 5 is transmitted through a diffusion window formed between two forming field oxide layers 1 02 a ( (Not shown) is formed in a designed surface portion of an n- / n + epitaxial semiconductor substrate 10 1/1 00; a metal silicide layer 103 is formed as a Schottky contact metal layer system Over the P + diffusion guard ring 105 and a surface exposing an n-7 n + stupid semiconductor substrate 1 0 1/1 0 0 surrounded by a forming step glass (BSG) layer 106a; a The forming metal layer 1 0 4 a is formed on a part of the surface of the forming field oxide layer 10 2 a, the forming step glass layer 106 a and the metal oxide layer 10 3 ′, and one is Edge metal layer (not
第7頁 1232592 五、發明說明(2) 圖示)作為一個歐姆接觸金屬層係形成於該η +半導體基板 1 00 之上。 這裡可以清楚地看到,圖一所示之該蕭特基屏障二極 體的製造需要三個罩幕光阻步驟,其中一個第一罩幕光阻 步驟係用來定義該ρ +擴散保護環的一個擴散窗;一個第二 罩幕光阻步驟係用來去除該成形場氧化物層1 0 2a (未圖示) 及該步階硼玻璃層1 0 6 (未圖示)的一部份來形成該金屬矽 化物層1 0 3 ;以及一個第三罩幕光阻步驟係用來形成該成Page 7 1232592 V. Description of the invention (2) (illustrated as an ohmic contact metal layer) is formed on the n + semiconductor substrate 100. It can be clearly seen here that the fabrication of the Schottky barrier diode shown in Figure 1 requires three mask photoresist steps, one of which is the first mask photoresist step to define the ρ + diffusion protection ring. A diffusion window; a second mask photoresist step is used to remove the forming field oxide layer 10 2a (not shown) and part of the step boro glass layer 10 6 (not shown) To form the metal silicide layer 103; and a third mask photoresist step is used to form the
形金屬層1 0 4a。很明顯地,利用一種溼式蝕刻溶液(例如: 緩衝氫氟酸)來同時去除該成形場氧化物層1 0 2 a 及該步階 石朋玻璃層106而不產生嚴重下部掏空(undercut) 係相當的 困難。相似地,利用非等向乾式蝕刻法來同時去除該成形 場氧化物層1 0 2 a 及該步階硼玻璃層1 0 6 而不產生該ρ + 保 護環及該暴露半導體基板1 0 1 / 1 0 0 的嚴重槽刻係相當不 容易。因此,利用溼式蝕刻法之該擴散窗的寬度必需保持 較大的尺寸(大於或等於1 0微米)而利用非等向乾式蝕刻法 之該P +擴散保護環1 0 5 的接面深度必需保持較深(大於或 等於2微米)。因此,該蕭特基屏障二極體細胞元尺寸將變 大且對於一個指定的崩潰電壓而言,其雜散串聯電阻將增 加0形 金属 层 10 0a. Obviously, a wet etching solution (for example: buffered hydrofluoric acid) is used to remove the forming field oxide layer 1 0 2 a and the step stone glass layer 106 simultaneously without serious undercutting. It was quite difficult. Similarly, a non-isotropic dry etching method is used to remove the forming field oxide layer 1 2 a and the step boro glass layer 1 0 simultaneously without generating the ρ + guard ring and the exposed semiconductor substrate 1 0 1 / The severe groove engraving of 100 is not easy. Therefore, the width of the diffusion window using the wet etching method must be kept large (10 micrometers or more) and the junction depth of the P + diffusion guard ring 1 0 5 using the non-isotropic dry etching method must be Keep it deep (greater than or equal to 2 microns). Therefore, the size of this Schottky barrier diode cell will increase and its stray series resistance will increase by 0 for a specified breakdown voltage.
因此,本發明的一個主要目的係提供一種局部氧化矽 蕭特基屏障接觸結構具有一個凸出(r a i s e d )擴散保護環以 獲得較高的逆向崩潰電壓及較低的順向電壓。 本發明的另一個目的係提供一種局部氧化矽蕭特基屏Therefore, a main object of the present invention is to provide a local silicon oxide Schottky barrier contact structure with a protruding (r a s d) diffusion protection ring to obtain a higher reverse breakdown voltage and a lower forward voltage. Another object of the present invention is to provide a local silicon oxide Schottky screen.
111 國|11 第8頁 1232592 五、發明說明(3) 障接觸結構具有一個較佳的金屬步階覆蓋。 本發明的一個進一步目的係提供一種局部氧化矽蕭特 基屏障接觸結構具有一個最小化的擴散保護環面積及一個 最佳化的細胞元面積。 【發明内容】111 country | 11 Page 8 1232592 V. Description of the invention (3) The barrier contact structure has a better metal step coverage. A further object of the present invention is to provide a locally-oxidized Schottky barrier contact structure having a minimized diffusion guard ring area and an optimized cell area. [Summary of the Invention]
本發明揭示一種局部氧化矽蕭特基屏障接觸結構及其 製造方法。該局部氧化矽蕭特基屏障接觸結構至少包含一 種第一導電型的一個半導體基板具有一個淡摻雜磊晶矽層 形成於一個高摻雜矽基板之上;一種第二導電型的一個凸 出擴散保護環形成於一個外部局部氧化矽場氧化物層及一 個内部局部氧化矽場氧化物層之間;一個凹陷半導體基板 被該凸出擴散保護環所包圍;一個金屬矽化物層形成於該 外部局部氧化矽場氧化物層所包圍的一個半導體表面,包 含該凸出擴散保護環及被該凸出擴散保護環所包圍的該半 導體基板;以及一個成形金屬層形成於該外部局部氧化矽 場氧化物層的一部份表面及該金屬矽化物層之上,其中該 内部局部氧化矽場氧化物層係在完成一個擴散製程以形成 該凸出擴散保護環之後再透過一個罩幕光阻步驟來加予去 除。 本發明之該局部氧化矽蕭特基屏障接觸結構提供該 凸出擴散保護環來消除接面曲率效應對逆向崩潰電壓的影 響、該凹陷半導體基板以形成一個蕭特基屏障接觸來降低The invention discloses a local silicon oxide Schottky barrier contact structure and a manufacturing method thereof. The local silicon oxide Schottky barrier contact structure includes at least a semiconductor substrate of a first conductivity type having a lightly doped epitaxial silicon layer formed on a highly doped silicon substrate; a protrusion of a second conductivity type A diffusion guard ring is formed between an external local silicon oxide field oxide layer and an internal local silicon oxide field oxide layer; a recessed semiconductor substrate is surrounded by the convex diffusion protection ring; a metal silicide layer is formed on the outer portion A semiconductor surface surrounded by a locally oxidized silicon field oxide layer includes the protruding diffusion protection ring and the semiconductor substrate surrounded by the protruding diffusion protection ring; and a formed metal layer is formed on the external local oxidation silicon field to oxidize A part of the surface of the material layer and the metal silicide layer, wherein the internal local silicon field oxide layer is passed through a mask photoresist step after completing a diffusion process to form the protruding diffusion protection ring. Plus to remove. The local silicon oxide Schottky barrier contact structure of the present invention provides the protruding diffusion protection ring to eliminate the influence of the junction curvature effect on the reverse breakdown voltage, and the recessed semiconductor substrate to form a Schottky barrier contact to reduce
第9頁 1232592 五、發明說明(4) 雜散串聯電阻、以及該外部局部氧化矽場氧化物層具有一 個較佳的金屬步階覆蓋。 【實施方式】 現請參見圖二A至圖二G,其中揭示製造本發明之一種 局部氧化矽蕭特基屏障接觸結構的製程步驟及其簡要剖面 圖。Page 9 1232592 V. Description of the invention (4) The stray series resistance and the external local silicon field oxide layer have a better metal step coverage. [Embodiment] Referring now to FIGS. 2A to 2G, the process steps for manufacturing a partially-oxidized Schottky barrier contact structure of silicon oxide according to the present invention and a schematic cross-sectional view thereof are disclosed.
圖二A顯示一個塾(pad)氧化物層202 係形成於一種第 一導電型的一個半導體基板2 01/200之上;接著,一個氮化 矽層2 0 3 係形成於該墊氧化物層2 0 2 之上。該墊氧化物層 2 0 2 係一個熱二氧化矽層在一個乾氧環境下成長於該半導 體基板2 0 1 / 2 0 0 之上且其厚度係介於100埃和5 0 0埃之間。 該氮化矽層2 0 3係藉由低壓化學氣相堆積(LPCVD)法來形成 且其厚度係介於5 0 0埃和1 5 0 0埃之間。該半導體基板2 0 1 / 2 0 0至少包含一個淡摻雜磊晶矽層2 0 1 置於一個高摻雜矽 基板2 0 0之上,其中該淡摻雜磊晶矽層2 0 1之内的摻雜質濃 度係介於1 014/立方公分和1017/立方公分之間而磊晶層厚度 係介於3微米和3 5微米之間,並依所指定的崩潰電壓來決 定;該高摻雜半導體基板2 0 0的摻雜質濃度係介於1 019/立方 公分和5 X 1 02G /立方公分之間,而其厚度係依照晶圓的尺 寸大小來決定。 圖二B顯示一個第一罩幕光阻(PR1 )步驟(未圖示)係用FIG. 2A shows that a pad oxide layer 202 is formed on a semiconductor substrate 2 01/200 of a first conductivity type; then, a silicon nitride layer 2 0 3 is formed on the pad oxide layer. 2 0 2 above. The pad oxide layer 2 0 2 is a thermal silicon dioxide layer grown on the semiconductor substrate 2 0 1/2 0 0 in a dry oxygen environment and has a thickness between 100 angstroms and 50 angstroms. . The silicon nitride layer 230 is formed by a low pressure chemical vapor deposition (LPCVD) method, and its thickness is between 500 angstroms and 150 angstroms. The semiconductor substrate 2 0 1/2 0 0 comprises at least a lightly doped epitaxial silicon layer 2 0 1 on a highly doped silicon substrate 2 0 0, wherein the lightly doped epitaxial silicon layer 2 0 1 The dopant concentration is between 1 014 / cm3 and 1017 / cm3 and the thickness of the epitaxial layer is between 3 microns and 35 microns, which is determined by the specified breakdown voltage; The dopant concentration of the doped semiconductor substrate 2000 is between 1 019 / cm3 and 5 X 102G / cm3, and its thickness is determined according to the size of the wafer. Figure 2B shows a first step photoresist (PR1) step (not shown) used
第10頁 1232592 五、發明說明(5) ^^- 來成形(pattern)該氮化石夕層203,其中一個保護環區之 的該氮化矽層2 0 3係利用非等向乾式#刻法來加予去除,卜 而該保護環區之該成形(p a 11 e r n e d )氮化石夕層2 0 3 a係力口 圖二C顯示位於該成形氮化矽層2 0 3 a之外的該墊氧 物層2 0 2係利用緩衝(b u f f e r e d )氫氟酸或稀釋氫氟酸來加 予去除;然後,在一個水蒸氣(s t e a m)或溼氧環境下進行 部氧化矽(LOCOS)製程,以形成一個内部局部氧化;^夕J^二 化物層2 0 4 b及一個外部局部氧化矽場氧化物層2 〇 4 a。該3 部/外部局部氧化矽場氧化物層2 0 4 b / 2 0 4 a的厚度係介於 6 0,0 0埃和1 〇 〇 〇 〇埃之間,而氧化溫度係介於丨〇 〇 〇和丨2 C之間。這裡值得注意的是,該局部氧化矽製程可以不必 去除該成形氮化矽層2 0 3 a之外的該墊氧化物層2 〇 2來進杆 氧化。 τ 圖一 D顯示该成形氮化石夕層2 0 3 a係利用熱填酸或非等 向乾式餘刻法來加予去除。 ^圖二E顯示以一種自動對準的方式進行離子佈植將一 種第二導電型的摻雜質誇過該成形墊氧化物層2〇2a佈植於 該半導體基板2 0 1 / 2 0 0的一個表面部份之内;然後,進行 雜質驅入製程來形成一個凸出擴散保護環2 〇 5 a ;接著,該 塾氧化物層20 2a係利用稀釋氫氟酸或緩衝氫氟酸來加予去 除’而該外部/内部局部氧化矽場氧化物層2〇4a/2〇4b亦同 時被蚀刻;之後,進行一個第二罩幕光阻(p R 2 )步驟將該 外部局部氧化石夕場氧化物層2 〇 4 a及該凸出擴散保護環2 0 5 aPage 10, 1232592 5. Description of the invention (5) ^^-To pattern the nitride nitride layer 203, the silicon nitride layer 203 in one of the protection ring regions uses an anisotropic dry type #etching method. To remove, and the formed (pa 11 erned) nitride nitride layer 2 0 3 a of the protection ring area is shown in FIG. 2C, the pad located outside the formed silicon nitride layer 2 0 3 a The oxygen layer 202 is removed by using buffered hydrofluoric acid or diluted hydrofluoric acid; then, a partial oxidation of silicon (LOCOS) process is performed in a steam or wet oxygen environment to form An internal partial oxidation; ^ Xi J ^ two compound layer 2 0 4 b and an external local oxide silicon field oxide layer 2 0 4 a. The thickness of the 3 / external localized silicon field oxide layer 2 0 4 b / 2 0 4 a is between 60,000 angstroms and 1,000 angstroms, and the oxidation temperature is between 丨 〇 〇〇 and 丨 2 C. It is worth noting here that the local silicon oxide process does not need to remove the pad oxide layer 202 other than the shaped silicon nitride layer 203a to perform rod oxidation. τ Figure 1D shows that the formed nitrided layer 203a is added and removed by hot-filled acid or anisotropic dry-etching method. ^ Figure 2E shows ion implantation in an automatic alignment method. A second conductivity type dopant is exaggerated over the forming pad oxide layer 202a and is implanted on the semiconductor substrate 2 0 1/2 0 0 Within a surface portion of the substrate; then, an impurity drive-in process is performed to form a protruding diffusion protection ring 205a; then, the hafnium oxide layer 202a is added with diluted hydrofluoric acid or buffered hydrofluoric acid. Pre-removal 'and the external / internal local silicon oxide field oxide layer 204a / 204b is also etched at the same time; after that, a second mask photoresist (p R 2) step is performed on the external local silicon oxide Field oxide layer 2 0 4 a and the protruding diffusion protection ring 2 0 5 a
1232592 五、發明說明(6) 的一部份表面蓋住。這裡值得注意的是,一個 埶 j 一個液態源、-個固態源或一個氣態源可以用來 2 Λ而植…這裡值得強調的是,該凸出擴散保護環 制約等於該外部/内部局部氧化矽場 乳化物層2 0 4a/ 20 4b之一個底部表面的水平。該凸出 保護環2 0 5 a可以是一個高摻雜擴散保護環、一個中度摻^ (moderate 1 y-doped)擴散保護環或一個高摻雜擴散保護環 形成於一個中度摻雜擴散保護環之内。 圖二F顯示該内部局部氧化矽場氧化物層2〇4b係利 緩衝氫氟酸來加予去除;然後,去除該第二罩幕光阻 ’接著進行一種半導體基板之清洗製程;接著,一個 石夕化物層2 0 6 a藉由一種習知自動對準石夕化(s e 1 ^ 一 & 1丨η” silicidation)製程形成於一個暴露的矽表面之上,n^ed 遠凸出擴散保δ蒦環2 0 5 a及由該凸出擴散保護環2 〇 $ a 圍的一個凹陷(recess ed)半導體基板。該金屬石夕化 = 206a係一個耐高溫(refractory)金屬石夕化物層,諸如· 9 化鎳(N i S i 2)、石夕化姑(C 〇 S i 2 )、石夕化鈦(T i S i 2 )、石夕4石夕 (M〇Si2)、矽化鈕(TaSi2)、矽化鉑(ptSi22)、匕鋼 (PdSi2)或矽化鎢(WSi2)等等。 2 化1巴 個金屬層 該金屬層; 圖二G顯示一個成形金屬層2 0 7a係形 氧化矽場氧化物層2 0 4 a 的一部份表面及 206a之上且藉由一個第三罩幕光阻(PR3) 加予成形。該成形金屬層207a 至少包含 於一個障礙金屬(barrier metal)層之上1232592 V. Part of the description of the invention (6) is covered by the surface. It is worth noting here that a 埶 j, a liquid source, a solid source, or a gaseous source can be used to plant 2 Λ ... It is worth highlighting here that the protruding diffusion protection ring constraint is equal to the external / internal local silicon oxide The level of one of the bottom surfaces of the field emulsion layer 20 4a / 20 4b. The protruding guard ring 2 0 5 a may be a highly doped diffusion guard ring, a moderately doped (moderate 1 y-doped) diffusion guard ring, or a highly doped diffusion guard ring formed in a moderately doped diffusion guard ring. Within the protection ring. FIG. 2F shows that the internal local silicon field oxide layer 204b is buffered and removed by hydrofluoric acid; then, the second mask photoresist is removed, and then a semiconductor substrate cleaning process is performed; then, a The lithium oxide layer 2 0 6 a is formed on an exposed silicon surface by a conventional self-aligning lithography (se 1 ^ a & 1 丨 η ”silicidation) process. Δ 蒦 ring 2 0 5 a and a recessed semiconductor substrate surrounded by the protruding diffusion protection ring 2 0 $ a. The metallization = 206a is a refractory metallization layer , Such as · Ni Si (Ni Si 2), Shi Xihua Gu (C0Si 2), Shi Xihua titanium (Ti S i 2), Shi Xi 4 Shi Xi (MoSi2), silicidation Button (TaSi2), platinum silicide (ptSi22), dagger steel (PdSi2) or tungsten silicide (WSi2), etc. 2 metal layers of this metal layer; Figure 2G shows a shaped metal layer 2 0 7a series oxidation A part of the surface of the silicon field oxide layer 2 0 4 a and 206 a is formed by a third mask photoresist (PR3). The formed metal layer 207 a Containing at least over a barrier metal (barrier metal) layer
第12頁Page 12
1232592 五、發明說明(7) 少包含鋁(A1)、銀(Ag)或金(Au)。該障礙金屬層至少包含 一個耐高温金屬層或一個耐高溫金屬氮化層。 這裡值得注意的是,該高摻雜矽基板2 0 0 係加予研磨 (未圖示)至一個所預定的一個厚度以降低雜散串聯電阻; 然後,形成一個背部歐姆接觸(未圖示)。 基於此,本發明之該局部氧化矽蕭特基屏障接觸結構 的特色及優點可以歸納如下: (a) 本發明之該局部氧化矽蕭特基屏障接觸結構可以提供 一個凸出擴散保護環來消除或降低接面曲率效應對逆向崩 潰電壓的影響,因而一個較高的逆向崩潰電壓可以容易地 獲得。 (b) 本發明之該局部氧化矽蕭特基屏障接觸結構提供該凸 出擴散保護環所包圍的一個凹陷半導體基板形成一個蕭特 基屏障金屬接觸來降低一個已知逆向崩潰電壓之下由該淡 摻雜磊晶矽層所產生的雜散串聯電阻,因而在一個已知順 向電流之下的一個較小順向電壓可以在不必增加細胞元面 積之下獲得。 (c ) 本發明之該局部氧化矽蕭特基屏障接觸結構具有一個 外部局部氧化矽場氧化物層及去除的一個内部局部氧化矽 場氧化物層來提供一個較佳的金屬步階覆蓋。1232592 V. Description of the invention (7) Less aluminum (A1), silver (Ag) or gold (Au). The barrier metal layer includes at least one refractory metal layer or one refractory metal nitride layer. It is worth noting here that the highly doped silicon substrate 200 is ground (not shown) to a predetermined thickness to reduce stray series resistance; then, a back ohmic contact is formed (not shown) . Based on this, the characteristics and advantages of the local silicon oxide Schottky barrier contact structure of the present invention can be summarized as follows: (a) The local silicon oxide Schottky barrier contact structure of the present invention can provide a protruding diffusion protection ring to eliminate Or reduce the effect of the curvature of the junction on the reverse breakdown voltage, so a higher reverse breakdown voltage can be easily obtained. (b) The local silicon oxide Schottky barrier contact structure of the present invention provides a recessed semiconductor substrate surrounded by the protruding diffusion protection ring to form a Schottky barrier metal contact to reduce a known reverse breakdown voltage by the The stray series resistance generated by the lightly doped epitaxial silicon layer, so a smaller forward voltage under a known forward current can be obtained without increasing the cell area. (c) The local silicon oxide Schottky barrier contact structure of the present invention has an external local silicon oxide field oxide layer and an internal local silicon oxide field oxide layer removed to provide a better metal step coverage.
第13頁 1232592 五、發明說明(8) (d ) 本發明之該局部氧化矽蕭特基屏障接觸結構可以在已 知逆向崩潰電壓、順向電壓及順向電流之下提供一個較小 化的細胞元面積具有一個較小化的凸出擴散保護環及一個 最佳化的蕭特基屏障接觸面積。 本發明雖特別以參考所附的例子或内涵來圖示及描述 ,但僅是代表陳述而非限制。再者,本發明不侷限於所列 之細節,對於熟知此種技術的人亦可瞭解,各種不同形狀 或細節的更動在不脫離本發明的真實精神和範疇下均可製 造,但亦屬本發明的範蜂。Page 131232595. Description of the invention (8) (d) The local silicon oxide Schottky barrier contact structure of the present invention can provide a smaller size under the known reverse breakdown voltage, forward voltage and forward current. The cell area has a reduced protruding diffusion protection ring and an optimized Schottky barrier contact area. Although the present invention is particularly illustrated and described with reference to the attached examples or connotations, it is only a representative statement and not a limitation. Furthermore, the present invention is not limited to the listed details. Those skilled in the art can also understand that changes of various shapes or details can be made without departing from the true spirit and scope of the present invention, but also belong to the present invention. Invented Fan Bee.
第14頁 1232592 圖式簡單說明 圖一顯示先前技術之一種蕭特基屏障接觸結構具有一 個擴散保護環的一個簡要剖面圖。 圖二A至圖二G揭示製造本發明之一種局部氧化矽蕭特 基屏障接觸結構的製程步驟及其簡要剖面圖。 代表圖號說明: 2 0 0 高摻雜半導體基板 201 淡摻雜磊晶半導體層 2 0 2 墊氧化物層 2 0 2a 成形墊氧化物層 2 0 3 氮化矽層 2 0 3 a 成形氮化矽層 2 0 4a 外部局部氧化碎場氧化物層 2 0 4b 内部局部氧化矽場氧化物層 2 0 5 a 凸出擴散保護環 2 0 6 耐高溫金屬層 206a 金屬矽化物層 207 金屬層 207a 成形金屬層Page 14 1232592 Brief Description of Drawings Figure 1 shows a schematic cross-sectional view of a prior art Schottky barrier contact structure with a diffusion guard ring. FIG. 2A to FIG. 2G show the manufacturing steps and a schematic cross-sectional view of the method for fabricating a local silicon oxide Schottky barrier contact structure of the present invention. Representative drawing number description: 2 0 0 highly doped semiconductor substrate 201 lightly doped epitaxial semiconductor layer 2 0 2 pad oxide layer 2 0 2a forming pad oxide layer 2 0 3 silicon nitride layer 2 0 3 a forming nitride Silicon layer 2 0 4a External partial oxide field oxide layer 2 0 4b Internal partial oxide field oxide layer 2 0 5 a Protruding diffusion protection ring 2 0 6 High temperature resistant metal layer 206a Metal silicide layer 207 Metal layer 207a Forming Metal layer
第15頁Page 15
Claims (1)
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
TW93106797A TWI232592B (en) | 2004-03-15 | 2004-03-15 | LOCOS Schottky barrier contact structure and its manufacturing method |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
TW93106797A TWI232592B (en) | 2004-03-15 | 2004-03-15 | LOCOS Schottky barrier contact structure and its manufacturing method |
Publications (2)
Publication Number | Publication Date |
---|---|
TWI232592B true TWI232592B (en) | 2005-05-11 |
TW200531291A TW200531291A (en) | 2005-09-16 |
Family
ID=36320077
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
TW93106797A TWI232592B (en) | 2004-03-15 | 2004-03-15 | LOCOS Schottky barrier contact structure and its manufacturing method |
Country Status (1)
Country | Link |
---|---|
TW (1) | TWI232592B (en) |
-
2004
- 2004-03-15 TW TW93106797A patent/TWI232592B/en not_active IP Right Cessation
Also Published As
Publication number | Publication date |
---|---|
TW200531291A (en) | 2005-09-16 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US20060091493A1 (en) | LOCOS Schottky barrier contact structure and its manufacturing method | |
TWI378492B (en) | Dual-metal cmos transistors with tunable gate electrode work function and method of making the same | |
TWI455209B (en) | Trench mos p-n junction schottky diode device and method for manufacturing the same | |
TWI388012B (en) | Schottky diode and method of manufacture | |
TWI234289B (en) | Schottky diode with high field breakdown and low reverse leakage current | |
US6004878A (en) | Method for silicide stringer removal in the fabrication of semiconductor integrated circuits | |
JP5542325B2 (en) | Manufacturing method of semiconductor device | |
EP0112773B1 (en) | Buried schottky clamped transistor | |
TWI779568B (en) | Manufacturing method of silicon carbide MOSFET device | |
US20060113624A1 (en) | LOCOS-based Schottky barrier diode and its manufacturing methods | |
JP4695402B2 (en) | Manufacturing method of Schottky barrier diode | |
JP2009140963A (en) | Schottky barrier diode and method of manufacturing the same | |
TWI232592B (en) | LOCOS Schottky barrier contact structure and its manufacturing method | |
US20060131686A1 (en) | LOCOS-based junction-pinched schottky rectifier and its manufacturing methods | |
JP2017130590A (en) | Semiconductor device and manufacturing method of the same | |
JP3283458B2 (en) | Method for manufacturing semiconductor device | |
TWI232591B (en) | Self-aligned Schottky barrier contact structure and its manufacturing methods | |
TWI283929B (en) | LOCOS-based schottky barrier diode and its manufacturing methods | |
JPH025428A (en) | Manufacture of semiconductor device | |
JPH03227066A (en) | Manufacture of schottky barrier diode | |
JP4011690B2 (en) | Manufacturing method of semiconductor device | |
US8159034B2 (en) | Semiconductor device having insulated gate field effect transistors and method of manufacturing the same | |
TWI246181B (en) | Scalable planar DMOS transistor structure and its fabricating methods | |
JP2000058874A (en) | Schottky barrier semiconductor device and fabrication thereof | |
JP2005038988A (en) | Semiconductor device and manufacturing method therefor |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
MM4A | Annulment or lapse of patent due to non-payment of fees |