TWI283929B - LOCOS-based schottky barrier diode and its manufacturing methods - Google Patents

LOCOS-based schottky barrier diode and its manufacturing methods Download PDF

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TWI283929B
TWI283929B TW93126799A TW93126799A TWI283929B TW I283929 B TWI283929 B TW I283929B TW 93126799 A TW93126799 A TW 93126799A TW 93126799 A TW93126799 A TW 93126799A TW I283929 B TWI283929 B TW I283929B
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layer
oxide
protection ring
diffusion
schottky barrier
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TW93126799A
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TW200610156A (en
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Ching-Yuan Wu
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Silicon Based Tech Corp
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Abstract

The LOCOS-based Schottky barrier diode of the present invention comprises a raised diffusion guard ring surrounded by an outer LOCOS field oxide layer, a recessed semiconductor substrate with or without a compensated diffusion layer surrounded by the raised diffusion guard ring, a metal silicide layer formed over a portion of the raised diffusion guard ring and the recessed semiconductor substrate, and a patterned metal layer formed at least over the metal silicide layer, wherein the raised diffusion guard ring is formed between an inner LOCOS field oxide layer and the outer LOCOS field oxide layer and the recessed semiconductor substrate is formed by removing the inner LOCOS field oxide layer. The LOCOS-based Schottky barrier diode comprises the raised diffusion guard ring to reduce junction curvature effect on reverse breakdown voltage, the recessed semiconductor substrate to reduce forward voltage, and the compensated diffusion layer to reduce reverse leakage current.

Description

1283929 五、發明說明(1) 【發明所屬之技術領域】 本發明與一種蕭特基屏障(Schottky barrier)二極體 及其製造方法有關,特別是與一種局部氧化矽基(LOCOS-based)蕭特基屏障二極體(LBSBD)及其製造方法有關。 【先前技術】 一個蕭特基屏障二極體至少包含一個金屬-半導體接 觸係被公認是一種多數載子二極體且因而作為一個高速交 換二極體或一個高頻整流器。對於作為一種交換功率二極 體之用的蕭特基屏障二極體而言,其主要設計問題均集中 於逆向崩潰電壓(VB)、逆向漏電流(IR)、順向電流(IF) 、及順向電壓(VF)。通常,一個蕭特基屏障二極體需要一 個擴散保護環來降低該金屬-半導體接觸之邊緣效應所產 生的逆向漏電電流並弛解由高邊緣電場所產生的軟性崩潰 。然而,該擴散保護環會產生接面曲率(c u r v a t u r e )效應 對逆向崩潰電壓的影響且通常需要一個較深的接面深度來 降低該接面曲率效應。因此,對於一個已知金屬-半導體 接觸面積而言,同時獲得一個較大的逆向崩潰電壓及一個 較小的順向電壓是相當困難的。 圖一顯示一種傳統蕭特基屏障二極體具有一個擴散保 護環的一個簡要剖面圖,其中一個P+擴散保護環1 0 5係透 過位於兩個成形(patterned)場氧化物層102a之間的一個1283929 V. INSTRUCTION DESCRIPTION OF THE INVENTION (1) Technical Field of the Invention The present invention relates to a Schottky barrier diode and a method of fabricating the same, and in particular to a LOCOS-based xiao The special barrier metal diode (LBSBD) and its manufacturing method are related. [Prior Art] A Schottky barrier diode comprising at least one metal-semiconductor contact is recognized as a majority carrier diode and thus acts as a high speed switching diode or a high frequency rectifier. For Schottky barrier diodes used as a switching power diode, the main design issues are focused on reverse breakdown voltage (VB), reverse leakage current (IR), forward current (IF), and Forward voltage (VF). Typically, a Schottky barrier diode requires a diffusion guard ring to reduce the reverse leakage current generated by the edge effect of the metal-semiconductor contact and to relax the soft collapse caused by the high edge electrical field. However, the diffusion guard ring produces the effect of the junction curvature (c u r v a t u r e ) effect on the reverse collapse voltage and typically requires a deep junction depth to reduce the junction curvature effect. Therefore, it is quite difficult to obtain a large reverse breakdown voltage and a small forward voltage for a known metal-semiconductor contact area. Figure 1 shows a schematic cross-sectional view of a conventional Schottky barrier diode having a diffusion protection ring in which a P+ diffusion protection ring 105 is passed through a layer between two patterned field oxide layers 102a.

1283929 五 '發明說明(2) 擴散窗口(未圖示)來形成於一個n-/n+磊晶矽基板1〇1 / 1 0 0的一個表面部份之内;一個金屬矽化物層i 0 3作為— ,蕭特基屏障金屬層係形成於該p+擴散保護環丨0 5的一部 份表面之上且置於由一個成形步階硼玻璃(BSG )層1〇6a 所包圍的該rr/n+磊晶矽基板101/丨00的表面之上;一個成 形金屬層1 0 4 a係形成於該成形場氧化物層丨〇 2 a的一部份表 面、該成形步階硼玻璃層1 〇 6 a、及該金屬石夕化物層1 〇 3 上 之 以及一個背邊金屬層(未圖示)作為一個歐姆接觸金屬 層係形成於該n+矽基板1〇〇 之上 這裡可以清楚地看到,圖一所示之該蕭特基屏障二極 +的製造需要三個罩幕光阻步驟,其中一個第一罩幕光阻 ^驟係用來定義該P+擴散保護環的該擴散窗;一個第二 ^幕光阻步驟係用來去除該成形場氧化物層1〇2a(未圖示^ 步階删玻璃層106 (未圖示)的一部份來形成該金屬石夕 上層1 0 3 ;以及一個第三罩幕光阻步驟係用來形成該成 二金屬層104a。很明顯地,該p+擴散保護環1〇5的寬度必 =保持較寬而該P+擴散保護環105的接面深度必需保持 /衣。因此,該蕭特基屏障二極體的細胞元尺寸將變大且 於—個指定順向電流(If)值的順向電壓(Vf)將變大。另外 :該成形金屬層104a的步階覆蓋(step c〇verage)亦不佳 I兼f ί,本發明的一個主要目的係提供一種局部氧化石夕 屏障二極體(LBSBD)具有一個凸出(raised)擴散 保濩%來獲得較大的逆向崩潰電壓及一個凹陷半導體基板1283929 V'Inventive Description (2) A diffusion window (not shown) is formed in a surface portion of an n-/n+ epitaxial germanium substrate 1〇1/100; a metal telluride layer i 0 3 As a - the Schottky barrier metal layer is formed over a portion of the surface of the p+ diffusion protection ring 丨0 5 and is placed in the rr/ surrounded by a forming step borosilicate (BSG) layer 1 〇 6a Above the surface of the n+ epitaxial germanium substrate 101/丨00; a formed metal layer 10 4 a is formed on a portion of the surface of the formed field oxide layer 丨〇 2 a , the forming step borosilicate layer 1 〇 6 a, and the metal lithium layer 1 〇 3 and a back side metal layer (not shown) formed as an ohmic contact metal layer on the n + 矽 substrate 1 这里 can be clearly seen here The fabrication of the Schottky barrier diode + shown in FIG. 1 requires three mask photoresist steps, wherein a first mask photoresist is used to define the diffusion window of the P+ diffusion protection ring; The second surface photoresist step is used to remove the formed field oxide layer 1〇2a (not shown) stepped glass layer 106 (not shown) a portion of the metal layer 10b; and a third mask photoresist step for forming the second metal layer 104a. Obviously, the width of the p+ diffusion protection ring 1〇5 Must be kept wide and the junction depth of the P+ diffusion protection ring 105 must be kept/clothed. Therefore, the cell size of the Schottky barrier diode will become larger and the specified forward current (If) value The forward voltage (Vf) will become larger. In addition, the step c〇verage of the formed metal layer 104a is also poor, and a main object of the present invention is to provide a local oxide oxide barrier. The diode (LBSBD) has a raised diffusion protection % to obtain a large reverse breakdown voltage and a recessed semiconductor substrate

1283929 五 、發明說明(3) 來獲得較小的順向電壓 本發明的另一個目的係提供一種 屏P早二極體(LBSBD)具有一個較佳的金屬乳化妙基蕭特基 本發明的一個重要目的係提供一種 &覆蓋。 基屏障二極體(LBSBD)具有—個補償二 /梦基蕭特 半導體基板的一個表面部份之内來降、形成於該凹陷 image-f〇rCe 1〇Wering)效應像力降低( 一步透過降低該凸出擴散保護環曲率属電電:且進 逆向崩潰電壓。 手效應來增加 【發明内容】 本發明揭示一種局部氣仆石々Α # Μ β β π 二 二β丨乳化矽基蕭特基屏障二極體及其 製造方法。该局部氧化矽基蕭特基屏障二極體至少包含一 種第一導電型的一個半導體基板具有一個淡摻雜磊晶矽層 形成於一個,摻雜石夕基板之上、一種第二導電型的一個凸 出擴散保護f形成於一個外部局部氧化矽場氧化物層及一 個内部局部氧化矽場氧化物層之間、一個凹陷半導體基板 具有或不具有由該凸出擴散保護環所包圍的一個補償擴散 層、一個金屬石夕化物層形成於該凸出擴散保護環的一部份 表面及由該凸出擴散保護環所包圍的該凹陷半導體基板的 表面之上、以及一個成形金屬層至少形成於該金屬矽化物 層之上’其中該補償擴散層在未執行局部氧化矽製程之前 藉由跨過一個塾(p a d)氧化物層佈植一個補償劑量的摻雜1283929 V. INSTRUCTION DESCRIPTION (3) To obtain a smaller forward voltage Another object of the present invention is to provide an important aspect of the basic invention of a screen P early diode (LBSBD) having a preferred metal emulsification base. The purpose is to provide an & coverage. The barrier-type diode (LBSBD) has a surface portion of the compensation second/Monte-based Schottky semiconductor substrate, and the image-f〇rCe 1〇Wering effect is reduced in the image. Reducing the curvature of the convex diffusion protection ring belongs to electric electricity: and enters the reverse collapse voltage. The hand effect is increased. SUMMARY OF THE INVENTION The present invention discloses a local gas servant # Μ β β π 二 二 β 丨 emulsifier 萧 萧 萧 萧a barrier bismuth body and a method of fabricating the same, the local yttrium oxide Schottky barrier diode comprising at least one semiconductor substrate of a first conductivity type having a lightly doped epitaxial layer formed on one, doped shi Above, a convex diffusion protection f of a second conductivity type is formed between an external localized yttrium oxide field layer and an internal localized yttrium oxide field layer, and a recessed semiconductor substrate has or does not have a convex a compensation diffusion layer surrounded by the diffusion protection ring, a metal lithium layer formed on a portion of the surface of the convex diffusion protection ring and surrounded by the convex diffusion protection ring Above the surface of the recessed semiconductor substrate, and a shaped metal layer formed on at least the metal germanide layer, wherein the compensating diffusion layer spans a pad oxide layer before performing the local germanium oxide process Budding a compensating dose of doping

第9頁 1283929 五、發明說明(4) 質於該凹陷半導體基板的一個表面部份之内來形成而該内 部局部氧化矽場氧化物層係在執行一個擴散製程來形成該 凸出擴散保護環之後透過一個罩幕光阻步驟來加予去除。 本發明之該局部氧化矽基蕭特基屏障二極體提供該凸出擴 散保護環來降低接面曲率效應對逆向崩潰電壓的影響、該 凹陷半導體基板來形成一個蕭特基屏障接觸以降低雜散串 聯電阻、以及該補償擴散層形成於該凹陷半導體基板的一 個表面部份之内來降低由影像力降低效應所產生的逆向漏 電電流並進一步降低該凸出擴散保護環的該接面曲率效應 【實施方式】 現請參見圖二A至圖二G,其中揭示製造本發明之一種 第一型局部氧化矽基蕭特基屏障二極體的製程步驟及其簡 要剖面圖。 圖二A顯示一個墊(pad)氧化物層2 0 2 係形成於一種第 一導電型的一個半導體基板201/200之上;一個罩幕氮化石夕 層203係形成於該墊氧化物層202 之上;接著,進行—個 第一罩幕光阻(PR1)步驟來定義一個擴散保護環區(pGR)。 該墊氧化物層2 0 2係一個熱二氧化矽層且在一個乾氧環境 下成長於該半導體基板201/200之上,其厚度係介於1〇f 埃和5 0 0埃之間。該罩幕氮化矽層2 0 3係藉由低壓化學氣相 堆積(LPCVD)法來形成且其厚度係介於5〇〇埃和15〇〇 ^之間Page 9 1283929 V. INSTRUCTION DESCRIPTION (4) The quality is formed in a surface portion of the recessed semiconductor substrate and the internal partial oxide field oxide layer is subjected to a diffusion process to form the protruding diffusion protection ring. It is then removed by a mask photoresist step. The local yttrium oxide Schottky barrier diode of the present invention provides the embossed diffusion protection ring to reduce the effect of the junction curvature effect on the reverse collapse voltage, and the recessed semiconductor substrate forms a Schottky barrier contact to reduce the impurity a series resistance and a compensation diffusion layer are formed in one surface portion of the recessed semiconductor substrate to reduce a reverse leakage current generated by an image force reduction effect and further reduce a curvature effect of the junction of the convex diffusion protection ring [Embodiment] Referring now to Figures 2A to 2G, a process step for fabricating a first type of local yttrium oxide Schottky barrier diode of the present invention and a schematic cross-sectional view thereof are disclosed. 2A shows that a pad oxide layer 2 0 2 is formed over a semiconductor substrate 201/200 of a first conductivity type; a mask nitride layer 203 is formed on the pad oxide layer 202. Above; then, a first mask photoresist (PR1) step is performed to define a diffusion guard ring region (pGR). The pad oxide layer 220 is a thermal ceria layer and is grown on the semiconductor substrate 201/200 in a dry oxygen atmosphere having a thickness between 1 〇f Å and 500 Å. The mask tantalum nitride layer is formed by a low pressure chemical vapor deposition (LPCVD) method and has a thickness of between 5 〇〇 and 15 〇〇 ^.

1283929 五、發明說明(5) 。該半導體基板2 0 1 / 2 0 0至少包含一個淡摻雜磊晶矽層2 0 1 形成於一個高摻雜矽基板2 0 0之上,其中該淡摻雜磊晶矽 層201之内的摻雜質濃度係介於1〇14/立方公分和1〇17/立方 公分之間而磊晶層厚度係介於2微米和3 5微米之間,並依 所需的崩潰電壓來決定;該高摻雜半導體基板200的摻雜質 濃度係介於1 018 /立方公分和5 · 0 X 1 020 /立方公分之間而 其厚度係介於2 5 0微米和8 0 0微米之間,並依照晶圓的尺寸 大小來決定。 圖二B顯示位於該擴散保護環區(DGR)之外的該罩幕氮 化碎層2 0 3係利用非等向乾式餘刻法來加予去除,以形成 一個内部場氧化物層區(I F Ο X R )及一個外部場氧化物層區 (OFOXR)。因此,位於該擴散保護環區(DGR)的該成形^幕 氮化石夕層2 0 3 a係加予保留。 圖二C顯示位於該成形罩幕氮化矽層2 〇 3 a之外的該塾 氧化物層202係利用緩衝(buffered)氫氟酸或稀釋氮* 酸來加予去除;然後,在一個水蒸氣(steam )或漫氧二= 下進行局部氧化矽(LOCOS )製程,以形成一個内部=广 氧化矽場氧化物層204b於該内部場氧化物區(4 内及一個外部局部氧化矽場氧化物層2 〇 4 a於該外部p童之 物區(OF0XR )之内。該内部/外部局部氧化石夕場氧=氧化 204b/204a的厚度係介於6000埃和10000埃之間,物層 溫度係介於9 5 0 °C和1 2 0 0 °C之間。這裡值得注意的f氧二化 局部氧化矽製程可以不必去除該成形罩幕氮化石夕層^ ’該 外的該墊氧化物層202 來進行氧化。 胃 ^之1283929 V. Description of invention (5). The semiconductor substrate 2 0 1 / 2 0 0 at least comprises a lightly doped epitaxial layer 2 0 1 formed on a highly doped germanium substrate 200, wherein the lightly doped epitaxial layer 201 is The doping concentration is between 1〇14/cm3 and 1〇17/cm^3 and the thickness of the epitaxial layer is between 2μm and 35μm, and is determined by the required breakdown voltage; The doping concentration of the highly doped semiconductor substrate 200 is between 1 018 /cm ^ 3 and 5 · 0 X 1 020 /cm ^ 3 and the thickness is between 250 μm and 800 μm, and It is determined by the size of the wafer. Figure 2B shows that the mask nitride layer 206 outside the diffusion protection ring region (DGR) is removed by anisotropic dry residuation to form an internal field oxide layer region ( IF Ο XR ) and an external field oxide layer (OFOXR). Therefore, the forming layer of the nitride layer in the diffusion protection ring region (DGR) is retained. Figure 2C shows that the tantalum oxide layer 202 outside the tantalum nitride layer 2 〇 3 a of the forming mask is removed by buffering hydrofluoric acid or diluted nitrogen acid; then, in a water A partial oxidation enthalpy (LOCOS) process is carried out under steam or diffuse oxygen = to form an internal = wide yttrium oxide field oxide layer 204b in the internal field oxide region (4 and an external local yttria field oxidation) The layer 2 〇4 a is within the outer object area (OF0XR) of the outer p. The internal/external local oxidized oxide field oxide = the thickness of the oxide 204b/204a is between 6000 angstroms and 10000 angstroms, the layer The temperature system is between 950 ° C and 1 200 ° C. The notable f-oxygenated local yttrium oxide process here may not need to remove the forming mask nitriding layer ^ 'the outside of the pad oxidation The layer 202 is oxidized.

12839291283929

圖二D顯示該点:^ 非等向乾式蝕刻法^ f形軍幕氮化矽層2 0 3 a係利用熱磷酸或 進行離子佈植,將f加予去除;接著,以自動對準的方式 氧化物層2〇2a佑# —種第二導電型的摻雜質跨過該成形墊 份來形成一個離子、邊+導體基板201/200的一個表面部 該成形墊氧化物居佈植區2 〇 5 a。這裡值得注意的是,若將 個固體源或一個^ 2 0 2 a加予去除,則利用一個液體源、一 子佈植。 職4體源的一種傳統熱擴散製程可以取代離 圖二b顯示進〜 護環2 0 5b而該外告订雜質驅入製程來形成一嗰凸出擴散保 及該成形墊氧化内部局部氧化石夕場氧化物層2 04a/ 2 04b ,該凸出擴散保ΐSt亦同時變厚。這裡值得強調的是 / ιλι a Μ & /、β隻辰2 0 5 b的接面深度係控制稍深於該外部 ^ 匕矽場氧化物層204c/204d的一個底部表面水 平。該凸出擴散保護環2〇 5b可以是一個高摻雜擴散保護環 、一個中度摻雜擴散保護環或一個高摻雜擴散保護環形成 於一個中度摻雜擴散保護環之内。 圖一 w不進行一個第二罩幕光阻(PR2)步驟,並將启 形第二罩幕光阻(pR2)置於該外部局部氧化矽場氧化物 2 0 4c及該凸出擴散保護環2〇5b之上的一個熱氧 2 0 2b的一部份表面之上。 乳化矽層 用 光阻 圖二G顯示該成形第二罩幕光阻之外(PR2)的該 局部氧化f場氧化物層2 0 4d及該熱二氧化矽層2〇2b ^ 用緩衝氫氟酸來加予去除;然後,去除該成形第二軍、 (pR2)並進行晶片的清洗製程;接著/ 一7固金』Figure 2D shows this point: ^ Non-isotropic dry etching method ^ f-shaped military screen tantalum nitride layer 2 0 3 a system using hot phosphoric acid or ion implantation, f is added to remove; then, with automatic alignment The oxide layer of the second conductivity type spans the forming pad to form a surface portion of the ion-side + conductor substrate 201/200. 2 〇 5 a. It is worth noting here that if a solid source or a ^ 2 0 2 a is added for removal, a liquid source and a single plant are used. A conventional thermal diffusion process of the body 4 source can be substituted for the second to the guard ring 2 0 5b and the external impurity is driven into the process to form a 嗰 convex diffusion to protect the forming oxidized internal local oxidized stone. The epoch oxide layer 2 04a / 2 04b, the bulging diffusion protection St also becomes thicker at the same time. It is worth emphasizing that the junction depth of / ιλι a Μ & /, β 辰 2 0 5 b is slightly deeper than the bottom surface level of the outer ^ 氧化物 field oxide layer 204c/204d. The protruding diffusion protection ring 2〇 5b may be a highly doped diffusion protection ring, a moderately doped diffusion protection ring or a highly doped diffusion protection ring formed within a moderately doped diffusion protection ring. Figure 1 w does not perform a second mask photoresist (PR2) step, and places the second mask photoresist (pR2) on the external local oxide field oxide 2 0 4c and the protruding diffusion protection ring Above a surface of a hot oxygen 2 0 2b above 2〇5b. The emulsified ruthenium layer photoresist diagram II G shows the local oxide f field oxide layer 2 0 4d outside the formed second mask photoresist (PR2) and the thermal ruthenium dioxide layer 2 〇 2b ^ buffered hydrogen fluoride Acid is added for removal; then, the formed second army, (pR2) is removed and the wafer cleaning process is performed; then / 7 solid gold

第12頁 1283929 五、發明說明(7) 矽化物層2 0 6 a係藉由一種習知的自動對準矽化製程來形成 於一個暴露的矽表面之上,包括該凸出擴散保護環的一部 份表面及由該凸出擴散保護環2 0 5b所包圍的一個凹陷半導 體基板2 0 1 / 2 0 0 。該金屬矽化物層2 0 6 a係一個耐高溫( refractory )金屬石夕化物層。 圖二G又顯示一個成形金屬層207a係藉由一個第三罩 幕光阻(PR3 )步驟(未圖示)來形成於該外部局部氧化矽 場氧化物層204c 的一部份表面及該金屬矽化物層206a之 上。該成形金屬層207a至少包含一個金屬層置於一個障 礙(barrier)金屬層之上。該金屬層至少包含鋁(A1) 、銀(Ag)或金(Au)。該障礙金屬層至少包含一個耐高溫金 屬層或一個耐高溫金屬氮化物層。這裡值得注意的是,該 高摻雜矽基板2 0 0係加予背部研磨至一個所預定的厚度來 降低雜散串聯電阻。然後,進行一個背部歐姆接觸(未圖 示)。很明顯地,本發明之該第一型局部氧化矽基蕭特基 屏障二極體的特色及優點可以歸納如下: (a) 本發明之該第一型局部氧化矽基蕭特基屏障二極體提 供一個凸出擴散保護環來降低接面曲率效應對逆向崩潰電 壓的影響,因此一個較大的逆向崩潰電壓可以藉由該凸出 擴散保護環的一個較小接面深度來得到。 (b ) 本發明之該第一型局部氧化矽基蕭特基屏障二極體提 供該凸出擴散保護環所包圍的一個凹陷半導體基板來形成Page 12 1283929 V. INSTRUCTION DESCRIPTION (7) The telluride layer 2 0 6 a is formed on an exposed crucible surface by a conventional auto-alignment deuteration process, including one of the protruding diffusion protection rings a portion of the surface and a recessed semiconductor substrate 2 0 1 / 2 0 0 surrounded by the protruding diffusion protection ring 2 0 5b. The metal telluride layer 2 0 6 a is a high temperature resistant (refractory) metallurgical layer. Figure 2G further shows that a shaped metal layer 207a is formed on a portion of the surface of the external partial oxide field oxide layer 204c and the metal by a third mask photoresist (PR3) step (not shown). Above the telluride layer 206a. The shaped metal layer 207a comprises at least one metal layer disposed over a barrier metal layer. The metal layer contains at least aluminum (A1), silver (Ag) or gold (Au). The barrier metal layer comprises at least one high temperature resistant metal layer or one high temperature resistant metal nitride layer. It is worth noting here that the highly doped germanium substrate 200 is back ground to a predetermined thickness to reduce the stray series resistance. Then, perform a back ohmic contact (not shown). Obviously, the characteristics and advantages of the first type of local yttrium oxide Schottky barrier diode of the present invention can be summarized as follows: (a) The first type of local yttrium oxide Schottky barrier diode of the present invention The body provides a convex diffusion protection ring to reduce the effect of the junction curvature effect on the reverse collapse voltage, so a larger reverse collapse voltage can be obtained by a smaller junction depth of the convex diffusion protection ring. (b) the first type of cerium oxide-based Schottky barrier diode of the present invention provides a recessed semiconductor substrate surrounded by the protruding diffusion protection ring to form

1283929 五、發明說明(8) 一個蕭特基屏障金屬接觸以降低一個已知逆向崩潰電壓之 下的該淡摻雜磊晶矽層之雜散串聯電阻,因而在一個已知 順向電流之下的一個較小順向電壓可以在不必增加細胞元 面積之下獲得。 (c ) 本發明之該第一型局部氧化矽基蕭特基屏障二極體具 有一個外部局部氧化矽場氧化物層及去除的一個内部局部 氧化矽場氧化物層來提供一個較佳的金屬步階覆蓋。 (d ) 本發明之該第一型局部氧化矽基蕭特基屏障二極體可 以在已知逆向崩潰電壓、順向電壓及順向電流之下提供一 個較小化的細胞元面積具有一個較小化的凸出擴散保護環 及一個最佳化的蕭特基屏障接觸面積。 現請參見圖三A至圖三F,其中揭示製造本發明之一種 第二型局部氧化矽基蕭特基屏障二極體之接續圖二B的製 程步驟及其簡要剖面圖。 圖三A顯示以一種自動對準的方式進行一個離子佈植 製程來形成該第二導電型的補償離子佈植區208b/208a於 該成形罩幕氮化矽層2 0 3 a之外的該淡摻雜磊晶矽層2 0 1的 表面部份之内。該補償離子佈植區208b/208a的佈植劑量 係適當地加予調整,使其尖峰摻雜質濃度約略等於該淡摻 雜磊晶矽層2 0 1的摻雜質濃度。 圖三B 顯示進行一個局部氧化矽製程來形成一個内部1283929 V. INSTRUCTIONS (8) A Schottky barrier metal contact to reduce the stray series resistance of the lightly doped epitaxial layer below a known reverse collapse voltage, thus below a known forward current A smaller forward voltage can be obtained without having to increase the cell area. (c) The first type of local cerium oxide-based Schottky barrier diode of the present invention has an outer partial yttrium oxide field oxide layer and an internal partial yttrium oxide field oxide layer removed to provide a preferred metal Step coverage. (d) The first type of local cerium oxide-based Schottky barrier diode of the present invention can provide a smaller cell area under known reverse collapse voltage, forward voltage and forward current. A reduced bulging diffusion protection ring and an optimized Schottky barrier contact area. Referring now to Figures 3A through 3F, there is disclosed a process step and a cross-sectional view of a second type of localized cerium oxide-based Schottky barrier diode of the present invention. Figure 3A shows an ion implantation process in an auto-alignment manner to form the second conductivity type compensation ion implantation region 208b/208a outside the formation mask tantalum nitride layer 2 0 3 a The surface portion of the lightly doped epitaxial layer 20 1 is within. The implant dose of the compensated ion implantation region 208b/208a is suitably adjusted so that the peak doping concentration is approximately equal to the doping concentration of the lightly doped epitaxial layer 201. Figure 3B shows a partial yttrium oxide process to form an internal

第14頁 1283929Page 14 1283929

5 til夕場氧化物層2〇4b於該内部場氧化物區(IFOXR) ^ 一個外部局部氧化矽場氧化物層2 0 4a於該外部場氧化物 區OyOXR)、’、如圖二c所描述。這裡可以清楚地看到,圖三 A所不之該補償離子佈植區2〇8b/2〇8a係同時加予驅入來形 成該第一導電型的補償擴散層208d/208c。 ,圖三C顯示位於該擴散保護環區(DGR)之内的該成形罩 幕氮化石夕層2 0 3 a係利用熱磷酸或非等向乾式蝕刻法來加予 去除’然後以自動對準的方式進行離子佈植,如圖二D所 描述。 ,三D顯示進行一個雜質驅入製程來形成一個凸出擴 散保護環2 0 5 b並同時使該成形墊氧化物層2 〇 2 a及該内部^ 外部局部氧化矽場氧化物層2〇4b/ 204a變厚,如圖二E所描 述。 圖三E顯示進行一個第二罩幕光阻(PR2)步驟來形成一 個成形第二罩幕光阻(p R 2 )於該外部局部氧化矽場氧化物 層204c及該熱二氧化矽層202b的一部份表面之上。 根據圖二G所描述的相同製程步驟,圖三f可以輕易 地得到。由圖三F可以清楚地看到,置於該金屬矽化物層 2 0 6a之下的該補償擴散層2〇8f具有位於該淡摻雜蟲晶石夕^ 201的一個表面部份之内的一個較低之摻雜質分佈可以大 幅地降低本發明之該第二型局部氧化矽基蕭特基屏障二極 體的影像力效應對逆向漏電電流的影響。另外,可以清楚 地看到,該補償擴散層2 0 8 f / 2 0 8 e可以大幅地降低該^出 擴散保護環205b的接面曲率效應,因而比圖二g具有較大5 til 场 oxide layer 2 〇 4b in the internal field oxide region (IFOXR) ^ an external local oxidized lanthanum oxide layer 2 0 4a in the external field oxide region OyOXR), ', as shown in Figure 2c description. It can be clearly seen here that the compensating ion implantation region 2〇8b/2〇8a of Fig. 3A is simultaneously applied to drive to form the compensating diffusion layer 208d/208c of the first conductivity type. Figure 3C shows that the shaped mask nitride layer in the diffusion protection ring region (DGR) is removed by thermal phosphoric acid or non-isotropic dry etching, and then automatically aligned. The method of ion implantation is as shown in Figure 2D. , three D shows an impurity drive-in process to form a convex diffusion protection ring 2 0 5 b and simultaneously make the forming pad oxide layer 2 〇 2 a and the internal ^ external local yttrium oxide field oxide layer 2 〇 4b / 204a thickens as depicted in Figure 2E. Figure 3E shows a second mask photoresist (PR2) step to form a shaped second mask photoresist (p R 2 ) to the external partial oxide field oxide layer 204c and the thermal ceria layer 202b. Part of the surface. Figure 3 f can be easily obtained according to the same process steps as described in Figure 2G. As can be clearly seen from FIG. 3F, the compensating diffusion layer 2〇8f disposed under the metal telluride layer 206 has a surface portion of the lightly doped smectite 201. A lower doping profile can substantially reduce the effect of the image force effect of the second type of local yttrium oxide Schottky barrier diode of the present invention on the reverse leakage current. In addition, it can be clearly seen that the compensating diffusion layer 2 0 8 f / 2 0 8 e can greatly reduce the junction curvature effect of the diffusion protection ring 205b, and thus has a larger ratio than the graph g

1283929 發明說明(10) 的崩潰電壓可以輕易地得到 現請參見圖四A及圖四B,其 一 第三型局部氧化矽基簫特美屏拉 ^ ^ 裡 化製程步驟及其簡要障二極體之接續圖二E的簡 圖四A顯不一個覆蓋介雷Μ D Λ A -個結構表面之上接著,電進層一2 0 9 /糸形成於/ 所示的 步驟來定義一個主動區ί形成進仃厂J第二草幕光阻(PR2) 成形第二罩幕光阻(PR2)之下成的一'金屬梦化物層2 0 6a及該 (未圖示)。這裡值得注意的0的—個終結(termination)區 保護環2 0 5b之外至少包含複= Λ = = 5區除工該凸出擴散 該覆蓋介電層2 0 9係由氮化矽所出漂洋擴散環(未圖示)。 其厚度係介於5 0 0埃和3 0 0 0 成且利用[^^來堆積, 蓋介ΚΓΛ位/Λ成Λ第。罩幕★阻(pr2)之外的該覆 盈"电層2 0 9係利用非等向乾式為w、丄 蓋介電層20 9a ;位於該成形第罩4^^來形成一個成形覆 熱二氧化梦層2〇2b及該内部局部一氧罩化\光阻(PR2)之外的該 利用非等向乾式蝕刻法或緩衝氫氟酸n〇4b: 除該成形第二罩幕光阻(PR2);然;m自= 矽化製程來形成該金屬矽化物層2 〇 6 _ 霞切主π 01於该主動區的一個暴 屬石夕彳卜必之上接著,一個成形金屬層2 0 7a係形成於該金 1矽化物層2 0 6 a及該成形覆蓋介電層2〇9&的一部份表面之 由圖四B可以清楚地看到,該成形覆蓋介雷層2〇9a 但做為一個硬質罩幕層來形成該金屬矽化物層2〇63而且做1283929 Inventive Note (10) The breakdown voltage can be easily obtained. Please refer to Figure 4A and Figure 4B for a third type of partial oxidation 矽 箫 箫 屏 屏 ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ Figure Continuation Figure 2E is a simplified diagram of the four A-displays. A 个 Μ Λ - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -形成 Forming the second curtain of the J (the second curtain) (PR2) Forming a 'metal dreaming layer 2 0 6a under the second mask photoresist (PR2) and this (not shown). Here, the notched 0-termination zone guard ring 2 0 5b contains at least complex = Λ = = 5 zone. The bump diffusion spreads the dielectric layer 2 0 9 by the tantalum nitride Floating ocean diffusion ring (not shown). The thickness is between 500 Å and 3,000 Å and is accumulated by [^^, and the capping ΚΓΛ/Λ Λ is the first. The covering layer ★ (P2) is not covered by the "pr2" electric layer. The electric layer is made of an anisotropic dry type w and a capping dielectric layer 20 9a; and the forming mask 4 is formed to form a forming cover. The non-isotropic dry etching method or the buffered hydrofluoric acid n〇4b other than the thermal dioxide dioxide layer 2〇2b and the internal partial oxygen masking/resistance (PR2): in addition to the forming second mask light Resistance (PR2); then; m from = deuteration process to form the metal telluride layer 2 〇6 _ Xia-cut main π 01 in the active region of a violent stone 彳 彳 之上 , , , , , , , , , 0 7a is formed on the gold 1 germanide layer 2 0 6 a and a part of the surface of the shaped cover dielectric layer 2〇9& which can be clearly seen from FIG. 4B, the shaped cover layer 2 9a but as a hard mask layer to form the metal telluride layer 2〇63 and do

第16頁 1283929 五、發明說明(π) 為一個純化(passivation)或保護層。更重要的是,與圖 二G作比較,該成形覆蓋介電層209a可以提供成形一個厚 金屬層(未圖示)的一個触刻停止層。 現請參見圖五A及圖五B,其中揭示製造本發明之一種 第四型局部氧化矽基蕭特基屏障二極體之接續圖三D的簡 化製程步驟及其簡要剖面圖。 圖五A顯示一個覆蓋介電層2 0 9係形成於圖三D所示的 一個結構表面之上;然後,進行一個第二罩幕光阻(P R 2 ) 步驟,如圖四A所描述。Page 16 1283929 V. Description of the invention (π) is a passivation or protective layer. More importantly, the shaped cover dielectric layer 209a can provide a etch stop layer that forms a thick metal layer (not shown) as compared to Figure 2G. Referring now to Figures 5A and 5B, there is shown a simplified process step and a simplified cross-sectional view of a fourth type of localized cerium oxide-based Schottky barrier diode of the present invention. Figure 5A shows a cover dielectric layer 209 formed over a surface of the structure shown in Figure 3D; then, a second mask photoresist (P R 2 ) step is performed, as depicted in Figure 4A.

根據圖四B所描述的相同製程步驟,圖五B可以輕易地 得到。很明顯地,與圖三F作比較,上述之第四型局部氧 化矽基蕭特基屏障二極體的優點及特色係與圖四B所描述 的相同。 根據上述的描述,本發明之局部氧化矽基蕭特基屏障 二極體的優點及特色可以歸納如下··Figure 5B can be easily obtained according to the same process steps as described in Figure 4B. Obviously, compared with Figure 3F, the advantages and characteristics of the fourth type of localized yttrium-based Schottky barrier diode described above are the same as those described in Figure 4B. According to the above description, the advantages and characteristics of the local yttrium oxide Schottky barrier diode of the present invention can be summarized as follows:

(a) 本發明之局部氧化矽基蕭特基屏障二極體提供位於一 個内部局部氧化矽場氧化物層及一個外部局部氧化矽場氧 化物層之間的一個凸出擴散保護環來降低具有一個較小接 面深度的該凸出擴散保護環之接面曲率效應對該逆向崩潰 電壓的影響。 (b ) 本發明之局部氧化矽基蕭特基屏障二極體提供位於該 淡摻雜磊晶矽層之内的一個凹陷半導體表面來形成一個蕭(a) The local yttrium oxide Schottky barrier diode of the present invention provides a embossed diffusion protection ring between an internal local yttrium oxide field oxide layer and an external local yttrium oxide field oxide layer to reduce The effect of the junction curvature effect of the convex diffusion protection ring on the reverse collapse voltage of a small junction depth. (b) The local cerium oxide-based Schottky barrier diode of the present invention provides a recessed semiconductor surface located within the lightly doped epitaxial layer to form a depression

第17頁 1283929 五、發明說明(12) 特基屏障接觸以降低順向電壓。 (c ) 本發明之局部氧化矽基蕭特基屏障二極艟提供由該凸 出擴散保護環所包圍的一個補償擴散層以形成該蕭特基屏 障接觸來降低該影像力降低效應對該逆向漏電電流的影響 且同時消除或降低該接面曲率效應對逆向崩潰電壓的影響 (d ) 本發明之局部氧化矽基蕭特基屏障二極體提供一個平 滑的表面來改進金屬步階覆蓋。 (e ) 本發明之局部氧化矽基蕭特基屏障二極體提供一個覆 蓋介電層以作為一個硬質罩幕層來成形該蕭特基屏障接觸 區及該終結區並且同時作為一個鈍化或保護層及成形一個 較厚金屬層的一個#刻停止層。 這裡值得注意的是,該補償離子佈植區2 0 8 a / 2 0 8 b之 内的佈植摻雜質對於該rr/n+ 矽基板2 0 1 / 2 0 0而言係硼摻雜 質。這裡值得強調的是,上述之局部氧化矽基蕭特基屏障 二極體可以藉由改變該凸出擴散保護環及該補償離子佈植 區的摻雜質型態來輕易地製造該局部氧化矽基蕭特基屏障 二極體於一個p_/p+ 矽基板之上。 本發明雖特別以參考所附的例子或内涵來圖示及描述 ,但僅是代表陳述而非限制。再者,本發明不侷限於所列Page 17 1283929 V. INSTRUCTIONS (12) The special base barrier contacts to reduce the forward voltage. (c) a local cerium oxide-based Schottky barrier diode of the present invention provides a compensation diffusion layer surrounded by the convex diffusion protection ring to form the Schottky barrier contact to reduce the image force reduction effect to the reverse The effect of leakage current and at the same time eliminating or reducing the effect of the junction curvature effect on the reverse collapse voltage (d) The local yttrium oxide Schottky barrier diode of the present invention provides a smooth surface to improve metal step coverage. (e) The local cerium oxide-based Schottky barrier diode of the present invention provides a covering dielectric layer as a hard mask layer to form the Schottky barrier contact region and the termination region and simultaneously serves as a passivation or protection The layer and a #刻止层 layer forming a thicker metal layer. It is worth noting here that the implant doping within the compensated ion implantation region of 2 0 8 a / 2 0 8 b is boron doping for the rr/n+ germanium substrate 2 0 1 / 2 0 0 . It is worth emphasizing here that the above-mentioned local yttrium oxide Schottky barrier diode can easily fabricate the local yttrium oxide by changing the doping type of the convex diffusion protection ring and the compensation ion implantation region. The Schottky barrier diode is on a p_/p+ 矽 substrate. The present invention has been illustrated and described with particular reference Furthermore, the invention is not limited to the listed

第18頁 1283929 五、發明說明(13) 之細節,對於熟知此種技術的人亦可瞭解,各種不同形狀 或細節的更動在不脫離本發明的真實精神和範疇下均可製 造,但亦屬本發明的範疇。Page 18 1283929 V. Details of the Invention (13), those skilled in the art will also appreciate that various shapes or details can be made without departing from the true spirit and scope of the invention, but also The scope of the invention.

第19頁 1283929 圖式簡單說明 圖一顯示先前技術之一種蕭特基屏障接觸結構的一個 簡要剖面圖。 圖二A至圖二G揭示製造本發明之一種第一型局部氧化 矽基蕭特基屏障二極體的製程步驟及其簡要剖面圖。 圖三A至圖三F揭示製造本發明之一種第二型局部氧化 矽基蕭特基屏障二極體之接續圖二B的製程步驟及其簡要 剖面圖。 圖四A及圖四B揭示製造本發明之一種第三型局部氧化 矽基蕭特基屏障二極體之接續圖二E的簡化製程步驟及其 簡要剖面圖。 圖五A及圖五B揭示製造本發明之一種第四型局部氧化 矽基蕭特基屏障二極體之接續圖三D的簡化製程步驟及其 簡要剖面圖。 代表圖號說明:Page 19 1283929 Brief Description of the Drawings Figure 1 shows a schematic cross-sectional view of a Schottky barrier contact structure of the prior art. Figures 2A through 2G illustrate the process steps and a cross-sectional view of a first type of localized yttrium-based Schottky barrier diode of the present invention. Fig. 3A to Fig. 3F show the process steps and a schematic cross-sectional view of the second embodiment of the second type of localized cerium oxide Schottky barrier diode of the present invention. Fig. 4A and Fig. 4B show a simplified process step and a schematic cross-sectional view of the second embodiment of the third type of localized yttrium oxide Schottky barrier diode of the present invention. Fig. 5A and Fig. 5B show a simplified process step and a schematic cross-sectional view of the fourth embodiment of the fourth type of localized yttrium oxide Schottky barrier diode of the present invention. Representative figure description:

2 0 0 高摻雜矽基板 2 0 2 墊氧化物層 202b 熱二氧化矽層 2 0 3 罩幕氮化矽層 2 0 4 a / 2 0 4 c 外部局部氧化矽 204b/204d 内部局部氧化矽 205a 離子佈植區 206a 金屬矽化物層 201 淡摻雜磊晶矽層 2 0 2 a 成形墊氧化物層 2 0 2 c 成形熱二氧化矽層 2 0 3 a 成形罩幕氮化矽層 場氧化物層 場氧化物層 2 0 5 b 凸出擴散保護環 207a 成形金屬層2 0 0 highly doped ruthenium substrate 2 0 2 pad oxide layer 202b thermal ruthenium dioxide layer 2 0 3 mask ruthenium nitride layer 2 0 4 a / 2 0 4 c external local ruthenium oxide 204b/204d internal local ruthenium oxide 205a ion implantation zone 206a metal telluride layer 201 lightly doped epitaxial layer 2 0 2 a shaped pad oxide layer 2 0 2 c shaped hot ruthenium dioxide layer 2 0 3 a forming mask nitride tantalum layer field oxidation Layer field oxide layer 2 0 5 b convex diffusion protection ring 207a shaped metal layer

第20頁 1283929 圖式簡單說明 2 0 8a/ 2 0 8b 補償離子佈植區 208c/208d/208e/208f 補償擴散層 2 0 9 覆蓋介電層 209a成形覆蓋介電層Page 20 1283929 Brief description of the diagram 2 0 8a/ 2 0 8b Compensating ion implantation area 208c/208d/208e/208f Compensating diffusion layer 2 0 9 Covering dielectric layer 209a Forming covering dielectric layer

HIHI

Claims (1)

1283929 六、申請專利範圍 1 . 一種局部氧化矽基蕭特基屏障二極體,至少包含: 一種第一導電型的一個半導體基板,其中該半導體基 板至少包含一個淡摻雜磊晶半導體層形成於一個高摻雜半 導體板之上; 一種第二導電型的一個凸出擴散保護環形成於一個外 部局部氧化矽場氧化物層及一個内部局部氧化矽場氧化物 層之間的該淡摻雜磊晶半導體層的一個部份表面之内,其 中該内部局部氧化矽場氧化物層係加予备除來形成由該凸 出擴散保護環所包圍的一個凹陷半導體基板;以及 一個金屬矽化物層形成於由該外部局部氧化矽場氧化 物層所包圍之該凸出擴散保護環的一個内部表面部份及由 該凸出擴散保護環所包圍的該凹陷半導體基板之上。 2. 如申請專利範圍第1項所述之局部氧化矽基蕭特基屏障 二極體,其中上述之外部及内部局部氧化矽場氧化物層係 經由一種局部氧化矽(LOCOS)製程於一個水蒸氣或溼氧的 環境下來氧化。 3. 如申請專利範圍第1項所述之局部氧化矽基蕭特基屏障 二極體,其中上述之凸出擴散保護環至少包含一個高摻雜 擴散保護環、一個中度摻雜擴散保護環或一個高摻雜擴散 保護環形成於一個中度摻雜擴散保護環之内。 4 · 如申請專利範圍第1項所述之局部氧化矽基蕭特基屏障1283929 6. Patent application scope 1. A localized yttrium-based Schottky barrier diode comprising at least: a semiconductor substrate of a first conductivity type, wherein the semiconductor substrate comprises at least one lightly doped epitaxial semiconductor layer formed on a highly doped semiconductor plate; a convex diffusion protection ring of a second conductivity type formed between an external localized yttrium oxide oxide layer and an internal localized yttrium oxide oxide layer Within a portion of the surface of the crystalline semiconductor layer, wherein the internal localized yttrium oxide oxide layer is additionally provided to form a recessed semiconductor substrate surrounded by the raised diffusion protection ring; and a metal halide layer is formed An inner surface portion of the protruding diffusion protection ring surrounded by the outer partial oxidation oxide field oxide layer and the recessed semiconductor substrate surrounded by the convex diffusion protection ring. 2. The local cerium oxide-based Schottky barrier diode according to claim 1, wherein the external and internal localized yttrium oxide oxide layer is processed in a water via a local yttrium oxide (LOCOS) process. Oxidation in a vapor or wet oxygen environment. 3. The localized yttrium oxide Schottky barrier diode according to claim 1, wherein the protruding diffusion protection ring comprises at least one highly doped diffusion protection ring and one moderately doped diffusion protection ring. Or a highly doped diffusion protection ring is formed within a moderately doped diffusion protection ring. 4 · The local cerium oxide based Schottky barrier as described in claim 1 1283929 六、申請專利範圍 二極體,其中上述之凸出擴散保護環係以一種自動對準的 方式將摻雜質跨過位於該外部局部氧化矽場氧化物層及該 内部局部氧化矽場氧化物層之間的一個墊氧化物層佈植於 該淡摻雜磊晶半導體層的一個表面部份之内。 5. 如申請專利範圍第1項所述之局部氧化矽基蕭特基屏障 二極體,其中上述之凸出擴散保護環係以一種自動對準的 方式藉由一個液體源、一個固體源、或一個氣體源的一種 熱擴散製程透過位於該外部局部氧化矽場氧化物層及該内 部局部氧化矽場氧化物層之間的一個擴散窗來形成。 6. 如申請專利範圍第1項所述之局部氧化矽基蕭特基屏障 二極體,其中上述之金屬矽化物·層至少包含藉由一種自動 對準矽化製程所形成的一個耐高溫金屬矽化物層。 7. 如申請專利範圍第1項所述之局部氧化矽基蕭特基屏障 二極體,其中上述之第二導電型的一個補償離子佈植係用 來形成一個補償擴散層於該外部及内部局部氧化矽場氧化 物層之下的該淡摻雜半導體層之一個表面部份之内。 8. 一種局部氧化矽基蕭特基屏障二極體,至少包含: 一種第一導電型的一個半導體基板,其中該半導體基 板至少包含一個淡摻雜磊晶矽層形成於一個高摻雜矽基板 之上;1283929 6. Applying for a patent range diode, wherein the above-mentioned protruding diffusion protection ring oxidizes dopants across the external localized yttrium oxide oxide layer and the internal local yttrium oxide field in an automatic alignment manner. A pad oxide layer between the layers is implanted within a surface portion of the lightly doped epitaxial semiconductor layer. 5. The local yttrium oxide Schottky barrier diode of claim 1, wherein the bulging diffusion protection ring is in a self-aligned manner by a liquid source, a solid source, Or a thermal diffusion process of a gas source is formed through a diffusion window between the outer localized yttria oxide layer and the internal local yttrium oxide oxide layer. 6. The localized cerium oxide-based Schottky barrier diode of claim 1, wherein the metal halide layer comprises at least one refractory metal deuteration formed by an auto-alignment deuteration process. Layer of matter. 7. The local yttrium oxide Schottky barrier diode of claim 1, wherein a compensating ion implant of the second conductivity type is used to form a compensation diffusion layer on the exterior and interior A portion of the surface portion of the lightly doped semiconductor layer below the local oxide field oxide layer. A partial cerium oxide-based Schottky barrier diode comprising at least: a semiconductor substrate of a first conductivity type, wherein the semiconductor substrate comprises at least one lightly doped epitaxial layer formed on a highly doped germanium substrate Above 第23頁 1283929 六、申請專利範圍 一個擴散保護環區藉由一種局部氧化矽(LOCOS)製程 形成於一個外部局部氧化矽場氧化物層及一個内部局部氧 化矽場氧化物層之間,其中該擴散保護環區係以一種自動 對準的方式加予掺雜以形成一種第二導電型的一個凸出擴 散保護環於該淡摻雜磊晶矽層的一個表面部份之内; 一個凹陷半導體基板藉由去除該内部局部氧化矽場氧 化物層來形成; 一個耐高溫金屬矽化層形成於由該外部局部氧化矽場 氧化物層所包圍之該凸出擴散保護環的一個内部表面部份 及由該凸出擴散保護環所包圍之該凹陷半導體基板之上; 以及 一個成形金屬層至少形成於該耐高溫金屬矽化物層之 9.如申請專利範圍第8項所述之局部氧化矽基蕭特基屏障 二極體,其中上述之淡摻雜磊晶矽層具有一個摻雜質濃度 介於1 014/立方公分和1 017/立方公分之間及一個厚度介於2 微米和3 5微米之間。 1 0 ·如申請專利範圍第8項所述之局部氧化矽基蕭特基屏障 二極體,其中上述之外部及内部局部氧化矽場氧化物層藉 由該局部氧化矽(LOCOS) 製程來形成係在一個水蒸氣或溼 氧環境下成長介於6 0 0 0埃和1 0 0 0 0埃之間的一個厚度。Page 23 1283929 VI. Scope of Application A diffusion protection ring region is formed between an external localized yttrium oxide field layer and an internal local yttrium oxide field oxide layer by a LOCOS process. The diffusion protection ring region is doped in an automatic alignment manner to form a convex diffusion protection ring of a second conductivity type within a surface portion of the lightly doped epitaxial layer; a recessed semiconductor The substrate is formed by removing the inner partial yttrium oxide field oxide layer; a refractory metal deuterated layer is formed on an inner surface portion of the protruding diffusion protection ring surrounded by the outer partial yttrium oxide field oxide layer and a recessed semiconductor substrate surrounded by the protruding diffusion protection ring; and a shaped metal layer formed at least on the high temperature resistant metal halide layer. 9. The localized cerium oxide base according to claim 8 a barrier-based diode, wherein the lightly doped epitaxial layer has a doping concentration of 1 014 /cm ^ 3 and 1 017 / cubic centimeter And a thickness between between 2 microns and 35 microns. The local cerium oxide-based Schottky barrier diode according to claim 8, wherein the external and internal localized yttrium oxide oxide layer is formed by the local yttrium oxide (LOCOS) process. It is grown to a thickness between 600 Å and 1 00 Å in a water vapor or wet oxygen environment. 第24頁 1283929 六、申請專利範圍 1 1 .如申請專利範圍第8項所述之局部氧化矽基蕭特基屏障 二極體,其中上述之凸出擴散保護環包含一個高摻雜擴散 保護環、一個中度摻雜擴散保護環或一個高摻雜擴散保護 環形成於一個中度摻雜擴散保護環之内。 1 2.如申請專利範圍第8項所述之局部氧化矽基蕭特基屏障 二極體,其中一個補償擴散層係在未進行該局部氧化矽製 程之前跨過一個墊氧化層佈值該第二導電型的摻雜質於該 擴散保護環區之外的該淡摻雜磊晶矽層之一個表面部份。</ RTI> </ RTI> <RTIgt; </ RTI> <RTIgt; </ RTI> <RTIgt; </ RTI> <RTIgt; </ RTI> <RTIgt; </ RTI> <RTIgt; </ RTI> <RTIgt; A moderately doped diffusion protection ring or a highly doped diffusion protection ring is formed within a moderately doped diffusion protection ring. 1 2. The localized cerium oxide-based Schottky barrier diode according to claim 8 wherein one of the compensating diffusion layers is crossed by a pad oxide layer before the local cerium oxide process is performed. The doping of the two conductivity type is on a surface portion of the lightly doped epitaxial layer outside the diffusion protection ring region. 1 3.如申請專利範圍第8項所述之局部氧化矽基蕭特基屏障 二極體,其中上述之成形金屬層至少包含一個金屬層置於 一個障礙金屬層之上係形成於一個成形覆蓋介電層的一部 份表面及該金屬矽化物層之上。 1 4. 一種局部氧化矽基蕭特基屏障二極體,至少包含: 一種第一導電型的一個半導體基板,其中該半導體基 板至少包含一個淡摻雜磊晶矽層形成於一個高摻雜矽基板 之上;The localized yttrium-based Schottky barrier diode according to claim 8, wherein the formed metal layer comprises at least one metal layer disposed on a barrier metal layer and formed in a shaped covering a portion of the surface of the dielectric layer and the metal halide layer. 1 1. A partial cerium oxide-based Schottky barrier diode comprising at least: a semiconductor substrate of a first conductivity type, wherein the semiconductor substrate comprises at least one lightly doped epitaxial layer formed on a highly doped germanium Above the substrate; 一個擴散保護環區藉由一種局部氧化矽(LOCOS) 製程 於一個水蒸氣或溼氧環境下所形成的一個外部局部氧化矽 場氧化物層及一個内部局部氧化矽場氧化物層之間,其中 該擴散保護環區係以一種自動對準的方式利用離子佈植或 一種熱擴散製程來摻雜以形成一種第二導電型的一個凸出A diffusion protection ring region is formed by a localized yttria (LOCOS) process between an external localized yttrium oxide field layer and an internal local yttrium oxide field oxide layer formed in a water vapor or wet oxygen environment. The diffusion protection ring region is doped in an auto-aligned manner by ion implantation or a thermal diffusion process to form a protrusion of a second conductivity type 第25頁 1283929 六、申請專利範圍 擴散保護環於該淡摻雜磊晶矽層的一個表面部份之内; 一個凹陷半導體基板藉由去除該内部局部氧化矽場氧 化物層來形成,其中該凹陷半導體基板至少包含一個補償 擴散層形成於該淡摻雜磊晶矽層的一個表面部份之内; 一個耐高溫金屬矽化物層形成於由該外部局部氧化矽 場氧化物層所包圍的該凸出擴散保護環的一個内部表面部 份及由該凸出擴散保護環所包圍之該凹陷半導體基板之上 ,其中該耐高溫金屬矽化物層係利用一種自動對準矽化製 程來形成;以及 一個成形金屬層至少形成於一個成形覆蓋介電層的一 部份表面及該耐高溫金屬矽化物層之上。 1 5.如申請專利範圍第1 4項所述之局部氧化矽基蕭特基屏 障二極體,其中上述之成形覆蓋介電層至少包含氮化矽係 形成於該凸出擴散保護環之上的一個熱二氧化矽層之一個 外部表面部份及該外部局部氧化矽場氧化物層的一部份表 面之上。 16. 如申請專利範圍第1 4項所述之局部氧化矽基蕭特基屏 障二極體,其中上述之熱擴散製程至少包含利用一個液體 源、一個固體源或一個氣體源的一種熱摻雜製程。 17. 如申請專利範圍第1 4項所述之局部氧化矽基蕭特基屏 障二極體,其中上述之擴散保護環區係藉由一個第一罩幕Page 25 1283929 6. The patent application scope diffusion protection ring is within a surface portion of the lightly doped epitaxial layer; a recessed semiconductor substrate is formed by removing the internal local oxide field oxide layer, wherein The recessed semiconductor substrate includes at least one compensation diffusion layer formed in a surface portion of the lightly doped epitaxial layer; a high temperature resistant metal telluride layer is formed on the outer partial oxide oxide field oxide layer Extending an inner surface portion of the diffusion protection ring and the recessed semiconductor substrate surrounded by the protruding diffusion protection ring, wherein the high temperature resistant metal telluride layer is formed by an automatic alignment deuteration process; and The formed metal layer is formed on at least a portion of the surface of the shaped cover dielectric layer and the high temperature resistant metal telluride layer. 1. The local yttrium oxide Schottky barrier diode of claim 14, wherein the shaped overlying dielectric layer comprises at least a tantalum nitride system formed over the convex diffusion protection ring An outer surface portion of a thermal ruthenium dioxide layer and a portion of the surface of the outer local yttrium oxide oxide layer. 16. The localized yttrium-based Schottky barrier diode of claim 14, wherein the thermal diffusion process comprises at least one thermal doping using a liquid source, a solid source, or a gas source. Process. 17. The localized yttrium-based Schottky barrier diode of claim 14, wherein the diffusion protection ring region is provided by a first mask 第26頁 1283929 六、申請專利範圍 光阻步驟將一個罩幕氮化矽層置於一個墊(p a d ) 氧化物層 之上加予成形來定義。 18. 如申請專利範圍第1 4項所述之局部氧化矽基蕭特基屏 障二極體,其中上述之内部局部氧化矽場氧化物層係在摻 雜該凸出擴散保護環之後利用一個第二罩幕光阻步驟來加 予去除。 19. 如申請專利範圍第1 4項所述之局部氧化矽基蕭特基屏 障二極體,其中上述之成形金屬層至少包含一個銀(Ag)、 鋁(A1)或金(Au)層置於一個障礙金屬層之上係藉由一個第 三罩幕光阻步驟來形成於該成形覆蓋介電層的一部份表面 及該耐高溫金屬矽化物層之上。 2 0. 如申請專利範圍第1 4項所述之局部氧化矽基蕭特基屏 障二極體,其中上述之補償擴散層係在未進行該局部氧化 矽層製程之前跨過一個墊氧化物層佈植該第二導電型的摻 雜質於該擴散保護環區之外的該淡摻雜磊晶矽層的表面部 份之内。Page 26 1283929 VI. Scope of Application The photoresist step is defined by placing a masked tantalum nitride layer on top of a pad (p a d ) oxide layer. 18. The local yttrium oxide Schottky barrier diode according to claim 14, wherein the internal partial oxidized lanthanum oxide layer is utilized after doping the bulging diffusion protection ring. The second mask photoresist step is added for removal. 19. The localized cerium oxide-based Schottky barrier diode according to claim 14, wherein the shaped metal layer comprises at least one layer of silver (Ag), aluminum (A1) or gold (Au). A portion of the barrier metal layer is formed on a portion of the surface of the shaped capping dielectric layer and the refractory metal germanide layer by a third mask photoresist step. The local yttrium oxide Schottky barrier diode of claim 14, wherein the compensating diffusion layer spans a pad oxide layer before the local yttrium oxide layer process is performed. The dopant of the second conductivity type is implanted within a surface portion of the lightly doped epitaxial layer outside the diffusion protection ring region. 第27頁Page 27
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TWI743818B (en) * 2020-06-02 2021-10-21 台灣半導體股份有限公司 Schottky diode with multiple guard ring structures

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